| blob | dc70de2c57414aa0db7b61554f2df9228448fb19 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512fp16 -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK-32
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16 -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK-64
5 define i32 @test_f16_oeq_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
6 ; CHECK-32-LABEL: test_f16_oeq_q:
7 ; CHECK-32: # %bb.0:
8 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
9 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
10 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
11 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
12 ; CHECK-32-NEXT: cmovnel %eax, %ecx
13 ; CHECK-32-NEXT: cmovpl %eax, %ecx
14 ; CHECK-32-NEXT: movl (%ecx), %eax
15 ; CHECK-32-NEXT: retl
16 ;
17 ; CHECK-64-LABEL: test_f16_oeq_q:
18 ; CHECK-64: # %bb.0:
19 ; CHECK-64-NEXT: movl %edi, %eax
20 ; CHECK-64-NEXT: vucomish %xmm1, %xmm0
21 ; CHECK-64-NEXT: cmovnel %esi, %eax
22 ; CHECK-64-NEXT: cmovpl %esi, %eax
23 ; CHECK-64-NEXT: retq
24 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
25 half %f1, half %f2, metadata !"oeq",
26 metadata !"fpexcept.strict") #0
27 %res = select i1 %cond, i32 %a, i32 %b
28 ret i32 %res
29 }
31 define i32 @test_f16_ogt_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
32 ; CHECK-32-LABEL: test_f16_ogt_q:
33 ; CHECK-32: # %bb.0:
34 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
35 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
36 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
37 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
38 ; CHECK-32-NEXT: cmoval %eax, %ecx
39 ; CHECK-32-NEXT: movl (%ecx), %eax
40 ; CHECK-32-NEXT: retl
41 ;
42 ; CHECK-64-LABEL: test_f16_ogt_q:
43 ; CHECK-64: # %bb.0:
44 ; CHECK-64-NEXT: movl %edi, %eax
45 ; CHECK-64-NEXT: vucomish %xmm1, %xmm0
46 ; CHECK-64-NEXT: cmovbel %esi, %eax
47 ; CHECK-64-NEXT: retq
48 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
49 half %f1, half %f2, metadata !"ogt",
50 metadata !"fpexcept.strict") #0
51 %res = select i1 %cond, i32 %a, i32 %b
52 ret i32 %res
53 }
55 define i32 @test_f16_oge_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
56 ; CHECK-32-LABEL: test_f16_oge_q:
57 ; CHECK-32: # %bb.0:
58 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
59 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
60 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
61 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
62 ; CHECK-32-NEXT: cmovael %eax, %ecx
63 ; CHECK-32-NEXT: movl (%ecx), %eax
64 ; CHECK-32-NEXT: retl
65 ;
66 ; CHECK-64-LABEL: test_f16_oge_q:
67 ; CHECK-64: # %bb.0:
68 ; CHECK-64-NEXT: movl %edi, %eax
69 ; CHECK-64-NEXT: vucomish %xmm1, %xmm0
70 ; CHECK-64-NEXT: cmovbl %esi, %eax
71 ; CHECK-64-NEXT: retq
72 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
73 half %f1, half %f2, metadata !"oge",
74 metadata !"fpexcept.strict") #0
75 %res = select i1 %cond, i32 %a, i32 %b
76 ret i32 %res
77 }
79 define i32 @test_f16_olt_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
80 ; CHECK-32-LABEL: test_f16_olt_q:
81 ; CHECK-32: # %bb.0:
82 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
83 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
84 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
85 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
86 ; CHECK-32-NEXT: cmoval %eax, %ecx
87 ; CHECK-32-NEXT: movl (%ecx), %eax
88 ; CHECK-32-NEXT: retl
89 ;
90 ; CHECK-64-LABEL: test_f16_olt_q:
91 ; CHECK-64: # %bb.0:
92 ; CHECK-64-NEXT: movl %edi, %eax
93 ; CHECK-64-NEXT: vucomish %xmm0, %xmm1
94 ; CHECK-64-NEXT: cmovbel %esi, %eax
95 ; CHECK-64-NEXT: retq
96 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
97 half %f1, half %f2, metadata !"olt",
98 metadata !"fpexcept.strict") #0
99 %res = select i1 %cond, i32 %a, i32 %b
100 ret i32 %res
101 }
103 define i32 @test_f16_ole_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
104 ; CHECK-32-LABEL: test_f16_ole_q:
105 ; CHECK-32: # %bb.0:
106 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
107 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
108 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
109 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
110 ; CHECK-32-NEXT: cmovael %eax, %ecx
111 ; CHECK-32-NEXT: movl (%ecx), %eax
112 ; CHECK-32-NEXT: retl
113 ;
114 ; CHECK-64-LABEL: test_f16_ole_q:
115 ; CHECK-64: # %bb.0:
116 ; CHECK-64-NEXT: movl %edi, %eax
117 ; CHECK-64-NEXT: vucomish %xmm0, %xmm1
118 ; CHECK-64-NEXT: cmovbl %esi, %eax
119 ; CHECK-64-NEXT: retq
120 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
121 half %f1, half %f2, metadata !"ole",
122 metadata !"fpexcept.strict") #0
123 %res = select i1 %cond, i32 %a, i32 %b
124 ret i32 %res
125 }
127 define i32 @test_f16_one_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
128 ; CHECK-32-LABEL: test_f16_one_q:
129 ; CHECK-32: # %bb.0:
130 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
131 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
132 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
133 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
134 ; CHECK-32-NEXT: cmovnel %eax, %ecx
135 ; CHECK-32-NEXT: movl (%ecx), %eax
136 ; CHECK-32-NEXT: retl
137 ;
138 ; CHECK-64-LABEL: test_f16_one_q:
139 ; CHECK-64: # %bb.0:
140 ; CHECK-64-NEXT: movl %edi, %eax
141 ; CHECK-64-NEXT: vucomish %xmm1, %xmm0
142 ; CHECK-64-NEXT: cmovel %esi, %eax
143 ; CHECK-64-NEXT: retq
144 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
145 half %f1, half %f2, metadata !"one",
146 metadata !"fpexcept.strict") #0
147 %res = select i1 %cond, i32 %a, i32 %b
148 ret i32 %res
149 }
151 define i32 @test_f16_ord_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
152 ; CHECK-32-LABEL: test_f16_ord_q:
153 ; CHECK-32: # %bb.0:
154 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
155 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
156 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
157 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
158 ; CHECK-32-NEXT: cmovnpl %eax, %ecx
159 ; CHECK-32-NEXT: movl (%ecx), %eax
160 ; CHECK-32-NEXT: retl
161 ;
162 ; CHECK-64-LABEL: test_f16_ord_q:
163 ; CHECK-64: # %bb.0:
164 ; CHECK-64-NEXT: movl %edi, %eax
165 ; CHECK-64-NEXT: vucomish %xmm1, %xmm0
166 ; CHECK-64-NEXT: cmovpl %esi, %eax
167 ; CHECK-64-NEXT: retq
168 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
169 half %f1, half %f2, metadata !"ord",
170 metadata !"fpexcept.strict") #0
171 %res = select i1 %cond, i32 %a, i32 %b
172 ret i32 %res
173 }
175 define i32 @test_f16_ueq_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
176 ; CHECK-32-LABEL: test_f16_ueq_q:
177 ; CHECK-32: # %bb.0:
178 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
179 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
180 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
181 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
182 ; CHECK-32-NEXT: cmovel %eax, %ecx
183 ; CHECK-32-NEXT: movl (%ecx), %eax
184 ; CHECK-32-NEXT: retl
185 ;
186 ; CHECK-64-LABEL: test_f16_ueq_q:
187 ; CHECK-64: # %bb.0:
188 ; CHECK-64-NEXT: movl %edi, %eax
189 ; CHECK-64-NEXT: vucomish %xmm1, %xmm0
190 ; CHECK-64-NEXT: cmovnel %esi, %eax
191 ; CHECK-64-NEXT: retq
192 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
193 half %f1, half %f2, metadata !"ueq",
194 metadata !"fpexcept.strict") #0
195 %res = select i1 %cond, i32 %a, i32 %b
196 ret i32 %res
197 }
199 define i32 @test_f16_ugt_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
200 ; CHECK-32-LABEL: test_f16_ugt_q:
201 ; CHECK-32: # %bb.0:
202 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
203 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
204 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
205 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
206 ; CHECK-32-NEXT: cmovbl %eax, %ecx
207 ; CHECK-32-NEXT: movl (%ecx), %eax
208 ; CHECK-32-NEXT: retl
209 ;
210 ; CHECK-64-LABEL: test_f16_ugt_q:
211 ; CHECK-64: # %bb.0:
212 ; CHECK-64-NEXT: movl %edi, %eax
213 ; CHECK-64-NEXT: vucomish %xmm0, %xmm1
214 ; CHECK-64-NEXT: cmovael %esi, %eax
215 ; CHECK-64-NEXT: retq
216 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
217 half %f1, half %f2, metadata !"ugt",
218 metadata !"fpexcept.strict") #0
219 %res = select i1 %cond, i32 %a, i32 %b
220 ret i32 %res
221 }
223 define i32 @test_f16_uge_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
224 ; CHECK-32-LABEL: test_f16_uge_q:
225 ; CHECK-32: # %bb.0:
226 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
227 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
228 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
229 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
230 ; CHECK-32-NEXT: cmovbel %eax, %ecx
231 ; CHECK-32-NEXT: movl (%ecx), %eax
232 ; CHECK-32-NEXT: retl
233 ;
234 ; CHECK-64-LABEL: test_f16_uge_q:
235 ; CHECK-64: # %bb.0:
236 ; CHECK-64-NEXT: movl %edi, %eax
237 ; CHECK-64-NEXT: vucomish %xmm0, %xmm1
238 ; CHECK-64-NEXT: cmoval %esi, %eax
239 ; CHECK-64-NEXT: retq
240 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
241 half %f1, half %f2, metadata !"uge",
242 metadata !"fpexcept.strict") #0
243 %res = select i1 %cond, i32 %a, i32 %b
244 ret i32 %res
245 }
247 define i32 @test_f16_ult_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
248 ; CHECK-32-LABEL: test_f16_ult_q:
249 ; CHECK-32: # %bb.0:
250 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
251 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
252 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
253 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
254 ; CHECK-32-NEXT: cmovbl %eax, %ecx
255 ; CHECK-32-NEXT: movl (%ecx), %eax
256 ; CHECK-32-NEXT: retl
257 ;
258 ; CHECK-64-LABEL: test_f16_ult_q:
259 ; CHECK-64: # %bb.0:
260 ; CHECK-64-NEXT: movl %edi, %eax
261 ; CHECK-64-NEXT: vucomish %xmm1, %xmm0
262 ; CHECK-64-NEXT: cmovael %esi, %eax
263 ; CHECK-64-NEXT: retq
264 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
265 half %f1, half %f2, metadata !"ult",
266 metadata !"fpexcept.strict") #0
267 %res = select i1 %cond, i32 %a, i32 %b
268 ret i32 %res
269 }
271 define i32 @test_f16_ule_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
272 ; CHECK-32-LABEL: test_f16_ule_q:
273 ; CHECK-32: # %bb.0:
274 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
275 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
276 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
277 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
278 ; CHECK-32-NEXT: cmovbel %eax, %ecx
279 ; CHECK-32-NEXT: movl (%ecx), %eax
280 ; CHECK-32-NEXT: retl
281 ;
282 ; CHECK-64-LABEL: test_f16_ule_q:
283 ; CHECK-64: # %bb.0:
284 ; CHECK-64-NEXT: movl %edi, %eax
285 ; CHECK-64-NEXT: vucomish %xmm1, %xmm0
286 ; CHECK-64-NEXT: cmoval %esi, %eax
287 ; CHECK-64-NEXT: retq
288 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
289 half %f1, half %f2, metadata !"ule",
290 metadata !"fpexcept.strict") #0
291 %res = select i1 %cond, i32 %a, i32 %b
292 ret i32 %res
293 }
295 define i32 @test_f16_une_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
296 ; CHECK-32-LABEL: test_f16_une_q:
297 ; CHECK-32: # %bb.0:
298 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
299 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
300 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
301 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
302 ; CHECK-32-NEXT: cmovnel %eax, %ecx
303 ; CHECK-32-NEXT: cmovpl %eax, %ecx
304 ; CHECK-32-NEXT: movl (%ecx), %eax
305 ; CHECK-32-NEXT: retl
306 ;
307 ; CHECK-64-LABEL: test_f16_une_q:
308 ; CHECK-64: # %bb.0:
309 ; CHECK-64-NEXT: movl %esi, %eax
310 ; CHECK-64-NEXT: vucomish %xmm1, %xmm0
311 ; CHECK-64-NEXT: cmovnel %edi, %eax
312 ; CHECK-64-NEXT: cmovpl %edi, %eax
313 ; CHECK-64-NEXT: retq
314 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
315 half %f1, half %f2, metadata !"une",
316 metadata !"fpexcept.strict") #0
317 %res = select i1 %cond, i32 %a, i32 %b
318 ret i32 %res
319 }
321 define i32 @test_f16_uno_q(i32 %a, i32 %b, half %f1, half %f2) #0 {
322 ; CHECK-32-LABEL: test_f16_uno_q:
323 ; CHECK-32: # %bb.0:
324 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
325 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
326 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
327 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
328 ; CHECK-32-NEXT: cmovpl %eax, %ecx
329 ; CHECK-32-NEXT: movl (%ecx), %eax
330 ; CHECK-32-NEXT: retl
331 ;
332 ; CHECK-64-LABEL: test_f16_uno_q:
333 ; CHECK-64: # %bb.0:
334 ; CHECK-64-NEXT: movl %edi, %eax
335 ; CHECK-64-NEXT: vucomish %xmm1, %xmm0
336 ; CHECK-64-NEXT: cmovnpl %esi, %eax
337 ; CHECK-64-NEXT: retq
338 %cond = call i1 @llvm.experimental.constrained.fcmp.f16(
339 half %f1, half %f2, metadata !"uno",
340 metadata !"fpexcept.strict") #0
341 %res = select i1 %cond, i32 %a, i32 %b
342 ret i32 %res
343 }
345 define i32 @test_f16_oeq_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
346 ; CHECK-32-LABEL: test_f16_oeq_s:
347 ; CHECK-32: # %bb.0:
348 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
349 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
350 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
351 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
352 ; CHECK-32-NEXT: cmovnel %eax, %ecx
353 ; CHECK-32-NEXT: cmovpl %eax, %ecx
354 ; CHECK-32-NEXT: movl (%ecx), %eax
355 ; CHECK-32-NEXT: retl
356 ;
357 ; CHECK-64-LABEL: test_f16_oeq_s:
358 ; CHECK-64: # %bb.0:
359 ; CHECK-64-NEXT: movl %edi, %eax
360 ; CHECK-64-NEXT: vcomish %xmm1, %xmm0
361 ; CHECK-64-NEXT: cmovnel %esi, %eax
362 ; CHECK-64-NEXT: cmovpl %esi, %eax
363 ; CHECK-64-NEXT: retq
364 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
365 half %f1, half %f2, metadata !"oeq",
366 metadata !"fpexcept.strict") #0
367 %res = select i1 %cond, i32 %a, i32 %b
368 ret i32 %res
369 }
371 define i32 @test_f16_ogt_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
372 ; CHECK-32-LABEL: test_f16_ogt_s:
373 ; CHECK-32: # %bb.0:
374 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
375 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
376 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
377 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
378 ; CHECK-32-NEXT: cmoval %eax, %ecx
379 ; CHECK-32-NEXT: movl (%ecx), %eax
380 ; CHECK-32-NEXT: retl
381 ;
382 ; CHECK-64-LABEL: test_f16_ogt_s:
383 ; CHECK-64: # %bb.0:
384 ; CHECK-64-NEXT: movl %edi, %eax
385 ; CHECK-64-NEXT: vcomish %xmm1, %xmm0
386 ; CHECK-64-NEXT: cmovbel %esi, %eax
387 ; CHECK-64-NEXT: retq
388 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
389 half %f1, half %f2, metadata !"ogt",
390 metadata !"fpexcept.strict") #0
391 %res = select i1 %cond, i32 %a, i32 %b
392 ret i32 %res
393 }
395 define i32 @test_f16_oge_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
396 ; CHECK-32-LABEL: test_f16_oge_s:
397 ; CHECK-32: # %bb.0:
398 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
399 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
400 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
401 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
402 ; CHECK-32-NEXT: cmovael %eax, %ecx
403 ; CHECK-32-NEXT: movl (%ecx), %eax
404 ; CHECK-32-NEXT: retl
405 ;
406 ; CHECK-64-LABEL: test_f16_oge_s:
407 ; CHECK-64: # %bb.0:
408 ; CHECK-64-NEXT: movl %edi, %eax
409 ; CHECK-64-NEXT: vcomish %xmm1, %xmm0
410 ; CHECK-64-NEXT: cmovbl %esi, %eax
411 ; CHECK-64-NEXT: retq
412 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
413 half %f1, half %f2, metadata !"oge",
414 metadata !"fpexcept.strict") #0
415 %res = select i1 %cond, i32 %a, i32 %b
416 ret i32 %res
417 }
419 define i32 @test_f16_olt_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
420 ; CHECK-32-LABEL: test_f16_olt_s:
421 ; CHECK-32: # %bb.0:
422 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
423 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
424 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
425 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
426 ; CHECK-32-NEXT: cmoval %eax, %ecx
427 ; CHECK-32-NEXT: movl (%ecx), %eax
428 ; CHECK-32-NEXT: retl
429 ;
430 ; CHECK-64-LABEL: test_f16_olt_s:
431 ; CHECK-64: # %bb.0:
432 ; CHECK-64-NEXT: movl %edi, %eax
433 ; CHECK-64-NEXT: vcomish %xmm0, %xmm1
434 ; CHECK-64-NEXT: cmovbel %esi, %eax
435 ; CHECK-64-NEXT: retq
436 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
437 half %f1, half %f2, metadata !"olt",
438 metadata !"fpexcept.strict") #0
439 %res = select i1 %cond, i32 %a, i32 %b
440 ret i32 %res
441 }
443 define i32 @test_f16_ole_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
444 ; CHECK-32-LABEL: test_f16_ole_s:
445 ; CHECK-32: # %bb.0:
446 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
447 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
448 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
449 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
450 ; CHECK-32-NEXT: cmovael %eax, %ecx
451 ; CHECK-32-NEXT: movl (%ecx), %eax
452 ; CHECK-32-NEXT: retl
453 ;
454 ; CHECK-64-LABEL: test_f16_ole_s:
455 ; CHECK-64: # %bb.0:
456 ; CHECK-64-NEXT: movl %edi, %eax
457 ; CHECK-64-NEXT: vcomish %xmm0, %xmm1
458 ; CHECK-64-NEXT: cmovbl %esi, %eax
459 ; CHECK-64-NEXT: retq
460 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
461 half %f1, half %f2, metadata !"ole",
462 metadata !"fpexcept.strict") #0
463 %res = select i1 %cond, i32 %a, i32 %b
464 ret i32 %res
465 }
467 define i32 @test_f16_one_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
468 ; CHECK-32-LABEL: test_f16_one_s:
469 ; CHECK-32: # %bb.0:
470 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
471 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
472 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
473 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
474 ; CHECK-32-NEXT: cmovnel %eax, %ecx
475 ; CHECK-32-NEXT: movl (%ecx), %eax
476 ; CHECK-32-NEXT: retl
477 ;
478 ; CHECK-64-LABEL: test_f16_one_s:
479 ; CHECK-64: # %bb.0:
480 ; CHECK-64-NEXT: movl %edi, %eax
481 ; CHECK-64-NEXT: vcomish %xmm1, %xmm0
482 ; CHECK-64-NEXT: cmovel %esi, %eax
483 ; CHECK-64-NEXT: retq
484 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
485 half %f1, half %f2, metadata !"one",
486 metadata !"fpexcept.strict") #0
487 %res = select i1 %cond, i32 %a, i32 %b
488 ret i32 %res
489 }
491 define i32 @test_f16_ord_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
492 ; CHECK-32-LABEL: test_f16_ord_s:
493 ; CHECK-32: # %bb.0:
494 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
495 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
496 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
497 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
498 ; CHECK-32-NEXT: cmovnpl %eax, %ecx
499 ; CHECK-32-NEXT: movl (%ecx), %eax
500 ; CHECK-32-NEXT: retl
501 ;
502 ; CHECK-64-LABEL: test_f16_ord_s:
503 ; CHECK-64: # %bb.0:
504 ; CHECK-64-NEXT: movl %edi, %eax
505 ; CHECK-64-NEXT: vcomish %xmm1, %xmm0
506 ; CHECK-64-NEXT: cmovpl %esi, %eax
507 ; CHECK-64-NEXT: retq
508 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
509 half %f1, half %f2, metadata !"ord",
510 metadata !"fpexcept.strict") #0
511 %res = select i1 %cond, i32 %a, i32 %b
512 ret i32 %res
513 }
515 define i32 @test_f16_ueq_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
516 ; CHECK-32-LABEL: test_f16_ueq_s:
517 ; CHECK-32: # %bb.0:
518 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
519 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
520 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
521 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
522 ; CHECK-32-NEXT: cmovel %eax, %ecx
523 ; CHECK-32-NEXT: movl (%ecx), %eax
524 ; CHECK-32-NEXT: retl
525 ;
526 ; CHECK-64-LABEL: test_f16_ueq_s:
527 ; CHECK-64: # %bb.0:
528 ; CHECK-64-NEXT: movl %edi, %eax
529 ; CHECK-64-NEXT: vcomish %xmm1, %xmm0
530 ; CHECK-64-NEXT: cmovnel %esi, %eax
531 ; CHECK-64-NEXT: retq
532 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
533 half %f1, half %f2, metadata !"ueq",
534 metadata !"fpexcept.strict") #0
535 %res = select i1 %cond, i32 %a, i32 %b
536 ret i32 %res
537 }
539 define i32 @test_f16_ugt_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
540 ; CHECK-32-LABEL: test_f16_ugt_s:
541 ; CHECK-32: # %bb.0:
542 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
543 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
544 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
545 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
546 ; CHECK-32-NEXT: cmovbl %eax, %ecx
547 ; CHECK-32-NEXT: movl (%ecx), %eax
548 ; CHECK-32-NEXT: retl
549 ;
550 ; CHECK-64-LABEL: test_f16_ugt_s:
551 ; CHECK-64: # %bb.0:
552 ; CHECK-64-NEXT: movl %edi, %eax
553 ; CHECK-64-NEXT: vcomish %xmm0, %xmm1
554 ; CHECK-64-NEXT: cmovael %esi, %eax
555 ; CHECK-64-NEXT: retq
556 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
557 half %f1, half %f2, metadata !"ugt",
558 metadata !"fpexcept.strict") #0
559 %res = select i1 %cond, i32 %a, i32 %b
560 ret i32 %res
561 }
563 define i32 @test_f16_uge_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
564 ; CHECK-32-LABEL: test_f16_uge_s:
565 ; CHECK-32: # %bb.0:
566 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
567 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
568 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
569 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
570 ; CHECK-32-NEXT: cmovbel %eax, %ecx
571 ; CHECK-32-NEXT: movl (%ecx), %eax
572 ; CHECK-32-NEXT: retl
573 ;
574 ; CHECK-64-LABEL: test_f16_uge_s:
575 ; CHECK-64: # %bb.0:
576 ; CHECK-64-NEXT: movl %edi, %eax
577 ; CHECK-64-NEXT: vcomish %xmm0, %xmm1
578 ; CHECK-64-NEXT: cmoval %esi, %eax
579 ; CHECK-64-NEXT: retq
580 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
581 half %f1, half %f2, metadata !"uge",
582 metadata !"fpexcept.strict") #0
583 %res = select i1 %cond, i32 %a, i32 %b
584 ret i32 %res
585 }
587 define i32 @test_f16_ult_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
588 ; CHECK-32-LABEL: test_f16_ult_s:
589 ; CHECK-32: # %bb.0:
590 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
591 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
592 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
593 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
594 ; CHECK-32-NEXT: cmovbl %eax, %ecx
595 ; CHECK-32-NEXT: movl (%ecx), %eax
596 ; CHECK-32-NEXT: retl
597 ;
598 ; CHECK-64-LABEL: test_f16_ult_s:
599 ; CHECK-64: # %bb.0:
600 ; CHECK-64-NEXT: movl %edi, %eax
601 ; CHECK-64-NEXT: vcomish %xmm1, %xmm0
602 ; CHECK-64-NEXT: cmovael %esi, %eax
603 ; CHECK-64-NEXT: retq
604 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
605 half %f1, half %f2, metadata !"ult",
606 metadata !"fpexcept.strict") #0
607 %res = select i1 %cond, i32 %a, i32 %b
608 ret i32 %res
609 }
611 define i32 @test_f16_ule_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
612 ; CHECK-32-LABEL: test_f16_ule_s:
613 ; CHECK-32: # %bb.0:
614 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
615 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
616 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
617 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
618 ; CHECK-32-NEXT: cmovbel %eax, %ecx
619 ; CHECK-32-NEXT: movl (%ecx), %eax
620 ; CHECK-32-NEXT: retl
621 ;
622 ; CHECK-64-LABEL: test_f16_ule_s:
623 ; CHECK-64: # %bb.0:
624 ; CHECK-64-NEXT: movl %edi, %eax
625 ; CHECK-64-NEXT: vcomish %xmm1, %xmm0
626 ; CHECK-64-NEXT: cmoval %esi, %eax
627 ; CHECK-64-NEXT: retq
628 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
629 half %f1, half %f2, metadata !"ule",
630 metadata !"fpexcept.strict") #0
631 %res = select i1 %cond, i32 %a, i32 %b
632 ret i32 %res
633 }
635 define i32 @test_f16_une_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
636 ; CHECK-32-LABEL: test_f16_une_s:
637 ; CHECK-32: # %bb.0:
638 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
639 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
640 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
641 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
642 ; CHECK-32-NEXT: cmovnel %eax, %ecx
643 ; CHECK-32-NEXT: cmovpl %eax, %ecx
644 ; CHECK-32-NEXT: movl (%ecx), %eax
645 ; CHECK-32-NEXT: retl
646 ;
647 ; CHECK-64-LABEL: test_f16_une_s:
648 ; CHECK-64: # %bb.0:
649 ; CHECK-64-NEXT: movl %esi, %eax
650 ; CHECK-64-NEXT: vcomish %xmm1, %xmm0
651 ; CHECK-64-NEXT: cmovnel %edi, %eax
652 ; CHECK-64-NEXT: cmovpl %edi, %eax
653 ; CHECK-64-NEXT: retq
654 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
655 half %f1, half %f2, metadata !"une",
656 metadata !"fpexcept.strict") #0
657 %res = select i1 %cond, i32 %a, i32 %b
658 ret i32 %res
659 }
661 define i32 @test_f16_uno_s(i32 %a, i32 %b, half %f1, half %f2) #0 {
662 ; CHECK-32-LABEL: test_f16_uno_s:
663 ; CHECK-32: # %bb.0:
664 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
665 ; CHECK-32-NEXT: vcomish {{[0-9]+}}(%esp), %xmm0
666 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
667 ; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
668 ; CHECK-32-NEXT: cmovpl %eax, %ecx
669 ; CHECK-32-NEXT: movl (%ecx), %eax
670 ; CHECK-32-NEXT: retl
671 ;
672 ; CHECK-64-LABEL: test_f16_uno_s:
673 ; CHECK-64: # %bb.0:
674 ; CHECK-64-NEXT: movl %edi, %eax
675 ; CHECK-64-NEXT: vcomish %xmm1, %xmm0
676 ; CHECK-64-NEXT: cmovnpl %esi, %eax
677 ; CHECK-64-NEXT: retq
678 %cond = call i1 @llvm.experimental.constrained.fcmps.f16(
679 half %f1, half %f2, metadata !"uno",
680 metadata !"fpexcept.strict") #0
681 %res = select i1 %cond, i32 %a, i32 %b
682 ret i32 %res
683 }
685 define void @foo(half %0, half %1) #0 {
686 ; CHECK-32-LABEL: foo:
687 ; CHECK-32: # %bb.0:
688 ; CHECK-32-NEXT: vmovsh {{[0-9]+}}(%esp), %xmm0
689 ; CHECK-32-NEXT: vucomish {{[0-9]+}}(%esp), %xmm0
690 ; CHECK-32-NEXT: jbe .LBB28_1
691 ; CHECK-32-NEXT: # %bb.2:
692 ; CHECK-32-NEXT: jmp bar@PLT # TAILCALL
693 ; CHECK-32-NEXT: .LBB28_1:
694 ; CHECK-32-NEXT: retl
695 ;
696 ; CHECK-64-LABEL: foo:
697 ; CHECK-64: # %bb.0:
698 ; CHECK-64-NEXT: vucomish %xmm1, %xmm0
699 ; CHECK-64-NEXT: jbe .LBB28_1
700 ; CHECK-64-NEXT: # %bb.2:
701 ; CHECK-64-NEXT: jmp bar@PLT # TAILCALL
702 ; CHECK-64-NEXT: .LBB28_1:
703 ; CHECK-64-NEXT: retq
704 %3 = call i1 @llvm.experimental.constrained.fcmp.f16( half %0, half %1, metadata !"ogt", metadata !"fpexcept.strict") #0
705 br i1 %3, label %4, label %5
707 4: ; preds = %2
708 tail call void @bar() #0
709 br label %5
711 5: ; preds = %4, %2
712 ret void
713 }
714 declare void @bar()
716 attributes #0 = { strictfp }
718 declare i1 @llvm.experimental.constrained.fcmp.f16(half, half, metadata, metadata)
719 declare i1 @llvm.experimental.constrained.fcmps.f16(half, half, metadata, metadata)