| blob | 95888c640d291390c156a3da4aaefc85d1e9c2f5 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=SSE,SSE2
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefixes=SSE,SSE3
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE,SSSE3
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-SLOW
8 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-FAST
9 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-FAST
11 define <2 x double> @insert_v2f64_z1(<2 x double> %a) {
12 ; SSE2-LABEL: insert_v2f64_z1:
13 ; SSE2: # %bb.0:
14 ; SSE2-NEXT: xorpd %xmm1, %xmm1
15 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
16 ; SSE2-NEXT: retq
17 ;
18 ; SSE3-LABEL: insert_v2f64_z1:
19 ; SSE3: # %bb.0:
20 ; SSE3-NEXT: xorpd %xmm1, %xmm1
21 ; SSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
22 ; SSE3-NEXT: retq
23 ;
24 ; SSSE3-LABEL: insert_v2f64_z1:
25 ; SSSE3: # %bb.0:
26 ; SSSE3-NEXT: xorpd %xmm1, %xmm1
27 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
28 ; SSSE3-NEXT: retq
29 ;
30 ; SSE41-LABEL: insert_v2f64_z1:
31 ; SSE41: # %bb.0:
32 ; SSE41-NEXT: xorps %xmm1, %xmm1
33 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
34 ; SSE41-NEXT: retq
35 ;
36 ; AVX-LABEL: insert_v2f64_z1:
37 ; AVX: # %bb.0:
38 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
39 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
40 ; AVX-NEXT: retq
41 %1 = insertelement <2 x double> %a, double 0.0, i32 0
42 ret <2 x double> %1
43 }
45 define <4 x double> @insert_v4f64_0zz3(<4 x double> %a) {
46 ; SSE2-LABEL: insert_v4f64_0zz3:
47 ; SSE2: # %bb.0:
48 ; SSE2-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
49 ; SSE2-NEXT: xorpd %xmm2, %xmm2
50 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
51 ; SSE2-NEXT: retq
52 ;
53 ; SSE3-LABEL: insert_v4f64_0zz3:
54 ; SSE3: # %bb.0:
55 ; SSE3-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
56 ; SSE3-NEXT: xorpd %xmm2, %xmm2
57 ; SSE3-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
58 ; SSE3-NEXT: retq
59 ;
60 ; SSSE3-LABEL: insert_v4f64_0zz3:
61 ; SSSE3: # %bb.0:
62 ; SSSE3-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
63 ; SSSE3-NEXT: xorpd %xmm2, %xmm2
64 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
65 ; SSSE3-NEXT: retq
66 ;
67 ; SSE41-LABEL: insert_v4f64_0zz3:
68 ; SSE41: # %bb.0:
69 ; SSE41-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
70 ; SSE41-NEXT: xorps %xmm2, %xmm2
71 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3]
72 ; SSE41-NEXT: retq
73 ;
74 ; AVX-LABEL: insert_v4f64_0zz3:
75 ; AVX: # %bb.0:
76 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
77 ; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5],ymm0[6,7]
78 ; AVX-NEXT: retq
79 %1 = insertelement <4 x double> %a, double 0.0, i32 1
80 %2 = insertelement <4 x double> %1, double 0.0, i32 2
81 ret <4 x double> %2
82 }
84 define <2 x i64> @insert_v2i64_z1(<2 x i64> %a) {
85 ; SSE2-LABEL: insert_v2i64_z1:
86 ; SSE2: # %bb.0:
87 ; SSE2-NEXT: xorpd %xmm1, %xmm1
88 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
89 ; SSE2-NEXT: retq
90 ;
91 ; SSE3-LABEL: insert_v2i64_z1:
92 ; SSE3: # %bb.0:
93 ; SSE3-NEXT: xorpd %xmm1, %xmm1
94 ; SSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
95 ; SSE3-NEXT: retq
96 ;
97 ; SSSE3-LABEL: insert_v2i64_z1:
98 ; SSSE3: # %bb.0:
99 ; SSSE3-NEXT: xorpd %xmm1, %xmm1
100 ; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
101 ; SSSE3-NEXT: retq
102 ;
103 ; SSE41-LABEL: insert_v2i64_z1:
104 ; SSE41: # %bb.0:
105 ; SSE41-NEXT: xorps %xmm1, %xmm1
106 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
107 ; SSE41-NEXT: retq
108 ;
109 ; AVX-LABEL: insert_v2i64_z1:
110 ; AVX: # %bb.0:
111 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
112 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
113 ; AVX-NEXT: retq
114 %1 = insertelement <2 x i64> %a, i64 0, i32 0
115 ret <2 x i64> %1
116 }
118 define <4 x i64> @insert_v4i64_01z3(<4 x i64> %a) {
119 ; SSE2-LABEL: insert_v4i64_01z3:
120 ; SSE2: # %bb.0:
121 ; SSE2-NEXT: xorpd %xmm2, %xmm2
122 ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
123 ; SSE2-NEXT: retq
124 ;
125 ; SSE3-LABEL: insert_v4i64_01z3:
126 ; SSE3: # %bb.0:
127 ; SSE3-NEXT: xorpd %xmm2, %xmm2
128 ; SSE3-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
129 ; SSE3-NEXT: retq
130 ;
131 ; SSSE3-LABEL: insert_v4i64_01z3:
132 ; SSSE3: # %bb.0:
133 ; SSSE3-NEXT: xorpd %xmm2, %xmm2
134 ; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
135 ; SSSE3-NEXT: retq
136 ;
137 ; SSE41-LABEL: insert_v4i64_01z3:
138 ; SSE41: # %bb.0:
139 ; SSE41-NEXT: xorps %xmm2, %xmm2
140 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3]
141 ; SSE41-NEXT: retq
142 ;
143 ; AVX-LABEL: insert_v4i64_01z3:
144 ; AVX: # %bb.0:
145 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
146 ; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5],ymm0[6,7]
147 ; AVX-NEXT: retq
148 %1 = insertelement <4 x i64> %a, i64 0, i32 2
149 ret <4 x i64> %1
150 }
152 define <4 x float> @insert_v4f32_01z3(<4 x float> %a) {
153 ; SSE2-LABEL: insert_v4f32_01z3:
154 ; SSE2: # %bb.0:
155 ; SSE2-NEXT: xorps %xmm1, %xmm1
156 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
157 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
158 ; SSE2-NEXT: retq
159 ;
160 ; SSE3-LABEL: insert_v4f32_01z3:
161 ; SSE3: # %bb.0:
162 ; SSE3-NEXT: xorps %xmm1, %xmm1
163 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
164 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
165 ; SSE3-NEXT: retq
166 ;
167 ; SSSE3-LABEL: insert_v4f32_01z3:
168 ; SSSE3: # %bb.0:
169 ; SSSE3-NEXT: xorps %xmm1, %xmm1
170 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
171 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
172 ; SSSE3-NEXT: retq
173 ;
174 ; SSE41-LABEL: insert_v4f32_01z3:
175 ; SSE41: # %bb.0:
176 ; SSE41-NEXT: xorps %xmm1, %xmm1
177 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
178 ; SSE41-NEXT: retq
179 ;
180 ; AVX-LABEL: insert_v4f32_01z3:
181 ; AVX: # %bb.0:
182 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
183 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
184 ; AVX-NEXT: retq
185 %1 = insertelement <4 x float> %a, float 0.0, i32 2
186 ret <4 x float> %1
187 }
189 define <8 x float> @insert_v8f32_z12345z7(<8 x float> %a) {
190 ; SSE2-LABEL: insert_v8f32_z12345z7:
191 ; SSE2: # %bb.0:
192 ; SSE2-NEXT: xorps %xmm2, %xmm2
193 ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
194 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
195 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
196 ; SSE2-NEXT: retq
197 ;
198 ; SSE3-LABEL: insert_v8f32_z12345z7:
199 ; SSE3: # %bb.0:
200 ; SSE3-NEXT: xorps %xmm2, %xmm2
201 ; SSE3-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
202 ; SSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
203 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
204 ; SSE3-NEXT: retq
205 ;
206 ; SSSE3-LABEL: insert_v8f32_z12345z7:
207 ; SSSE3: # %bb.0:
208 ; SSSE3-NEXT: xorps %xmm2, %xmm2
209 ; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
210 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
211 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
212 ; SSSE3-NEXT: retq
213 ;
214 ; SSE41-LABEL: insert_v8f32_z12345z7:
215 ; SSE41: # %bb.0:
216 ; SSE41-NEXT: xorps %xmm2, %xmm2
217 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
218 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3]
219 ; SSE41-NEXT: retq
220 ;
221 ; AVX-LABEL: insert_v8f32_z12345z7:
222 ; AVX: # %bb.0:
223 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
224 ; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7]
225 ; AVX-NEXT: retq
226 %1 = insertelement <8 x float> %a, float 0.0, i32 0
227 %2 = insertelement <8 x float> %1, float 0.0, i32 6
228 ret <8 x float> %2
229 }
231 define <4 x i32> @insert_v4i32_01z3(<4 x i32> %a) {
232 ; SSE2-LABEL: insert_v4i32_01z3:
233 ; SSE2: # %bb.0:
234 ; SSE2-NEXT: xorps %xmm1, %xmm1
235 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
236 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
237 ; SSE2-NEXT: retq
238 ;
239 ; SSE3-LABEL: insert_v4i32_01z3:
240 ; SSE3: # %bb.0:
241 ; SSE3-NEXT: xorps %xmm1, %xmm1
242 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
243 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
244 ; SSE3-NEXT: retq
245 ;
246 ; SSSE3-LABEL: insert_v4i32_01z3:
247 ; SSSE3: # %bb.0:
248 ; SSSE3-NEXT: xorps %xmm1, %xmm1
249 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
250 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
251 ; SSSE3-NEXT: retq
252 ;
253 ; SSE41-LABEL: insert_v4i32_01z3:
254 ; SSE41: # %bb.0:
255 ; SSE41-NEXT: xorps %xmm1, %xmm1
256 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
257 ; SSE41-NEXT: retq
258 ;
259 ; AVX-LABEL: insert_v4i32_01z3:
260 ; AVX: # %bb.0:
261 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
262 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
263 ; AVX-NEXT: retq
264 %1 = insertelement <4 x i32> %a, i32 0, i32 2
265 ret <4 x i32> %1
266 }
268 define <8 x i32> @insert_v8i32_z12345z7(<8 x i32> %a) {
269 ; SSE2-LABEL: insert_v8i32_z12345z7:
270 ; SSE2: # %bb.0:
271 ; SSE2-NEXT: xorps %xmm2, %xmm2
272 ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
273 ; SSE2-NEXT: xorps %xmm2, %xmm2
274 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
275 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
276 ; SSE2-NEXT: retq
277 ;
278 ; SSE3-LABEL: insert_v8i32_z12345z7:
279 ; SSE3: # %bb.0:
280 ; SSE3-NEXT: xorps %xmm2, %xmm2
281 ; SSE3-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
282 ; SSE3-NEXT: xorps %xmm2, %xmm2
283 ; SSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
284 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
285 ; SSE3-NEXT: retq
286 ;
287 ; SSSE3-LABEL: insert_v8i32_z12345z7:
288 ; SSSE3: # %bb.0:
289 ; SSSE3-NEXT: xorps %xmm2, %xmm2
290 ; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
291 ; SSSE3-NEXT: xorps %xmm2, %xmm2
292 ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
293 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
294 ; SSSE3-NEXT: retq
295 ;
296 ; SSE41-LABEL: insert_v8i32_z12345z7:
297 ; SSE41: # %bb.0:
298 ; SSE41-NEXT: xorps %xmm2, %xmm2
299 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
300 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3]
301 ; SSE41-NEXT: retq
302 ;
303 ; AVX-LABEL: insert_v8i32_z12345z7:
304 ; AVX: # %bb.0:
305 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
306 ; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7]
307 ; AVX-NEXT: retq
308 %1 = insertelement <8 x i32> %a, i32 0, i32 0
309 %2 = insertelement <8 x i32> %1, i32 0, i32 6
310 ret <8 x i32> %2
311 }
313 define <8 x i16> @insert_v8i16_z12345z7(<8 x i16> %a) {
314 ; SSE2-LABEL: insert_v8i16_z12345z7:
315 ; SSE2: # %bb.0:
316 ; SSE2-NEXT: xorl %eax, %eax
317 ; SSE2-NEXT: pinsrw $0, %eax, %xmm0
318 ; SSE2-NEXT: pinsrw $6, %eax, %xmm0
319 ; SSE2-NEXT: retq
320 ;
321 ; SSE3-LABEL: insert_v8i16_z12345z7:
322 ; SSE3: # %bb.0:
323 ; SSE3-NEXT: xorl %eax, %eax
324 ; SSE3-NEXT: pinsrw $0, %eax, %xmm0
325 ; SSE3-NEXT: pinsrw $6, %eax, %xmm0
326 ; SSE3-NEXT: retq
327 ;
328 ; SSSE3-LABEL: insert_v8i16_z12345z7:
329 ; SSSE3: # %bb.0:
330 ; SSSE3-NEXT: xorl %eax, %eax
331 ; SSSE3-NEXT: pinsrw $0, %eax, %xmm0
332 ; SSSE3-NEXT: pinsrw $6, %eax, %xmm0
333 ; SSSE3-NEXT: retq
334 ;
335 ; SSE41-LABEL: insert_v8i16_z12345z7:
336 ; SSE41: # %bb.0:
337 ; SSE41-NEXT: pxor %xmm1, %xmm1
338 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5],xmm1[6],xmm0[7]
339 ; SSE41-NEXT: retq
340 ;
341 ; AVX-LABEL: insert_v8i16_z12345z7:
342 ; AVX: # %bb.0:
343 ; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
344 ; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5],xmm1[6],xmm0[7]
345 ; AVX-NEXT: retq
346 %1 = insertelement <8 x i16> %a, i16 0, i32 0
347 %2 = insertelement <8 x i16> %1, i16 0, i32 6
348 ret <8 x i16> %2
349 }
351 define <16 x i16> @insert_v16i16_z12345z789ABCDEz(<16 x i16> %a) {
352 ; SSE2-LABEL: insert_v16i16_z12345z789ABCDEz:
353 ; SSE2: # %bb.0:
354 ; SSE2-NEXT: xorl %eax, %eax
355 ; SSE2-NEXT: pinsrw $0, %eax, %xmm0
356 ; SSE2-NEXT: pinsrw $6, %eax, %xmm0
357 ; SSE2-NEXT: pinsrw $7, %eax, %xmm1
358 ; SSE2-NEXT: retq
359 ;
360 ; SSE3-LABEL: insert_v16i16_z12345z789ABCDEz:
361 ; SSE3: # %bb.0:
362 ; SSE3-NEXT: xorl %eax, %eax
363 ; SSE3-NEXT: pinsrw $0, %eax, %xmm0
364 ; SSE3-NEXT: pinsrw $6, %eax, %xmm0
365 ; SSE3-NEXT: pinsrw $7, %eax, %xmm1
366 ; SSE3-NEXT: retq
367 ;
368 ; SSSE3-LABEL: insert_v16i16_z12345z789ABCDEz:
369 ; SSSE3: # %bb.0:
370 ; SSSE3-NEXT: xorl %eax, %eax
371 ; SSSE3-NEXT: pinsrw $0, %eax, %xmm0
372 ; SSSE3-NEXT: pinsrw $6, %eax, %xmm0
373 ; SSSE3-NEXT: pinsrw $7, %eax, %xmm1
374 ; SSSE3-NEXT: retq
375 ;
376 ; SSE41-LABEL: insert_v16i16_z12345z789ABCDEz:
377 ; SSE41: # %bb.0:
378 ; SSE41-NEXT: pxor %xmm2, %xmm2
379 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3,4,5],xmm2[6],xmm0[7]
380 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,6],xmm2[7]
381 ; SSE41-NEXT: retq
382 ;
383 ; AVX-LABEL: insert_v16i16_z12345z789ABCDEz:
384 ; AVX: # %bb.0:
385 ; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
386 ; AVX-NEXT: retq
387 %1 = insertelement <16 x i16> %a, i16 0, i32 0
388 %2 = insertelement <16 x i16> %1, i16 0, i32 6
389 %3 = insertelement <16 x i16> %2, i16 0, i32 15
390 ret <16 x i16> %3
391 }
393 define <16 x i8> @insert_v16i8_z123456789ABCDEz(<16 x i8> %a) {
394 ; SSE2-LABEL: insert_v16i8_z123456789ABCDEz:
395 ; SSE2: # %bb.0:
396 ; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
397 ; SSE2-NEXT: retq
398 ;
399 ; SSE3-LABEL: insert_v16i8_z123456789ABCDEz:
400 ; SSE3: # %bb.0:
401 ; SSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
402 ; SSE3-NEXT: retq
403 ;
404 ; SSSE3-LABEL: insert_v16i8_z123456789ABCDEz:
405 ; SSSE3: # %bb.0:
406 ; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
407 ; SSSE3-NEXT: retq
408 ;
409 ; SSE41-LABEL: insert_v16i8_z123456789ABCDEz:
410 ; SSE41: # %bb.0:
411 ; SSE41-NEXT: xorl %eax, %eax
412 ; SSE41-NEXT: pinsrb $0, %eax, %xmm0
413 ; SSE41-NEXT: pinsrb $15, %eax, %xmm0
414 ; SSE41-NEXT: retq
415 ;
416 ; AVX1-LABEL: insert_v16i8_z123456789ABCDEz:
417 ; AVX1: # %bb.0:
418 ; AVX1-NEXT: xorl %eax, %eax
419 ; AVX1-NEXT: vpinsrb $0, %eax, %xmm0, %xmm0
420 ; AVX1-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
421 ; AVX1-NEXT: retq
422 ;
423 ; AVX2-SLOW-LABEL: insert_v16i8_z123456789ABCDEz:
424 ; AVX2-SLOW: # %bb.0:
425 ; AVX2-SLOW-NEXT: xorl %eax, %eax
426 ; AVX2-SLOW-NEXT: vpinsrb $0, %eax, %xmm0, %xmm0
427 ; AVX2-SLOW-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
428 ; AVX2-SLOW-NEXT: retq
429 ;
430 ; AVX2-FAST-LABEL: insert_v16i8_z123456789ABCDEz:
431 ; AVX2-FAST: # %bb.0:
432 ; AVX2-FAST-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
433 ; AVX2-FAST-NEXT: retq
434 %1 = insertelement <16 x i8> %a, i8 0, i32 0
435 %2 = insertelement <16 x i8> %1, i8 0, i32 15
436 ret <16 x i8> %2
437 }
439 define <32 x i8> @insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz(<32 x i8> %a) {
440 ; SSE2-LABEL: insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz:
441 ; SSE2: # %bb.0:
442 ; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
443 ; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
444 ; SSE2-NEXT: retq
445 ;
446 ; SSE3-LABEL: insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz:
447 ; SSE3: # %bb.0:
448 ; SSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
449 ; SSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
450 ; SSE3-NEXT: retq
451 ;
452 ; SSSE3-LABEL: insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz:
453 ; SSSE3: # %bb.0:
454 ; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
455 ; SSSE3-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
456 ; SSSE3-NEXT: retq
457 ;
458 ; SSE41-LABEL: insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz:
459 ; SSE41: # %bb.0:
460 ; SSE41-NEXT: xorl %eax, %eax
461 ; SSE41-NEXT: pinsrb $0, %eax, %xmm0
462 ; SSE41-NEXT: pinsrb $15, %eax, %xmm0
463 ; SSE41-NEXT: pxor %xmm2, %xmm2
464 ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,6],xmm2[7]
465 ; SSE41-NEXT: retq
466 ;
467 ; AVX-LABEL: insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz:
468 ; AVX: # %bb.0:
469 ; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
470 ; AVX-NEXT: retq
471 %1 = insertelement <32 x i8> %a, i8 0, i32 0
472 %2 = insertelement <32 x i8> %1, i8 0, i32 15
473 %3 = insertelement <32 x i8> %2, i8 0, i32 30
474 %4 = insertelement <32 x i8> %3, i8 0, i32 31
475 ret <32 x i8> %4
476 }
478 define <4 x i32> @PR41512(i32 %x, i32 %y) {
479 ; SSE-LABEL: PR41512:
480 ; SSE: # %bb.0:
481 ; SSE-NEXT: movd %edi, %xmm0
482 ; SSE-NEXT: movd %esi, %xmm1
483 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
484 ; SSE-NEXT: retq
485 ;
486 ; AVX-LABEL: PR41512:
487 ; AVX: # %bb.0:
488 ; AVX-NEXT: vmovd %edi, %xmm0
489 ; AVX-NEXT: vmovd %esi, %xmm1
490 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
491 ; AVX-NEXT: retq
492 %ins1 = insertelement <4 x i32> <i32 undef, i32 0, i32 undef, i32 undef>, i32 %x, i32 0
493 %ins2 = insertelement <4 x i32> <i32 undef, i32 0, i32 undef, i32 undef>, i32 %y, i32 0
494 %r = shufflevector <4 x i32> %ins1, <4 x i32> %ins2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
495 ret <4 x i32> %r
496 }
498 define <4 x i64> @PR41512_v4i64(i64 %x, i64 %y) {
499 ; SSE-LABEL: PR41512_v4i64:
500 ; SSE: # %bb.0:
501 ; SSE-NEXT: movq %rdi, %xmm0
502 ; SSE-NEXT: movq %rsi, %xmm1
503 ; SSE-NEXT: retq
504 ;
505 ; AVX1-LABEL: PR41512_v4i64:
506 ; AVX1: # %bb.0:
507 ; AVX1-NEXT: vmovq %rdi, %xmm0
508 ; AVX1-NEXT: vmovq %rsi, %xmm1
509 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
510 ; AVX1-NEXT: retq
511 ;
512 ; AVX2-LABEL: PR41512_v4i64:
513 ; AVX2: # %bb.0:
514 ; AVX2-NEXT: vmovq %rdi, %xmm0
515 ; AVX2-NEXT: vmovq %rsi, %xmm1
516 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
517 ; AVX2-NEXT: retq
518 %ins1 = insertelement <4 x i64> <i64 undef, i64 0, i64 undef, i64 undef>, i64 %x, i32 0
519 %ins2 = insertelement <4 x i64> <i64 undef, i64 0, i64 undef, i64 undef>, i64 %y, i32 0
520 %r = shufflevector <4 x i64> %ins1, <4 x i64> %ins2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
521 ret <4 x i64> %r
522 }
524 define <8 x float> @PR41512_v8f32(float %x, float %y) {
525 ; SSE2-LABEL: PR41512_v8f32:
526 ; SSE2: # %bb.0:
527 ; SSE2-NEXT: xorps %xmm2, %xmm2
528 ; SSE2-NEXT: xorps %xmm3, %xmm3
529 ; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3]
530 ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
531 ; SSE2-NEXT: movaps %xmm3, %xmm0
532 ; SSE2-NEXT: movaps %xmm2, %xmm1
533 ; SSE2-NEXT: retq
534 ;
535 ; SSE3-LABEL: PR41512_v8f32:
536 ; SSE3: # %bb.0:
537 ; SSE3-NEXT: xorps %xmm2, %xmm2
538 ; SSE3-NEXT: xorps %xmm3, %xmm3
539 ; SSE3-NEXT: movss {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3]
540 ; SSE3-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
541 ; SSE3-NEXT: movaps %xmm3, %xmm0
542 ; SSE3-NEXT: movaps %xmm2, %xmm1
543 ; SSE3-NEXT: retq
544 ;
545 ; SSSE3-LABEL: PR41512_v8f32:
546 ; SSSE3: # %bb.0:
547 ; SSSE3-NEXT: xorps %xmm2, %xmm2
548 ; SSSE3-NEXT: xorps %xmm3, %xmm3
549 ; SSSE3-NEXT: movss {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3]
550 ; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
551 ; SSSE3-NEXT: movaps %xmm3, %xmm0
552 ; SSSE3-NEXT: movaps %xmm2, %xmm1
553 ; SSSE3-NEXT: retq
554 ;
555 ; SSE41-LABEL: PR41512_v8f32:
556 ; SSE41: # %bb.0:
557 ; SSE41-NEXT: xorps %xmm2, %xmm2
558 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
559 ; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
560 ; SSE41-NEXT: retq
561 ;
562 ; AVX-LABEL: PR41512_v8f32:
563 ; AVX: # %bb.0:
564 ; AVX-NEXT: vxorps %xmm2, %xmm2, %xmm2
565 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
566 ; AVX-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
567 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
568 ; AVX-NEXT: retq
569 %ins1 = insertelement <8 x float> zeroinitializer, float %x, i32 0
570 %ins2 = insertelement <8 x float> zeroinitializer, float %y, i32 0
571 %r = shufflevector <8 x float> %ins1, <8 x float> %ins2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
572 ret <8 x float> %r
573 }
575 define <4 x i32> @PR41512_loads(i32* %p1, i32* %p2) {
576 ; SSE-LABEL: PR41512_loads:
577 ; SSE: # %bb.0:
578 ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
579 ; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
580 ; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
581 ; SSE-NEXT: retq
582 ;
583 ; AVX-LABEL: PR41512_loads:
584 ; AVX: # %bb.0:
585 ; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
586 ; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
587 ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
588 ; AVX-NEXT: retq
589 %x = load i32, i32* %p1
590 %y = load i32, i32* %p2
591 %ins1 = insertelement <4 x i32> <i32 undef, i32 0, i32 undef, i32 undef>, i32 %x, i32 0
592 %ins2 = insertelement <4 x i32> <i32 undef, i32 0, i32 undef, i32 undef>, i32 %y, i32 0
593 %r = shufflevector <4 x i32> %ins1, <4 x i32> %ins2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
594 ret <4 x i32> %r
595 }