| blob | 3218916ddc285c80d7caecf046a1547938bce059 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.1 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X86-SSE
3 ; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,AVX1,X86-AVX1
4 ; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=AVX,AVX512,X86-AVX512
5 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.1 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
6 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,AVX1,X64-AVX1
7 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=AVX,AVX512,X64-AVX512
9 define <2 x double> @test_x86_sse41_blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) {
10 ; SSE-LABEL: test_x86_sse41_blendvpd:
11 ; SSE: ## %bb.0:
12 ; SSE-NEXT: movapd %xmm0, %xmm3 ## encoding: [0x66,0x0f,0x28,0xd8]
13 ; SSE-NEXT: movaps %xmm2, %xmm0 ## encoding: [0x0f,0x28,0xc2]
14 ; SSE-NEXT: blendvpd %xmm0, %xmm1, %xmm3 ## encoding: [0x66,0x0f,0x38,0x15,0xd9]
15 ; SSE-NEXT: movapd %xmm3, %xmm0 ## encoding: [0x66,0x0f,0x28,0xc3]
16 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
17 ;
18 ; AVX-LABEL: test_x86_sse41_blendvpd:
19 ; AVX: ## %bb.0:
20 ; AVX-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x4b,0xc1,0x20]
21 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
22 %res = call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) ; <<2 x double>> [#uses=1]
23 ret <2 x double> %res
24 }
25 declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
28 define <4 x float> @test_x86_sse41_blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
29 ; SSE-LABEL: test_x86_sse41_blendvps:
30 ; SSE: ## %bb.0:
31 ; SSE-NEXT: movaps %xmm0, %xmm3 ## encoding: [0x0f,0x28,0xd8]
32 ; SSE-NEXT: movaps %xmm2, %xmm0 ## encoding: [0x0f,0x28,0xc2]
33 ; SSE-NEXT: blendvps %xmm0, %xmm1, %xmm3 ## encoding: [0x66,0x0f,0x38,0x14,0xd9]
34 ; SSE-NEXT: movaps %xmm3, %xmm0 ## encoding: [0x0f,0x28,0xc3]
35 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
36 ;
37 ; AVX-LABEL: test_x86_sse41_blendvps:
38 ; AVX: ## %bb.0:
39 ; AVX-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x4a,0xc1,0x20]
40 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
41 %res = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) ; <<4 x float>> [#uses=1]
42 ret <4 x float> %res
43 }
44 declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
47 define <2 x double> @test_x86_sse41_dppd(<2 x double> %a0, <2 x double> %a1) {
48 ; SSE-LABEL: test_x86_sse41_dppd:
49 ; SSE: ## %bb.0:
50 ; SSE-NEXT: dppd $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x41,0xc1,0x07]
51 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
52 ;
53 ; AVX-LABEL: test_x86_sse41_dppd:
54 ; AVX: ## %bb.0:
55 ; AVX-NEXT: vdppd $7, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x41,0xc1,0x07]
56 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
57 %res = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]
58 ret <2 x double> %res
59 }
60 declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i8) nounwind readnone
63 define <4 x float> @test_x86_sse41_dpps(<4 x float> %a0, <4 x float> %a1) {
64 ; SSE-LABEL: test_x86_sse41_dpps:
65 ; SSE: ## %bb.0:
66 ; SSE-NEXT: dpps $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x40,0xc1,0x07]
67 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
68 ;
69 ; AVX-LABEL: test_x86_sse41_dpps:
70 ; AVX: ## %bb.0:
71 ; AVX-NEXT: vdpps $7, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x40,0xc1,0x07]
72 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
73 %res = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1]
74 ret <4 x float> %res
75 }
76 declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i8) nounwind readnone
79 define <4 x float> @test_x86_sse41_insertps(<4 x float> %a0, <4 x float> %a1) {
80 ; SSE-LABEL: test_x86_sse41_insertps:
81 ; SSE: ## %bb.0:
82 ; SSE-NEXT: insertps $17, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x21,0xc1,0x11]
83 ; SSE-NEXT: ## xmm0 = zero,xmm1[0],xmm0[2,3]
84 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
85 ;
86 ; AVX1-LABEL: test_x86_sse41_insertps:
87 ; AVX1: ## %bb.0:
88 ; AVX1-NEXT: vinsertps $17, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x11]
89 ; AVX1-NEXT: ## xmm0 = zero,xmm1[0],xmm0[2,3]
90 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
91 ;
92 ; AVX512-LABEL: test_x86_sse41_insertps:
93 ; AVX512: ## %bb.0:
94 ; AVX512-NEXT: vinsertps $17, %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x11]
95 ; AVX512-NEXT: ## xmm0 = zero,xmm1[0],xmm0[2,3]
96 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
97 %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 17) ; <<4 x float>> [#uses=1]
98 ret <4 x float> %res
99 }
100 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone
104 define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) {
105 ; SSE-LABEL: test_x86_sse41_mpsadbw:
106 ; SSE: ## %bb.0:
107 ; SSE-NEXT: mpsadbw $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x42,0xc1,0x07]
108 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
109 ;
110 ; AVX-LABEL: test_x86_sse41_mpsadbw:
111 ; AVX: ## %bb.0:
112 ; AVX-NEXT: vmpsadbw $7, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x42,0xc1,0x07]
113 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
114 %res = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <<8 x i16>> [#uses=1]
115 ret <8 x i16> %res
116 }
117 declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i8) nounwind readnone
120 define <8 x i16> @test_x86_sse41_packusdw(<4 x i32> %a0, <4 x i32> %a1) {
121 ; SSE-LABEL: test_x86_sse41_packusdw:
122 ; SSE: ## %bb.0:
123 ; SSE-NEXT: packusdw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x2b,0xc1]
124 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
125 ;
126 ; AVX1-LABEL: test_x86_sse41_packusdw:
127 ; AVX1: ## %bb.0:
128 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x2b,0xc1]
129 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
130 ;
131 ; AVX512-LABEL: test_x86_sse41_packusdw:
132 ; AVX512: ## %bb.0:
133 ; AVX512-NEXT: vpackusdw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x2b,0xc1]
134 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
135 %res = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1]
136 ret <8 x i16> %res
137 }
138 declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>) nounwind readnone
141 define <8 x i16> @test_x86_sse41_packusdw_fold() {
142 ; X86-SSE-LABEL: test_x86_sse41_packusdw_fold:
143 ; X86-SSE: ## %bb.0:
144 ; X86-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,65535,65535,0,0]
145 ; X86-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
146 ; X86-SSE-NEXT: ## fixup A - offset: 3, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
147 ; X86-SSE-NEXT: retl ## encoding: [0xc3]
148 ;
149 ; X86-AVX1-LABEL: test_x86_sse41_packusdw_fold:
150 ; X86-AVX1: ## %bb.0:
151 ; X86-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,65535,65535,0,0]
152 ; X86-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
153 ; X86-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
154 ; X86-AVX1-NEXT: retl ## encoding: [0xc3]
155 ;
156 ; X86-AVX512-LABEL: test_x86_sse41_packusdw_fold:
157 ; X86-AVX512: ## %bb.0:
158 ; X86-AVX512-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,65535,65535,0,0]
159 ; X86-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
160 ; X86-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
161 ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
162 ;
163 ; X64-SSE-LABEL: test_x86_sse41_packusdw_fold:
164 ; X64-SSE: ## %bb.0:
165 ; X64-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,65535,65535,0,0]
166 ; X64-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
167 ; X64-SSE-NEXT: ## fixup A - offset: 3, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
168 ; X64-SSE-NEXT: retq ## encoding: [0xc3]
169 ;
170 ; X64-AVX1-LABEL: test_x86_sse41_packusdw_fold:
171 ; X64-AVX1: ## %bb.0:
172 ; X64-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,65535,65535,0,0]
173 ; X64-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
174 ; X64-AVX1-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
175 ; X64-AVX1-NEXT: retq ## encoding: [0xc3]
176 ;
177 ; X64-AVX512-LABEL: test_x86_sse41_packusdw_fold:
178 ; X64-AVX512: ## %bb.0:
179 ; X64-AVX512-NEXT: vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,65535,65535,0,0]
180 ; X64-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
181 ; X64-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
182 ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
183 %res = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> zeroinitializer, <4 x i32> <i32 65535, i32 65536, i32 -1, i32 -131072>)
184 ret <8 x i16> %res
185 }
188 define <16 x i8> @test_x86_sse41_pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) {
189 ; SSE-LABEL: test_x86_sse41_pblendvb:
190 ; SSE: ## %bb.0:
191 ; SSE-NEXT: movdqa %xmm0, %xmm3 ## encoding: [0x66,0x0f,0x6f,0xd8]
192 ; SSE-NEXT: movaps %xmm2, %xmm0 ## encoding: [0x0f,0x28,0xc2]
193 ; SSE-NEXT: pblendvb %xmm0, %xmm1, %xmm3 ## encoding: [0x66,0x0f,0x38,0x10,0xd9]
194 ; SSE-NEXT: movdqa %xmm3, %xmm0 ## encoding: [0x66,0x0f,0x6f,0xc3]
195 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
196 ;
197 ; AVX-LABEL: test_x86_sse41_pblendvb:
198 ; AVX: ## %bb.0:
199 ; AVX-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x4c,0xc1,0x20]
200 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
201 %res = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) ; <<16 x i8>> [#uses=1]
202 ret <16 x i8> %res
203 }
204 declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
207 define <8 x i16> @test_x86_sse41_phminposuw(<8 x i16> %a0) {
208 ; SSE-LABEL: test_x86_sse41_phminposuw:
209 ; SSE: ## %bb.0:
210 ; SSE-NEXT: phminposuw %xmm0, %xmm0 ## encoding: [0x66,0x0f,0x38,0x41,0xc0]
211 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
212 ;
213 ; AVX-LABEL: test_x86_sse41_phminposuw:
214 ; AVX: ## %bb.0:
215 ; AVX-NEXT: vphminposuw %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x41,0xc0]
216 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
217 %res = call <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16> %a0) ; <<8 x i16>> [#uses=1]
218 ret <8 x i16> %res
219 }
220 declare <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16>) nounwind readnone
223 define i32 @test_x86_sse41_ptestc(<2 x i64> %a0, <2 x i64> %a1) {
224 ; SSE-LABEL: test_x86_sse41_ptestc:
225 ; SSE: ## %bb.0:
226 ; SSE-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
227 ; SSE-NEXT: ptest %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x17,0xc1]
228 ; SSE-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
229 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
230 ;
231 ; AVX-LABEL: test_x86_sse41_ptestc:
232 ; AVX: ## %bb.0:
233 ; AVX-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
234 ; AVX-NEXT: vptest %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x17,0xc1]
235 ; AVX-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
236 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
237 %res = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]
238 ret i32 %res
239 }
240 declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
243 define i32 @test_x86_sse41_ptestnzc(<2 x i64> %a0, <2 x i64> %a1) {
244 ; SSE-LABEL: test_x86_sse41_ptestnzc:
245 ; SSE: ## %bb.0:
246 ; SSE-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
247 ; SSE-NEXT: ptest %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x17,0xc1]
248 ; SSE-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
249 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
250 ;
251 ; AVX-LABEL: test_x86_sse41_ptestnzc:
252 ; AVX: ## %bb.0:
253 ; AVX-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
254 ; AVX-NEXT: vptest %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x17,0xc1]
255 ; AVX-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
256 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
257 %res = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]
258 ret i32 %res
259 }
260 declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone
263 define i32 @test_x86_sse41_ptestz(<2 x i64> %a0, <2 x i64> %a1) {
264 ; SSE-LABEL: test_x86_sse41_ptestz:
265 ; SSE: ## %bb.0:
266 ; SSE-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
267 ; SSE-NEXT: ptest %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x17,0xc1]
268 ; SSE-NEXT: sete %al ## encoding: [0x0f,0x94,0xc0]
269 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
270 ;
271 ; AVX-LABEL: test_x86_sse41_ptestz:
272 ; AVX: ## %bb.0:
273 ; AVX-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
274 ; AVX-NEXT: vptest %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x17,0xc1]
275 ; AVX-NEXT: sete %al ## encoding: [0x0f,0x94,0xc0]
276 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
277 %res = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %a0, <2 x i64> %a1) ; <i32> [#uses=1]
278 ret i32 %res
279 }
280 declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
283 define <2 x double> @test_x86_sse41_round_pd(<2 x double> %a0) {
284 ; SSE-LABEL: test_x86_sse41_round_pd:
285 ; SSE: ## %bb.0:
286 ; SSE-NEXT: roundpd $7, %xmm0, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x09,0xc0,0x07]
287 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
288 ;
289 ; AVX1-LABEL: test_x86_sse41_round_pd:
290 ; AVX1: ## %bb.0:
291 ; AVX1-NEXT: vroundpd $7, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x09,0xc0,0x07]
292 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
293 ;
294 ; AVX512-LABEL: test_x86_sse41_round_pd:
295 ; AVX512: ## %bb.0:
296 ; AVX512-NEXT: vroundpd $7, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x09,0xc0,0x07]
297 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
298 %res = call <2 x double> @llvm.x86.sse41.round.pd(<2 x double> %a0, i32 7) ; <<2 x double>> [#uses=1]
299 ret <2 x double> %res
300 }
301 declare <2 x double> @llvm.x86.sse41.round.pd(<2 x double>, i32) nounwind readnone
304 define <4 x float> @test_x86_sse41_round_ps(<4 x float> %a0) {
305 ; SSE-LABEL: test_x86_sse41_round_ps:
306 ; SSE: ## %bb.0:
307 ; SSE-NEXT: roundps $7, %xmm0, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x08,0xc0,0x07]
308 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
309 ;
310 ; AVX1-LABEL: test_x86_sse41_round_ps:
311 ; AVX1: ## %bb.0:
312 ; AVX1-NEXT: vroundps $7, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x08,0xc0,0x07]
313 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
314 ;
315 ; AVX512-LABEL: test_x86_sse41_round_ps:
316 ; AVX512: ## %bb.0:
317 ; AVX512-NEXT: vroundps $7, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x08,0xc0,0x07]
318 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
319 %res = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %a0, i32 7) ; <<4 x float>> [#uses=1]
320 ret <4 x float> %res
321 }
322 declare <4 x float> @llvm.x86.sse41.round.ps(<4 x float>, i32) nounwind readnone
325 define <2 x double> @test_x86_sse41_round_sd(<2 x double> %a0, <2 x double> %a1) {
326 ; SSE-LABEL: test_x86_sse41_round_sd:
327 ; SSE: ## %bb.0:
328 ; SSE-NEXT: roundsd $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x0b,0xc1,0x07]
329 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
330 ;
331 ; AVX1-LABEL: test_x86_sse41_round_sd:
332 ; AVX1: ## %bb.0:
333 ; AVX1-NEXT: vroundsd $7, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0b,0xc1,0x07]
334 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
335 ;
336 ; AVX512-LABEL: test_x86_sse41_round_sd:
337 ; AVX512: ## %bb.0:
338 ; AVX512-NEXT: vroundsd $7, %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x0b,0xc1,0x07]
339 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
340 %res = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %a0, <2 x double> %a1, i32 7) ; <<2 x double>> [#uses=1]
341 ret <2 x double> %res
342 }
343 declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone
346 define <2 x double> @test_x86_sse41_round_sd_load(<2 x double> %a0, <2 x double>* %a1) {
347 ; X86-SSE-LABEL: test_x86_sse41_round_sd_load:
348 ; X86-SSE: ## %bb.0:
349 ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
350 ; X86-SSE-NEXT: roundsd $7, (%eax), %xmm0 ## encoding: [0x66,0x0f,0x3a,0x0b,0x00,0x07]
351 ; X86-SSE-NEXT: retl ## encoding: [0xc3]
352 ;
353 ; X86-AVX1-LABEL: test_x86_sse41_round_sd_load:
354 ; X86-AVX1: ## %bb.0:
355 ; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
356 ; X86-AVX1-NEXT: vroundsd $7, (%eax), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0b,0x00,0x07]
357 ; X86-AVX1-NEXT: retl ## encoding: [0xc3]
358 ;
359 ; X86-AVX512-LABEL: test_x86_sse41_round_sd_load:
360 ; X86-AVX512: ## %bb.0:
361 ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
362 ; X86-AVX512-NEXT: vroundsd $7, (%eax), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x0b,0x00,0x07]
363 ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
364 ;
365 ; X64-SSE-LABEL: test_x86_sse41_round_sd_load:
366 ; X64-SSE: ## %bb.0:
367 ; X64-SSE-NEXT: roundsd $7, (%rdi), %xmm0 ## encoding: [0x66,0x0f,0x3a,0x0b,0x07,0x07]
368 ; X64-SSE-NEXT: retq ## encoding: [0xc3]
369 ;
370 ; X64-AVX1-LABEL: test_x86_sse41_round_sd_load:
371 ; X64-AVX1: ## %bb.0:
372 ; X64-AVX1-NEXT: vroundsd $7, (%rdi), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0b,0x07,0x07]
373 ; X64-AVX1-NEXT: retq ## encoding: [0xc3]
374 ;
375 ; X64-AVX512-LABEL: test_x86_sse41_round_sd_load:
376 ; X64-AVX512: ## %bb.0:
377 ; X64-AVX512-NEXT: vroundsd $7, (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x0b,0x07,0x07]
378 ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
379 %a1b = load <2 x double>, <2 x double>* %a1
380 %res = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %a0, <2 x double> %a1b, i32 7) ; <<2 x double>> [#uses=1]
381 ret <2 x double> %res
382 }
385 define <4 x float> @test_x86_sse41_round_ss(<4 x float> %a0, <4 x float> %a1) {
386 ; SSE-LABEL: test_x86_sse41_round_ss:
387 ; SSE: ## %bb.0:
388 ; SSE-NEXT: roundss $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x0a,0xc1,0x07]
389 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
390 ;
391 ; AVX1-LABEL: test_x86_sse41_round_ss:
392 ; AVX1: ## %bb.0:
393 ; AVX1-NEXT: vroundss $7, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0a,0xc1,0x07]
394 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
395 ;
396 ; AVX512-LABEL: test_x86_sse41_round_ss:
397 ; AVX512: ## %bb.0:
398 ; AVX512-NEXT: vroundss $7, %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x0a,0xc1,0x07]
399 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
400 %res = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1]
401 ret <4 x float> %res
402 }
403 declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone