| blob | 28ffa025d8a2e30c5ed76fc199393e368344963f |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2 < %s | FileCheck %s --check-prefixes=CHECK-SSE,CHECK-SSE2
3 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse4.1 < %s | FileCheck %s --check-prefixes=CHECK-SSE,CHECK-SSE41
4 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+avx < %s | FileCheck %s --check-prefixes=CHECK-AVX,CHECK-AVX1
5 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 < %s | FileCheck %s --check-prefixes=CHECK-AVX,CHECK-AVX2
6 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f,+avx512vl < %s | FileCheck %s --check-prefixes=CHECK-AVX,CHECK-AVX512VL
8 ; Odd divisor
9 define <4 x i32> @test_urem_odd_25(<4 x i32> %X) nounwind {
10 ; CHECK-SSE2-LABEL: test_urem_odd_25:
11 ; CHECK-SSE2: # %bb.0:
12 ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [3264175145,3264175145,3264175145,3264175145]
13 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
14 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
15 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
16 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
17 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
18 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
19 ; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
20 ; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
21 ; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
22 ; CHECK-SSE2-NEXT: retq
23 ;
24 ; CHECK-SSE41-LABEL: test_urem_odd_25:
25 ; CHECK-SSE41: # %bb.0:
26 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
27 ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [171798691,171798691,171798691,171798691]
28 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
29 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
30 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
31 ; CHECK-SSE41-NEXT: retq
32 ;
33 ; CHECK-AVX1-LABEL: test_urem_odd_25:
34 ; CHECK-AVX1: # %bb.0:
35 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
36 ; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
37 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
38 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
39 ; CHECK-AVX1-NEXT: retq
40 ;
41 ; CHECK-AVX2-LABEL: test_urem_odd_25:
42 ; CHECK-AVX2: # %bb.0:
43 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3264175145,3264175145,3264175145,3264175145]
44 ; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
45 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [171798691,171798691,171798691,171798691]
46 ; CHECK-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm1
47 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
48 ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
49 ; CHECK-AVX2-NEXT: retq
50 ;
51 ; CHECK-AVX512VL-LABEL: test_urem_odd_25:
52 ; CHECK-AVX512VL: # %bb.0:
53 ; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
54 ; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1
55 ; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
56 ; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
57 ; CHECK-AVX512VL-NEXT: retq
58 %urem = urem <4 x i32> %X, <i32 25, i32 25, i32 25, i32 25>
59 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
60 %ret = zext <4 x i1> %cmp to <4 x i32>
61 ret <4 x i32> %ret
62 }
64 ; Even divisors
65 define <4 x i32> @test_urem_even_100(<4 x i32> %X) nounwind {
66 ; CHECK-SSE2-LABEL: test_urem_even_100:
67 ; CHECK-SSE2: # %bb.0:
68 ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [3264175145,3264175145,3264175145,3264175145]
69 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
70 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
71 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
72 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
73 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
74 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
75 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
76 ; CHECK-SSE2-NEXT: psrld $2, %xmm1
77 ; CHECK-SSE2-NEXT: pslld $30, %xmm0
78 ; CHECK-SSE2-NEXT: por %xmm1, %xmm0
79 ; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
80 ; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
81 ; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
82 ; CHECK-SSE2-NEXT: retq
83 ;
84 ; CHECK-SSE41-LABEL: test_urem_even_100:
85 ; CHECK-SSE41: # %bb.0:
86 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
87 ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
88 ; CHECK-SSE41-NEXT: psrld $2, %xmm1
89 ; CHECK-SSE41-NEXT: pslld $30, %xmm0
90 ; CHECK-SSE41-NEXT: por %xmm1, %xmm0
91 ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [42949672,42949672,42949672,42949672]
92 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
93 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
94 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
95 ; CHECK-SSE41-NEXT: retq
96 ;
97 ; CHECK-AVX1-LABEL: test_urem_even_100:
98 ; CHECK-AVX1: # %bb.0:
99 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
100 ; CHECK-AVX1-NEXT: vpsrld $2, %xmm0, %xmm1
101 ; CHECK-AVX1-NEXT: vpslld $30, %xmm0, %xmm0
102 ; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
103 ; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
104 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
105 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
106 ; CHECK-AVX1-NEXT: retq
107 ;
108 ; CHECK-AVX2-LABEL: test_urem_even_100:
109 ; CHECK-AVX2: # %bb.0:
110 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3264175145,3264175145,3264175145,3264175145]
111 ; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
112 ; CHECK-AVX2-NEXT: vpsrld $2, %xmm0, %xmm1
113 ; CHECK-AVX2-NEXT: vpslld $30, %xmm0, %xmm0
114 ; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
115 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [42949672,42949672,42949672,42949672]
116 ; CHECK-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm1
117 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
118 ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
119 ; CHECK-AVX2-NEXT: retq
120 ;
121 ; CHECK-AVX512VL-LABEL: test_urem_even_100:
122 ; CHECK-AVX512VL: # %bb.0:
123 ; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
124 ; CHECK-AVX512VL-NEXT: vprord $2, %xmm0, %xmm0
125 ; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1
126 ; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
127 ; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
128 ; CHECK-AVX512VL-NEXT: retq
129 %urem = urem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100>
130 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
131 %ret = zext <4 x i1> %cmp to <4 x i32>
132 ret <4 x i32> %ret
133 }
135 ; Negative divisors should be negated, and thus this is still splat vectors.
137 ; Odd divisor
138 define <4 x i32> @test_urem_odd_neg25(<4 x i32> %X) nounwind {
139 ; CHECK-SSE2-LABEL: test_urem_odd_neg25:
140 ; CHECK-SSE2: # %bb.0:
141 ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [3264175145,1030792151,1030792151,3264175145]
142 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
143 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
144 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
145 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
146 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
147 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
148 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
149 ; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
150 ; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
151 ; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
152 ; CHECK-SSE2-NEXT: retq
153 ;
154 ; CHECK-SSE41-LABEL: test_urem_odd_neg25:
155 ; CHECK-SSE41: # %bb.0:
156 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
157 ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [171798691,1,1,171798691]
158 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
159 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
160 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
161 ; CHECK-SSE41-NEXT: retq
162 ;
163 ; CHECK-AVX-LABEL: test_urem_odd_neg25:
164 ; CHECK-AVX: # %bb.0:
165 ; CHECK-AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
166 ; CHECK-AVX-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
167 ; CHECK-AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
168 ; CHECK-AVX-NEXT: vpsrld $31, %xmm0, %xmm0
169 ; CHECK-AVX-NEXT: retq
170 %urem = urem <4 x i32> %X, <i32 25, i32 -25, i32 -25, i32 25>
171 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
172 %ret = zext <4 x i1> %cmp to <4 x i32>
173 ret <4 x i32> %ret
174 }
176 ; Even divisors
177 define <4 x i32> @test_urem_even_neg100(<4 x i32> %X) nounwind {
178 ; CHECK-SSE2-LABEL: test_urem_even_neg100:
179 ; CHECK-SSE2: # %bb.0:
180 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
181 ; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
182 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
183 ; CHECK-SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
184 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
185 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
186 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
187 ; CHECK-SSE2-NEXT: psrld $2, %xmm1
188 ; CHECK-SSE2-NEXT: pslld $30, %xmm0
189 ; CHECK-SSE2-NEXT: por %xmm1, %xmm0
190 ; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
191 ; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
192 ; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
193 ; CHECK-SSE2-NEXT: retq
194 ;
195 ; CHECK-SSE41-LABEL: test_urem_even_neg100:
196 ; CHECK-SSE41: # %bb.0:
197 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
198 ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
199 ; CHECK-SSE41-NEXT: psrld $2, %xmm1
200 ; CHECK-SSE41-NEXT: pslld $30, %xmm0
201 ; CHECK-SSE41-NEXT: por %xmm1, %xmm0
202 ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,42949672,1,42949672]
203 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
204 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
205 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
206 ; CHECK-SSE41-NEXT: retq
207 ;
208 ; CHECK-AVX1-LABEL: test_urem_even_neg100:
209 ; CHECK-AVX1: # %bb.0:
210 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
211 ; CHECK-AVX1-NEXT: vpsrld $2, %xmm0, %xmm1
212 ; CHECK-AVX1-NEXT: vpslld $30, %xmm0, %xmm0
213 ; CHECK-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
214 ; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
215 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
216 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
217 ; CHECK-AVX1-NEXT: retq
218 ;
219 ; CHECK-AVX2-LABEL: test_urem_even_neg100:
220 ; CHECK-AVX2: # %bb.0:
221 ; CHECK-AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
222 ; CHECK-AVX2-NEXT: vpsrld $2, %xmm0, %xmm1
223 ; CHECK-AVX2-NEXT: vpslld $30, %xmm0, %xmm0
224 ; CHECK-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
225 ; CHECK-AVX2-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
226 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
227 ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
228 ; CHECK-AVX2-NEXT: retq
229 ;
230 ; CHECK-AVX512VL-LABEL: test_urem_even_neg100:
231 ; CHECK-AVX512VL: # %bb.0:
232 ; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
233 ; CHECK-AVX512VL-NEXT: vprord $2, %xmm0, %xmm0
234 ; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
235 ; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
236 ; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
237 ; CHECK-AVX512VL-NEXT: retq
238 %urem = urem <4 x i32> %X, <i32 -100, i32 100, i32 -100, i32 100>
239 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
240 %ret = zext <4 x i1> %cmp to <4 x i32>
241 ret <4 x i32> %ret
242 }
244 ;------------------------------------------------------------------------------;
245 ; Comparison constant has undef elements.
246 ;------------------------------------------------------------------------------;
248 define <4 x i32> @test_urem_odd_undef1(<4 x i32> %X) nounwind {
249 ; CHECK-SSE2-LABEL: test_urem_odd_undef1:
250 ; CHECK-SSE2: # %bb.0:
251 ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1374389535,1374389535,1374389535,1374389535]
252 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
253 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
254 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
255 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
256 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
257 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
258 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
259 ; CHECK-SSE2-NEXT: psrld $3, %xmm2
260 ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [25,25,25,25]
261 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
262 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
263 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
264 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
265 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3]
266 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
267 ; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
268 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
269 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
270 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
271 ; CHECK-SSE2-NEXT: retq
272 ;
273 ; CHECK-SSE41-LABEL: test_urem_odd_undef1:
274 ; CHECK-SSE41: # %bb.0:
275 ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
276 ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [1374389535,1374389535,1374389535,1374389535]
277 ; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm1
278 ; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm2
279 ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
280 ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
281 ; CHECK-SSE41-NEXT: psrld $3, %xmm2
282 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
283 ; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0
284 ; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
285 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
286 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
287 ; CHECK-SSE41-NEXT: retq
288 ;
289 ; CHECK-AVX1-LABEL: test_urem_odd_undef1:
290 ; CHECK-AVX1: # %bb.0:
291 ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
292 ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1374389535,1374389535,1374389535,1374389535]
293 ; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
294 ; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm0, %xmm2
295 ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
296 ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
297 ; CHECK-AVX1-NEXT: vpsrld $3, %xmm1, %xmm1
298 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
299 ; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
300 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
301 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
302 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
303 ; CHECK-AVX1-NEXT: retq
304 ;
305 ; CHECK-AVX2-LABEL: test_urem_odd_undef1:
306 ; CHECK-AVX2: # %bb.0:
307 ; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
308 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1374389535,1374389535,1374389535,1374389535]
309 ; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
310 ; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm0, %xmm2
311 ; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
312 ; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3]
313 ; CHECK-AVX2-NEXT: vpsrld $3, %xmm1, %xmm1
314 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [25,25,25,25]
315 ; CHECK-AVX2-NEXT: vpmulld %xmm2, %xmm1, %xmm1
316 ; CHECK-AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
317 ; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
318 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
319 ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
320 ; CHECK-AVX2-NEXT: retq
321 ;
322 ; CHECK-AVX512VL-LABEL: test_urem_odd_undef1:
323 ; CHECK-AVX512VL: # %bb.0:
324 ; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
325 ; CHECK-AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1374389535,1374389535,1374389535,1374389535]
326 ; CHECK-AVX512VL-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
327 ; CHECK-AVX512VL-NEXT: vpmuludq %xmm2, %xmm0, %xmm2
328 ; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
329 ; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3]
330 ; CHECK-AVX512VL-NEXT: vpsrld $3, %xmm1, %xmm1
331 ; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
332 ; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0
333 ; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
334 ; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
335 ; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
336 ; CHECK-AVX512VL-NEXT: retq
337 %urem = urem <4 x i32> %X, <i32 25, i32 25, i32 25, i32 25>
338 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 undef, i32 0>
339 %ret = zext <4 x i1> %cmp to <4 x i32>
340 ret <4 x i32> %ret
341 }
343 define <4 x i32> @test_urem_even_undef1(<4 x i32> %X) nounwind {
344 ; CHECK-SSE2-LABEL: test_urem_even_undef1:
345 ; CHECK-SSE2: # %bb.0:
346 ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1374389535,1374389535,1374389535,1374389535]
347 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
348 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
349 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
350 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
351 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
352 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
353 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
354 ; CHECK-SSE2-NEXT: psrld $5, %xmm2
355 ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [100,100,100,100]
356 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
357 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
358 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
359 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
360 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3]
361 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
362 ; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
363 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
364 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
365 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
366 ; CHECK-SSE2-NEXT: retq
367 ;
368 ; CHECK-SSE41-LABEL: test_urem_even_undef1:
369 ; CHECK-SSE41: # %bb.0:
370 ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
371 ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [1374389535,1374389535,1374389535,1374389535]
372 ; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm1
373 ; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm2
374 ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
375 ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
376 ; CHECK-SSE41-NEXT: psrld $5, %xmm2
377 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
378 ; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0
379 ; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
380 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
381 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
382 ; CHECK-SSE41-NEXT: retq
383 ;
384 ; CHECK-AVX1-LABEL: test_urem_even_undef1:
385 ; CHECK-AVX1: # %bb.0:
386 ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
387 ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1374389535,1374389535,1374389535,1374389535]
388 ; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
389 ; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm0, %xmm2
390 ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
391 ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
392 ; CHECK-AVX1-NEXT: vpsrld $5, %xmm1, %xmm1
393 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
394 ; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
395 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
396 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
397 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
398 ; CHECK-AVX1-NEXT: retq
399 ;
400 ; CHECK-AVX2-LABEL: test_urem_even_undef1:
401 ; CHECK-AVX2: # %bb.0:
402 ; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
403 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1374389535,1374389535,1374389535,1374389535]
404 ; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
405 ; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm0, %xmm2
406 ; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
407 ; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3]
408 ; CHECK-AVX2-NEXT: vpsrld $5, %xmm1, %xmm1
409 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [100,100,100,100]
410 ; CHECK-AVX2-NEXT: vpmulld %xmm2, %xmm1, %xmm1
411 ; CHECK-AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
412 ; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
413 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
414 ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
415 ; CHECK-AVX2-NEXT: retq
416 ;
417 ; CHECK-AVX512VL-LABEL: test_urem_even_undef1:
418 ; CHECK-AVX512VL: # %bb.0:
419 ; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
420 ; CHECK-AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1374389535,1374389535,1374389535,1374389535]
421 ; CHECK-AVX512VL-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
422 ; CHECK-AVX512VL-NEXT: vpmuludq %xmm2, %xmm0, %xmm2
423 ; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
424 ; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3]
425 ; CHECK-AVX512VL-NEXT: vpsrld $5, %xmm1, %xmm1
426 ; CHECK-AVX512VL-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
427 ; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0
428 ; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
429 ; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
430 ; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
431 ; CHECK-AVX512VL-NEXT: retq
432 %urem = urem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100>
433 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 undef, i32 0>
434 %ret = zext <4 x i1> %cmp to <4 x i32>
435 ret <4 x i32> %ret
436 }
438 ;------------------------------------------------------------------------------;
439 ; Negative tests
440 ;------------------------------------------------------------------------------;
442 define <4 x i32> @test_urem_one_eq(<4 x i32> %X) nounwind {
443 ; CHECK-SSE-LABEL: test_urem_one_eq:
444 ; CHECK-SSE: # %bb.0:
445 ; CHECK-SSE-NEXT: movaps {{.*#+}} xmm0 = [1,1,1,1]
446 ; CHECK-SSE-NEXT: retq
447 ;
448 ; CHECK-AVX1-LABEL: test_urem_one_eq:
449 ; CHECK-AVX1: # %bb.0:
450 ; CHECK-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [1,1,1,1]
451 ; CHECK-AVX1-NEXT: retq
452 ;
453 ; CHECK-AVX2-LABEL: test_urem_one_eq:
454 ; CHECK-AVX2: # %bb.0:
455 ; CHECK-AVX2-NEXT: vbroadcastss {{.*#+}} xmm0 = [1,1,1,1]
456 ; CHECK-AVX2-NEXT: retq
457 ;
458 ; CHECK-AVX512VL-LABEL: test_urem_one_eq:
459 ; CHECK-AVX512VL: # %bb.0:
460 ; CHECK-AVX512VL-NEXT: vbroadcastss {{.*#+}} xmm0 = [1,1,1,1]
461 ; CHECK-AVX512VL-NEXT: retq
462 %urem = urem <4 x i32> %X, <i32 1, i32 1, i32 1, i32 1>
463 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
464 %ret = zext <4 x i1> %cmp to <4 x i32>
465 ret <4 x i32> %ret
466 }
467 define <4 x i32> @test_urem_one_ne(<4 x i32> %X) nounwind {
468 ; CHECK-SSE-LABEL: test_urem_one_ne:
469 ; CHECK-SSE: # %bb.0:
470 ; CHECK-SSE-NEXT: xorps %xmm0, %xmm0
471 ; CHECK-SSE-NEXT: retq
472 ;
473 ; CHECK-AVX-LABEL: test_urem_one_ne:
474 ; CHECK-AVX: # %bb.0:
475 ; CHECK-AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
476 ; CHECK-AVX-NEXT: retq
477 %urem = urem <4 x i32> %X, <i32 1, i32 1, i32 1, i32 1>
478 %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
479 %ret = zext <4 x i1> %cmp to <4 x i32>
480 ret <4 x i32> %ret
481 }
483 ; We can lower remainder of division by powers of two much better elsewhere.
484 define <4 x i32> @test_urem_pow2(<4 x i32> %X) nounwind {
485 ; CHECK-SSE-LABEL: test_urem_pow2:
486 ; CHECK-SSE: # %bb.0:
487 ; CHECK-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
488 ; CHECK-SSE-NEXT: pxor %xmm1, %xmm1
489 ; CHECK-SSE-NEXT: pcmpeqd %xmm1, %xmm0
490 ; CHECK-SSE-NEXT: psrld $31, %xmm0
491 ; CHECK-SSE-NEXT: retq
492 ;
493 ; CHECK-AVX1-LABEL: test_urem_pow2:
494 ; CHECK-AVX1: # %bb.0:
495 ; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
496 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
497 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
498 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
499 ; CHECK-AVX1-NEXT: retq
500 ;
501 ; CHECK-AVX2-LABEL: test_urem_pow2:
502 ; CHECK-AVX2: # %bb.0:
503 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [15,15,15,15]
504 ; CHECK-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
505 ; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
506 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
507 ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
508 ; CHECK-AVX2-NEXT: retq
509 ;
510 ; CHECK-AVX512VL-LABEL: test_urem_pow2:
511 ; CHECK-AVX512VL: # %bb.0:
512 ; CHECK-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
513 ; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
514 ; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
515 ; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
516 ; CHECK-AVX512VL-NEXT: retq
517 %urem = urem <4 x i32> %X, <i32 16, i32 16, i32 16, i32 16>
518 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
519 %ret = zext <4 x i1> %cmp to <4 x i32>
520 ret <4 x i32> %ret
521 }
523 ; We could lower remainder of division by INT_MIN much better elsewhere.
524 define <4 x i32> @test_urem_int_min(<4 x i32> %X) nounwind {
525 ; CHECK-SSE-LABEL: test_urem_int_min:
526 ; CHECK-SSE: # %bb.0:
527 ; CHECK-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
528 ; CHECK-SSE-NEXT: pxor %xmm1, %xmm1
529 ; CHECK-SSE-NEXT: pcmpeqd %xmm1, %xmm0
530 ; CHECK-SSE-NEXT: psrld $31, %xmm0
531 ; CHECK-SSE-NEXT: retq
532 ;
533 ; CHECK-AVX1-LABEL: test_urem_int_min:
534 ; CHECK-AVX1: # %bb.0:
535 ; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
536 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
537 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
538 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
539 ; CHECK-AVX1-NEXT: retq
540 ;
541 ; CHECK-AVX2-LABEL: test_urem_int_min:
542 ; CHECK-AVX2: # %bb.0:
543 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483647,2147483647,2147483647,2147483647]
544 ; CHECK-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
545 ; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
546 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
547 ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
548 ; CHECK-AVX2-NEXT: retq
549 ;
550 ; CHECK-AVX512VL-LABEL: test_urem_int_min:
551 ; CHECK-AVX512VL: # %bb.0:
552 ; CHECK-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
553 ; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
554 ; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
555 ; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
556 ; CHECK-AVX512VL-NEXT: retq
557 %urem = urem <4 x i32> %X, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
558 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
559 %ret = zext <4 x i1> %cmp to <4 x i32>
560 ret <4 x i32> %ret
561 }
563 ; We could lower remainder of division by all-ones much better elsewhere.
564 define <4 x i32> @test_urem_allones(<4 x i32> %X) nounwind {
565 ; CHECK-SSE2-LABEL: test_urem_allones:
566 ; CHECK-SSE2: # %bb.0:
567 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
568 ; CHECK-SSE2-NEXT: psubd %xmm0, %xmm1
569 ; CHECK-SSE2-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
570 ; CHECK-SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
571 ; CHECK-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
572 ; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm0
573 ; CHECK-SSE2-NEXT: retq
574 ;
575 ; CHECK-SSE41-LABEL: test_urem_allones:
576 ; CHECK-SSE41: # %bb.0:
577 ; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
578 ; CHECK-SSE41-NEXT: psubd %xmm0, %xmm1
579 ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [1,1,1,1]
580 ; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0
581 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
582 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
583 ; CHECK-SSE41-NEXT: retq
584 ;
585 ; CHECK-AVX1-LABEL: test_urem_allones:
586 ; CHECK-AVX1: # %bb.0:
587 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
588 ; CHECK-AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0
589 ; CHECK-AVX1-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
590 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
591 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
592 ; CHECK-AVX1-NEXT: retq
593 ;
594 ; CHECK-AVX2-LABEL: test_urem_allones:
595 ; CHECK-AVX2: # %bb.0:
596 ; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
597 ; CHECK-AVX2-NEXT: vpsubd %xmm0, %xmm1, %xmm0
598 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]
599 ; CHECK-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm1
600 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
601 ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
602 ; CHECK-AVX2-NEXT: retq
603 ;
604 ; CHECK-AVX512VL-LABEL: test_urem_allones:
605 ; CHECK-AVX512VL: # %bb.0:
606 ; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
607 ; CHECK-AVX512VL-NEXT: vpsubd %xmm0, %xmm1, %xmm0
608 ; CHECK-AVX512VL-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1
609 ; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
610 ; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
611 ; CHECK-AVX512VL-NEXT: retq
612 %urem = urem <4 x i32> %X, <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>
613 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
614 %ret = zext <4 x i1> %cmp to <4 x i32>
615 ret <4 x i32> %ret
616 }