1 ; RUN: llc -mtriple=aarch64-none-eabi -lsr-preferred-addressing-mode=preindexed %s -o - | FileCheck %s
3 ; In LSR for constant offsets and steps, we can generate pre-inc
4 ; accesses by having the offset equal the step and generate a reuse
5 ; formula. However, there are cases where the step, results in an
6 ; illegal addressing mode.
8 ; In this test, we set the preferred addressing mode to be preindexed,
9 ; in order to test a scenario where the step results in an illegal
10 ; addressing mode and because of that it should not generate a reuse formula.
12 ; This test was created in order to reproduce a bug that was observed
13 ; when building a bootstrap build on an AArch64 machine, where the
14 ; preferred addresing mode is preindexed.
17 %"Type" = type <{[166 x [338 x i8]]}>
18 define void @test_lsr_pre_inc_offset_check(%"Type"* %p) {
19 ; CHECK-LABEL: test_lsr_pre_inc_offset_check:
20 ; CHECK: // %bb.0: // %entry
21 ; CHECK-NEXT: add x8, x0, #340
22 ; CHECK-NEXT: mov w9, #165
23 ; CHECK-NEXT: mov w10, #2
24 ; CHECK-NEXT: .LBB0_1: // %main
25 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
26 ; CHECK-NEXT: stur wzr, [x8, #-1]
27 ; CHECK-NEXT: strb w10, [x8]
28 ; CHECK-NEXT: subs x9, x9, #1
29 ; CHECK-NEXT: add x8, x8, #338
30 ; CHECK-NEXT: b.ne .LBB0_1
31 ; CHECK-NEXT: // %bb.2: // %exit
38 %arrayidx.i = getelementptr inbounds %"Type", %"Type"* %p, i64 0, i32 0, i64 %indvars, i64 1
39 %0 = bitcast i8* %arrayidx.i to i32*
40 store i32 0, i32* %0, align 1
43 %arrayidx.p = getelementptr inbounds %"Type", %"Type"* %p, i64 0, i32 0, i64 %indvars, i64 2
44 store i8 2, i8* %arrayidx.p, align 1
45 %indvars.iv.next = add nuw nsw i64 %indvars, 1
46 %add.i = add nuw i8 %begin, 1
47 %cmp.i.not = icmp eq i64 %indvars.iv.next, 166
48 br i1 %cmp.i.not, label %exit, label %main
50 %begin = phi i8 [ 1, %entry ], [ %add.i, %if.end ]
51 %indvars = phi i64 [ 1, %entry ], [ %indvars.iv.next, %if.end ]