| blob | b6a2e56a237ebf138149fb92d69748081a5c0658 |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt -O2 -S < %s | FileCheck %s
3 ; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s
6 target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
7 target triple = "x86_64-apple-macosx10.15.0"
9 ; https://llvm.org/PR49055
10 ;
11 ; void loop_or(const unsigned char* __restrict pIn, unsigned int* __restrict pOut, int s) {
12 ; for (int i = 0; i < s; i++) {
13 ; unsigned int pixelChar = pIn[i];
14 ; unsigned int pixel = pixelChar | (pixelChar << 8) | (pixelChar << 16) | (255 << 24);
15 ; pOut[i] = pixel;
16 ; }
17 ; }
18 ;
19 ; We are looking for the shifts to get combined into mul along with vectorization.
21 define void @loop_or(i8* noalias %pIn, i32* noalias %pOut, i32 %s) {
22 ; CHECK-LABEL: @loop_or(
23 ; CHECK-NEXT: entry:
24 ; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[S:%.*]], 0
25 ; CHECK-NEXT: br i1 [[CMP1]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]]
26 ; CHECK: for.body.preheader:
27 ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[S]] to i64
28 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[S]], 8
29 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER4:%.*]], label [[VECTOR_PH:%.*]]
30 ; CHECK: vector.ph:
31 ; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 4294967288
32 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
33 ; CHECK: vector.body:
34 ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
35 ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, i8* [[PIN:%.*]], i64 [[INDEX]]
36 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i8>*
37 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
38 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[TMP0]], i64 4
39 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to <4 x i8>*
40 ; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i8>, <4 x i8>* [[TMP3]], align 1
41 ; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i32>
42 ; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[WIDE_LOAD3]] to <4 x i32>
43 ; CHECK-NEXT: [[TMP6:%.*]] = mul nuw nsw <4 x i32> [[TMP4]], <i32 65792, i32 65792, i32 65792, i32 65792>
44 ; CHECK-NEXT: [[TMP7:%.*]] = mul nuw nsw <4 x i32> [[TMP5]], <i32 65792, i32 65792, i32 65792, i32 65792>
45 ; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i32> [[TMP4]], <i32 -16777216, i32 -16777216, i32 -16777216, i32 -16777216>
46 ; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP5]], <i32 -16777216, i32 -16777216, i32 -16777216, i32 -16777216>
47 ; CHECK-NEXT: [[TMP10:%.*]] = add nsw <4 x i32> [[TMP8]], [[TMP6]]
48 ; CHECK-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[TMP9]], [[TMP7]]
49 ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, i32* [[POUT:%.*]], i64 [[INDEX]]
50 ; CHECK-NEXT: [[TMP13:%.*]] = bitcast i32* [[TMP12]] to <4 x i32>*
51 ; CHECK-NEXT: store <4 x i32> [[TMP10]], <4 x i32>* [[TMP13]], align 4
52 ; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, i32* [[TMP12]], i64 4
53 ; CHECK-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP14]] to <4 x i32>*
54 ; CHECK-NEXT: store <4 x i32> [[TMP11]], <4 x i32>* [[TMP15]], align 4
55 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
56 ; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
57 ; CHECK-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
58 ; CHECK: middle.block:
59 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[WIDE_TRIP_COUNT]]
60 ; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END]], label [[FOR_BODY_PREHEADER4]]
61 ; CHECK: for.body.preheader4:
62 ; CHECK-NEXT: [[INDVARS_IV_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ]
63 ; CHECK-NEXT: br label [[FOR_BODY:%.*]]
64 ; CHECK: for.body:
65 ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ [[INDVARS_IV_PH]], [[FOR_BODY_PREHEADER4]] ]
66 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, i8* [[PIN]], i64 [[INDVARS_IV]]
67 ; CHECK-NEXT: [[TMP17:%.*]] = load i8, i8* [[ARRAYIDX]], align 1
68 ; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP17]] to i32
69 ; CHECK-NEXT: [[REASS_MUL:%.*]] = mul nuw nsw i32 [[CONV]], 65792
70 ; CHECK-NEXT: [[OR2:%.*]] = or i32 [[CONV]], -16777216
71 ; CHECK-NEXT: [[OR3:%.*]] = add nsw i32 [[OR2]], [[REASS_MUL]]
72 ; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[POUT]], i64 [[INDVARS_IV]]
73 ; CHECK-NEXT: store i32 [[OR3]], i32* [[ARRAYIDX5]], align 4
74 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
75 ; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
76 ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
77 ; CHECK: for.end:
78 ; CHECK-NEXT: ret void
79 ;
80 entry:
81 br label %for.cond
83 for.cond:
84 %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
85 %cmp = icmp slt i32 %i.0, %s
86 br i1 %cmp, label %for.body, label %for.cond.cleanup
88 for.cond.cleanup:
89 br label %for.end
91 for.body:
92 %idxprom = sext i32 %i.0 to i64
93 %arrayidx = getelementptr inbounds i8, i8* %pIn, i64 %idxprom
94 %0 = load i8, i8* %arrayidx, align 1
95 %conv = zext i8 %0 to i32
96 %shl = shl i32 %conv, 8
97 %or = or i32 %conv, %shl
98 %shl1 = shl i32 %conv, 16
99 %or2 = or i32 %or, %shl1
100 %or3 = or i32 %or2, -16777216
101 %idxprom4 = sext i32 %i.0 to i64
102 %arrayidx5 = getelementptr inbounds i32, i32* %pOut, i64 %idxprom4
103 store i32 %or3, i32* %arrayidx5, align 4
104 br label %for.inc
106 for.inc:
107 %inc = add nsw i32 %i.0, 1
108 br label %for.cond
110 for.end:
111 ret void
112 }