| blob | d9ecab8cd1e3d5e0050c98bce78a04e6f4a18780 |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -simplifycfg -switch-to-lookup=true -keep-loops=false -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
3 ; RUN: opt < %s -passes='simplifycfg<no-keep-loops;switch-to-lookup>' -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
4 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
5 target triple = "x86_64-unknown-linux-gnu"
7 ; The table for @f
8 ; CHECK: @switch.table.f = private unnamed_addr constant [7 x i32] [i32 55, i32 123, i32 0, i32 -1, i32 27, i32 62, i32 1], align 4
10 ; The char table for char
11 ; CHECK: @switch.table.char = private unnamed_addr constant [9 x i8] c"7{\00\FF\1B>\01!T", align 1
13 ; The float table for @h
14 ; CHECK: @switch.table.h = private unnamed_addr constant [4 x float] [float 0x40091EB860000000, float 0x3FF3BE76C0000000, float 0x4012449BA0000000, float 0x4001AE1480000000], align 4
16 ; The table for @foostring
17 ; CHECK: @switch.table.foostring = private unnamed_addr constant [4 x i8*] [i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str2, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str3, i64 0, i64 0)], align 8
19 ; The table for @earlyreturncrash
20 ; CHECK: @switch.table.earlyreturncrash = private unnamed_addr constant [4 x i32] [i32 42, i32 9, i32 88, i32 5], align 4
22 ; The table for @large
23 ; CHECK: @switch.table.large = private unnamed_addr constant [199 x i32] [i32 1, i32 4, i32 9,
25 ; The table for @cprop
26 ; CHECK: @switch.table.cprop = private unnamed_addr constant [7 x i32] [i32 5, i32 42, i32 126, i32 -452, i32 128, i32 6, i32 7], align 4
28 ; The table for @unreachable_case
29 ; CHECK: @switch.table.unreachable_case = private unnamed_addr constant [9 x i32] [i32 0, i32 0, i32 0, i32 2, i32 -1, i32 1, i32 1, i32 1, i32 1], align 4
31 ; A simple int-to-int selection switch.
32 ; It is dense enough to be replaced by table lookup.
33 ; The result is directly by a ret from an otherwise empty bb,
34 ; so we return early, directly from the lookup bb.
36 define i32 @f(i32 %c) {
37 ; CHECK-LABEL: @f(
38 ; CHECK-NEXT: entry:
39 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 42
40 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 7
41 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
42 ; CHECK: switch.lookup:
43 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.f, i32 0, i32 [[SWITCH_TABLEIDX]]
44 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
45 ; CHECK-NEXT: br label [[RETURN]]
46 ; CHECK: return:
47 ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 15, [[ENTRY:%.*]] ]
48 ; CHECK-NEXT: ret i32 [[RETVAL_0]]
49 ;
50 entry:
51 switch i32 %c, label %sw.default [
52 i32 42, label %return
53 i32 43, label %sw.bb1
54 i32 44, label %sw.bb2
55 i32 45, label %sw.bb3
56 i32 46, label %sw.bb4
57 i32 47, label %sw.bb5
58 i32 48, label %sw.bb6
59 ]
61 sw.bb1: br label %return
62 sw.bb2: br label %return
63 sw.bb3: br label %return
64 sw.bb4: br label %return
65 sw.bb5: br label %return
66 sw.bb6: br label %return
67 sw.default: br label %return
68 return:
69 %retval.0 = phi i32 [ 15, %sw.default ], [ 1, %sw.bb6 ], [ 62, %sw.bb5 ], [ 27, %sw.bb4 ], [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
70 ret i32 %retval.0
72 }
74 ; Same thing, but with i8's
76 define i8 @char(i32 %c) {
77 ; CHECK-LABEL: @char(
78 ; CHECK-NEXT: entry:
79 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 42
80 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 9
81 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
82 ; CHECK: switch.lookup:
83 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [9 x i8], [9 x i8]* @switch.table.char, i32 0, i32 [[SWITCH_TABLEIDX]]
84 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i8, i8* [[SWITCH_GEP]], align 1
85 ; CHECK-NEXT: br label [[RETURN]]
86 ; CHECK: return:
87 ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i8 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 15, [[ENTRY:%.*]] ]
88 ; CHECK-NEXT: ret i8 [[RETVAL_0]]
89 ;
90 entry:
91 switch i32 %c, label %sw.default [
92 i32 42, label %return
93 i32 43, label %sw.bb1
94 i32 44, label %sw.bb2
95 i32 45, label %sw.bb3
96 i32 46, label %sw.bb4
97 i32 47, label %sw.bb5
98 i32 48, label %sw.bb6
99 i32 49, label %sw.bb7
100 i32 50, label %sw.bb8
101 ]
103 sw.bb1: br label %return
104 sw.bb2: br label %return
105 sw.bb3: br label %return
106 sw.bb4: br label %return
107 sw.bb5: br label %return
108 sw.bb6: br label %return
109 sw.bb7: br label %return
110 sw.bb8: br label %return
111 sw.default: br label %return
112 return:
113 %retval.0 = phi i8 [ 15, %sw.default ], [ 84, %sw.bb8 ], [ 33, %sw.bb7 ], [ 1, %sw.bb6 ], [ 62, %sw.bb5 ], [ 27, %sw.bb4 ], [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
114 ret i8 %retval.0
116 }
118 ; A switch used to initialize two variables, an i8 and a float.
120 declare void @dummy(i8 signext, float)
121 define void @h(i32 %x) {
122 ; CHECK-LABEL: @h(
123 ; CHECK-NEXT: entry:
124 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
125 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[SW_EPILOG:%.*]]
126 ; CHECK: switch.lookup:
127 ; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul i32 [[X]], 8
128 ; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i32 89655594, [[SWITCH_SHIFTAMT]]
129 ; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i32 [[SWITCH_DOWNSHIFT]] to i8
130 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x float], [4 x float]* @switch.table.h, i32 0, i32 [[X]]
131 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load float, float* [[SWITCH_GEP]], align 4
132 ; CHECK-NEXT: br label [[SW_EPILOG]]
133 ; CHECK: sw.epilog:
134 ; CHECK-NEXT: [[A_0:%.*]] = phi i8 [ [[SWITCH_MASKED]], [[SWITCH_LOOKUP]] ], [ 7, [[ENTRY:%.*]] ]
135 ; CHECK-NEXT: [[B_0:%.*]] = phi float [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 0x4023FAE140000000, [[ENTRY]] ]
136 ; CHECK-NEXT: call void @dummy(i8 signext [[A_0]], float [[B_0]])
137 ; CHECK-NEXT: ret void
138 ;
139 entry:
140 switch i32 %x, label %sw.default [
141 i32 0, label %sw.epilog
142 i32 1, label %sw.bb1
143 i32 2, label %sw.bb2
144 i32 3, label %sw.bb3
145 ]
147 sw.bb1: br label %sw.epilog
148 sw.bb2: br label %sw.epilog
149 sw.bb3: br label %sw.epilog
150 sw.default: br label %sw.epilog
152 sw.epilog:
153 %a.0 = phi i8 [ 7, %sw.default ], [ 5, %sw.bb3 ], [ 88, %sw.bb2 ], [ 9, %sw.bb1 ], [ 42, %entry ]
154 %b.0 = phi float [ 0x4023FAE140000000, %sw.default ], [ 0x4001AE1480000000, %sw.bb3 ], [ 0x4012449BA0000000, %sw.bb2 ], [ 0x3FF3BE76C0000000, %sw.bb1 ], [ 0x40091EB860000000, %entry ]
155 call void @dummy(i8 signext %a.0, float %b.0)
156 ret void
158 }
161 ; Switch used to return a string.
163 @.str = private unnamed_addr constant [4 x i8] c"foo\00", align 1
164 @.str1 = private unnamed_addr constant [4 x i8] c"bar\00", align 1
165 @.str2 = private unnamed_addr constant [4 x i8] c"baz\00", align 1
166 @.str3 = private unnamed_addr constant [4 x i8] c"qux\00", align 1
167 @.str4 = private unnamed_addr constant [6 x i8] c"error\00", align 1
169 define i8* @foostring(i32 %x) {
170 ; CHECK-LABEL: @foostring(
171 ; CHECK-NEXT: entry:
172 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
173 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
174 ; CHECK: switch.lookup:
175 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* @switch.table.foostring, i32 0, i32 [[X]]
176 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i8*, i8** [[SWITCH_GEP]], align 8
177 ; CHECK-NEXT: br label [[RETURN]]
178 ; CHECK: return:
179 ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i8* [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ getelementptr inbounds ([6 x i8], [6 x i8]* @.str4, i64 0, i64 0), [[ENTRY:%.*]] ]
180 ; CHECK-NEXT: ret i8* [[RETVAL_0]]
181 ;
182 entry:
183 switch i32 %x, label %sw.default [
184 i32 0, label %return
185 i32 1, label %sw.bb1
186 i32 2, label %sw.bb2
187 i32 3, label %sw.bb3
188 ]
190 sw.bb1: br label %return
191 sw.bb2: br label %return
192 sw.bb3: br label %return
193 sw.default: br label %return
195 return:
196 %retval.0 = phi i8* [ getelementptr inbounds ([6 x i8], [6 x i8]* @.str4, i64 0, i64 0), %sw.default ],
197 [ getelementptr inbounds ([4 x i8], [4 x i8]* @.str3, i64 0, i64 0), %sw.bb3 ],
198 [ getelementptr inbounds ([4 x i8], [4 x i8]* @.str2, i64 0, i64 0), %sw.bb2 ],
199 [ getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i64 0, i64 0), %sw.bb1 ],
200 [ getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), %entry ]
201 ret i8* %retval.0
203 }
205 ; Switch used to initialize two values. The first value is returned, the second
206 ; value is not used. This used to make the transformation generate illegal code.
208 define i32 @earlyreturncrash(i32 %x) {
209 ; CHECK-LABEL: @earlyreturncrash(
210 ; CHECK-NEXT: entry:
211 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
212 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[SW_EPILOG:%.*]]
213 ; CHECK: switch.lookup:
214 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.earlyreturncrash, i32 0, i32 [[X]]
215 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
216 ; CHECK-NEXT: [[SWITCH_GEP1:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.earlyreturncrash.1, i32 0, i32 [[X]]
217 ; CHECK-NEXT: [[SWITCH_LOAD2:%.*]] = load i32, i32* [[SWITCH_GEP1]], align 4
218 ; CHECK-NEXT: br label [[SW_EPILOG]]
219 ; CHECK: sw.epilog:
220 ; CHECK-NEXT: [[A_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 7, [[ENTRY:%.*]] ]
221 ; CHECK-NEXT: [[B_0:%.*]] = phi i32 [ [[SWITCH_LOAD2]], [[SWITCH_LOOKUP]] ], [ 10, [[ENTRY]] ]
222 ; CHECK-NEXT: ret i32 [[A_0]]
223 ;
224 entry:
225 switch i32 %x, label %sw.default [
226 i32 0, label %sw.epilog
227 i32 1, label %sw.bb1
228 i32 2, label %sw.bb2
229 i32 3, label %sw.bb3
230 ]
232 sw.bb1: br label %sw.epilog
233 sw.bb2: br label %sw.epilog
234 sw.bb3: br label %sw.epilog
235 sw.default: br label %sw.epilog
237 sw.epilog:
238 %a.0 = phi i32 [ 7, %sw.default ], [ 5, %sw.bb3 ], [ 88, %sw.bb2 ], [ 9, %sw.bb1 ], [ 42, %entry ]
239 %b.0 = phi i32 [ 10, %sw.default ], [ 5, %sw.bb3 ], [ 1, %sw.bb2 ], [ 4, %sw.bb1 ], [ 3, %entry ]
240 ret i32 %a.0
242 }
245 ; Example 7 from http://blog.regehr.org/archives/320
246 ; It is not dense enough for a regular table, but the results
247 ; can be packed into a bitmap.
249 define i32 @crud(i8 zeroext %c) {
250 ; CHECK-LABEL: @crud(
251 ; CHECK-NEXT: entry:
252 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[C:%.*]], 33
253 ; CHECK-NEXT: br i1 [[CMP]], label [[LOR_END:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
254 ; CHECK: switch.early.test:
255 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i8 [[C]], 34
256 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[SWITCH_TABLEIDX]], 59
257 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[LOR_END]]
258 ; CHECK: switch.lookup:
259 ; CHECK-NEXT: [[SWITCH_CAST:%.*]] = zext i8 [[SWITCH_TABLEIDX]] to i59
260 ; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul i59 [[SWITCH_CAST]], 1
261 ; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i59 -288230375765830623, [[SWITCH_SHIFTAMT]]
262 ; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i59 [[SWITCH_DOWNSHIFT]] to i1
263 ; CHECK-NEXT: br label [[LOR_END]]
264 ; CHECK: lor.end:
265 ; CHECK-NEXT: [[TMP1:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ [[SWITCH_MASKED]], [[SWITCH_LOOKUP]] ], [ false, [[SWITCH_EARLY_TEST]] ]
266 ; CHECK-NEXT: [[LOR_EXT:%.*]] = zext i1 [[TMP1]] to i32
267 ; CHECK-NEXT: ret i32 [[LOR_EXT]]
268 ;
269 entry:
270 %cmp = icmp ult i8 %c, 33
271 br i1 %cmp, label %lor.end, label %switch.early.test
273 switch.early.test:
274 switch i8 %c, label %lor.rhs [
275 i8 92, label %lor.end
276 i8 62, label %lor.end
277 i8 60, label %lor.end
278 i8 59, label %lor.end
279 i8 58, label %lor.end
280 i8 46, label %lor.end
281 i8 44, label %lor.end
282 i8 34, label %lor.end
283 i8 39, label %switch.edge
284 ]
286 switch.edge: br label %lor.end
287 lor.rhs: br label %lor.end
289 lor.end:
290 %0 = phi i1 [ true, %switch.early.test ],
291 [ false, %lor.rhs ],
292 [ true, %entry ],
293 [ true, %switch.early.test ],
294 [ true, %switch.early.test ],
295 [ true, %switch.early.test ],
296 [ true, %switch.early.test ],
297 [ true, %switch.early.test ],
298 [ true, %switch.early.test ],
299 [ true, %switch.early.test ],
300 [ true, %switch.edge ]
301 %lor.ext = zext i1 %0 to i32
302 ret i32 %lor.ext
304 }
306 ; PR13946
307 define i32 @overflow(i32 %type) {
308 ; CHECK-LABEL: @overflow(
309 ; CHECK-NEXT: entry:
310 ; CHECK-NEXT: switch i32 [[TYPE:%.*]], label [[IF_END:%.*]] [
311 ; CHECK-NEXT: i32 3, label [[SW_BB3:%.*]]
312 ; CHECK-NEXT: i32 -2147483645, label [[SW_BB3]]
313 ; CHECK-NEXT: i32 1, label [[SW_BB1:%.*]]
314 ; CHECK-NEXT: i32 2, label [[SW_BB2:%.*]]
315 ; CHECK-NEXT: ]
316 ; CHECK: sw.bb1:
317 ; CHECK-NEXT: br label [[IF_END]]
318 ; CHECK: sw.bb2:
319 ; CHECK-NEXT: br label [[IF_END]]
320 ; CHECK: sw.bb3:
321 ; CHECK-NEXT: br label [[IF_END]]
322 ; CHECK: if.end:
323 ; CHECK-NEXT: [[DIRENT_TYPE_0:%.*]] = phi i32 [ 6, [[SW_BB3]] ], [ 5, [[SW_BB2]] ], [ 0, [[SW_BB1]] ], [ 3, [[ENTRY:%.*]] ]
324 ; CHECK-NEXT: ret i32 [[DIRENT_TYPE_0]]
325 ;
326 entry:
327 switch i32 %type, label %sw.default [
328 i32 -2147483648, label %sw.bb
329 i32 0, label %sw.bb
330 i32 1, label %sw.bb1
331 i32 2, label %sw.bb2
332 i32 -2147483645, label %sw.bb3
333 i32 3, label %sw.bb3
334 ]
336 sw.bb: br label %if.end
337 sw.bb1: br label %if.end
338 sw.bb2: br label %if.end
339 sw.bb3: br label %if.end
340 sw.default: br label %if.end
341 if.else: br label %if.end
343 if.end:
344 %dirent_type.0 = phi i32 [ 3, %sw.default ], [ 6, %sw.bb3 ], [ 5, %sw.bb2 ], [ 0, %sw.bb1 ], [ 3, %sw.bb ], [ 0, %if.else ]
345 ret i32 %dirent_type.0
346 }
348 ; PR13985
349 define i1 @undef(i32 %tmp) {
350 ; CHECK-LABEL: @undef(
351 ; CHECK-NEXT: bb:
352 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[TMP:%.*]], 9
353 ; CHECK-NEXT: [[SWITCH_CAST:%.*]] = trunc i32 [[TMP]] to i9
354 ; CHECK-NEXT: [[SWITCH_SHIFTAMT:%.*]] = mul i9 [[SWITCH_CAST]], 1
355 ; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i9 3, [[SWITCH_SHIFTAMT]]
356 ; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = trunc i9 [[SWITCH_DOWNSHIFT]] to i1
357 ; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP0]], i1 [[SWITCH_MASKED]], i1 undef
358 ; CHECK-NEXT: ret i1 [[TMP4]]
359 ;
360 bb:
361 switch i32 %tmp, label %bb3 [
362 i32 0, label %bb1
363 i32 1, label %bb1
364 i32 7, label %bb2
365 i32 8, label %bb2
366 ]
368 bb1: br label %bb3
369 bb2: br label %bb3
371 bb3:
372 %tmp4 = phi i1 [ undef, %bb ], [ false, %bb2 ], [ true, %bb1 ]
373 ret i1 %tmp4
374 }
376 ; Also handle large switches that would be rejected by
377 ; isValueEqualityComparison()
379 define i32 @large(i32 %x) {
380 ; CHECK-LABEL: @large(
381 ; CHECK-NEXT: entry:
382 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
383 ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X]], -10
384 ; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP]], i32 [[MUL]], i32 [[X]]
385 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[SPEC_SELECT]], 1
386 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 199
387 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
388 ; CHECK: switch.lookup:
389 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [199 x i32], [199 x i32]* @switch.table.large, i32 0, i32 [[SWITCH_TABLEIDX]]
390 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
391 ; CHECK-NEXT: br label [[RETURN]]
392 ; CHECK: return:
393 ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ]
394 ; CHECK-NEXT: ret i32 [[RETVAL_0]]
395 ;
396 entry:
397 %cmp = icmp slt i32 %x, 0
398 br i1 %cmp, label %if.then, label %if.end
400 if.then:
401 %mul = mul i32 %x, -10
402 br label %if.end
404 if.end:
405 %x.addr.0 = phi i32 [ %mul, %if.then ], [ %x, %entry ]
406 switch i32 %x.addr.0, label %return [
407 i32 199, label %sw.bb203
408 i32 1, label %sw.bb1
409 i32 2, label %sw.bb2
410 i32 3, label %sw.bb3
411 i32 4, label %sw.bb4
412 i32 5, label %sw.bb5
413 i32 6, label %sw.bb6
414 i32 7, label %sw.bb7
415 i32 8, label %sw.bb8
416 i32 9, label %sw.bb9
417 i32 10, label %sw.bb10
418 i32 11, label %sw.bb11
419 i32 12, label %sw.bb12
420 i32 13, label %sw.bb13
421 i32 14, label %sw.bb14
422 i32 15, label %sw.bb15
423 i32 16, label %sw.bb16
424 i32 17, label %sw.bb17
425 i32 18, label %sw.bb18
426 i32 19, label %sw.bb19
427 i32 20, label %sw.bb20
428 i32 21, label %sw.bb21
429 i32 22, label %sw.bb22
430 i32 23, label %sw.bb23
431 i32 24, label %sw.bb24
432 i32 25, label %sw.bb25
433 i32 26, label %sw.bb26
434 i32 27, label %sw.bb27
435 i32 28, label %sw.bb28
436 i32 29, label %sw.bb29
437 i32 30, label %sw.bb30
438 i32 31, label %sw.bb31
439 i32 32, label %sw.bb32
440 i32 33, label %sw.bb33
441 i32 34, label %sw.bb34
442 i32 35, label %sw.bb35
443 i32 36, label %sw.bb37
444 i32 37, label %sw.bb38
445 i32 38, label %sw.bb39
446 i32 39, label %sw.bb40
447 i32 40, label %sw.bb41
448 i32 41, label %sw.bb42
449 i32 42, label %sw.bb43
450 i32 43, label %sw.bb44
451 i32 44, label %sw.bb45
452 i32 45, label %sw.bb47
453 i32 46, label %sw.bb48
454 i32 47, label %sw.bb49
455 i32 48, label %sw.bb50
456 i32 49, label %sw.bb51
457 i32 50, label %sw.bb52
458 i32 51, label %sw.bb53
459 i32 52, label %sw.bb54
460 i32 53, label %sw.bb55
461 i32 54, label %sw.bb56
462 i32 55, label %sw.bb58
463 i32 56, label %sw.bb59
464 i32 57, label %sw.bb60
465 i32 58, label %sw.bb61
466 i32 59, label %sw.bb62
467 i32 60, label %sw.bb63
468 i32 61, label %sw.bb64
469 i32 62, label %sw.bb65
470 i32 63, label %sw.bb66
471 i32 64, label %sw.bb67
472 i32 65, label %sw.bb68
473 i32 66, label %sw.bb69
474 i32 67, label %sw.bb70
475 i32 68, label %sw.bb71
476 i32 69, label %sw.bb72
477 i32 70, label %sw.bb73
478 i32 71, label %sw.bb74
479 i32 72, label %sw.bb76
480 i32 73, label %sw.bb77
481 i32 74, label %sw.bb78
482 i32 75, label %sw.bb79
483 i32 76, label %sw.bb80
484 i32 77, label %sw.bb81
485 i32 78, label %sw.bb82
486 i32 79, label %sw.bb83
487 i32 80, label %sw.bb84
488 i32 81, label %sw.bb85
489 i32 82, label %sw.bb86
490 i32 83, label %sw.bb87
491 i32 84, label %sw.bb88
492 i32 85, label %sw.bb89
493 i32 86, label %sw.bb90
494 i32 87, label %sw.bb91
495 i32 88, label %sw.bb92
496 i32 89, label %sw.bb93
497 i32 90, label %sw.bb94
498 i32 91, label %sw.bb95
499 i32 92, label %sw.bb96
500 i32 93, label %sw.bb97
501 i32 94, label %sw.bb98
502 i32 95, label %sw.bb99
503 i32 96, label %sw.bb100
504 i32 97, label %sw.bb101
505 i32 98, label %sw.bb102
506 i32 99, label %sw.bb103
507 i32 100, label %sw.bb104
508 i32 101, label %sw.bb105
509 i32 102, label %sw.bb106
510 i32 103, label %sw.bb107
511 i32 104, label %sw.bb108
512 i32 105, label %sw.bb109
513 i32 106, label %sw.bb110
514 i32 107, label %sw.bb111
515 i32 108, label %sw.bb112
516 i32 109, label %sw.bb113
517 i32 110, label %sw.bb114
518 i32 111, label %sw.bb115
519 i32 112, label %sw.bb116
520 i32 113, label %sw.bb117
521 i32 114, label %sw.bb118
522 i32 115, label %sw.bb119
523 i32 116, label %sw.bb120
524 i32 117, label %sw.bb121
525 i32 118, label %sw.bb122
526 i32 119, label %sw.bb123
527 i32 120, label %sw.bb124
528 i32 121, label %sw.bb125
529 i32 122, label %sw.bb126
530 i32 123, label %sw.bb127
531 i32 124, label %sw.bb128
532 i32 125, label %sw.bb129
533 i32 126, label %sw.bb130
534 i32 127, label %sw.bb131
535 i32 128, label %sw.bb132
536 i32 129, label %sw.bb133
537 i32 130, label %sw.bb134
538 i32 131, label %sw.bb135
539 i32 132, label %sw.bb136
540 i32 133, label %sw.bb137
541 i32 134, label %sw.bb138
542 i32 135, label %sw.bb139
543 i32 136, label %sw.bb140
544 i32 137, label %sw.bb141
545 i32 138, label %sw.bb142
546 i32 139, label %sw.bb143
547 i32 140, label %sw.bb144
548 i32 141, label %sw.bb145
549 i32 142, label %sw.bb146
550 i32 143, label %sw.bb147
551 i32 144, label %sw.bb148
552 i32 145, label %sw.bb149
553 i32 146, label %sw.bb150
554 i32 147, label %sw.bb151
555 i32 148, label %sw.bb152
556 i32 149, label %sw.bb153
557 i32 150, label %sw.bb154
558 i32 151, label %sw.bb155
559 i32 152, label %sw.bb156
560 i32 153, label %sw.bb157
561 i32 154, label %sw.bb158
562 i32 155, label %sw.bb159
563 i32 156, label %sw.bb160
564 i32 157, label %sw.bb161
565 i32 158, label %sw.bb162
566 i32 159, label %sw.bb163
567 i32 160, label %sw.bb164
568 i32 161, label %sw.bb165
569 i32 162, label %sw.bb166
570 i32 163, label %sw.bb167
571 i32 164, label %sw.bb168
572 i32 165, label %sw.bb169
573 i32 166, label %sw.bb170
574 i32 167, label %sw.bb171
575 i32 168, label %sw.bb172
576 i32 169, label %sw.bb173
577 i32 170, label %sw.bb174
578 i32 171, label %sw.bb175
579 i32 172, label %sw.bb176
580 i32 173, label %sw.bb177
581 i32 174, label %sw.bb178
582 i32 175, label %sw.bb179
583 i32 176, label %sw.bb180
584 i32 177, label %sw.bb181
585 i32 178, label %sw.bb182
586 i32 179, label %sw.bb183
587 i32 180, label %sw.bb184
588 i32 181, label %sw.bb185
589 i32 182, label %sw.bb186
590 i32 183, label %sw.bb187
591 i32 184, label %sw.bb188
592 i32 185, label %sw.bb189
593 i32 186, label %sw.bb190
594 i32 187, label %sw.bb191
595 i32 188, label %sw.bb192
596 i32 189, label %sw.bb193
597 i32 190, label %sw.bb194
598 i32 191, label %sw.bb195
599 i32 192, label %sw.bb196
600 i32 193, label %sw.bb197
601 i32 194, label %sw.bb198
602 i32 195, label %sw.bb199
603 i32 196, label %sw.bb200
604 i32 197, label %sw.bb201
605 i32 198, label %sw.bb202
606 ]
608 sw.bb1: br label %return
609 sw.bb2: br label %return
610 sw.bb3: br label %return
611 sw.bb4: br label %return
612 sw.bb5: br label %return
613 sw.bb6: br label %return
614 sw.bb7: br label %return
615 sw.bb8: br label %return
616 sw.bb9: br label %return
617 sw.bb10: br label %return
618 sw.bb11: br label %return
619 sw.bb12: br label %return
620 sw.bb13: br label %return
621 sw.bb14: br label %return
622 sw.bb15: br label %return
623 sw.bb16: br label %return
624 sw.bb17: br label %return
625 sw.bb18: br label %return
626 sw.bb19: br label %return
627 sw.bb20: br label %return
628 sw.bb21: br label %return
629 sw.bb22: br label %return
630 sw.bb23: br label %return
631 sw.bb24: br label %return
632 sw.bb25: br label %return
633 sw.bb26: br label %return
634 sw.bb27: br label %return
635 sw.bb28: br label %return
636 sw.bb29: br label %return
637 sw.bb30: br label %return
638 sw.bb31: br label %return
639 sw.bb32: br label %return
640 sw.bb33: br label %return
641 sw.bb34: br label %return
642 sw.bb35: br label %return
643 sw.bb37: br label %return
644 sw.bb38: br label %return
645 sw.bb39: br label %return
646 sw.bb40: br label %return
647 sw.bb41: br label %return
648 sw.bb42: br label %return
649 sw.bb43: br label %return
650 sw.bb44: br label %return
651 sw.bb45: br label %return
652 sw.bb47: br label %return
653 sw.bb48: br label %return
654 sw.bb49: br label %return
655 sw.bb50: br label %return
656 sw.bb51: br label %return
657 sw.bb52: br label %return
658 sw.bb53: br label %return
659 sw.bb54: br label %return
660 sw.bb55: br label %return
661 sw.bb56: br label %return
662 sw.bb58: br label %return
663 sw.bb59: br label %return
664 sw.bb60: br label %return
665 sw.bb61: br label %return
666 sw.bb62: br label %return
667 sw.bb63: br label %return
668 sw.bb64: br label %return
669 sw.bb65: br label %return
670 sw.bb66: br label %return
671 sw.bb67: br label %return
672 sw.bb68: br label %return
673 sw.bb69: br label %return
674 sw.bb70: br label %return
675 sw.bb71: br label %return
676 sw.bb72: br label %return
677 sw.bb73: br label %return
678 sw.bb74: br label %return
679 sw.bb76: br label %return
680 sw.bb77: br label %return
681 sw.bb78: br label %return
682 sw.bb79: br label %return
683 sw.bb80: br label %return
684 sw.bb81: br label %return
685 sw.bb82: br label %return
686 sw.bb83: br label %return
687 sw.bb84: br label %return
688 sw.bb85: br label %return
689 sw.bb86: br label %return
690 sw.bb87: br label %return
691 sw.bb88: br label %return
692 sw.bb89: br label %return
693 sw.bb90: br label %return
694 sw.bb91: br label %return
695 sw.bb92: br label %return
696 sw.bb93: br label %return
697 sw.bb94: br label %return
698 sw.bb95: br label %return
699 sw.bb96: br label %return
700 sw.bb97: br label %return
701 sw.bb98: br label %return
702 sw.bb99: br label %return
703 sw.bb100: br label %return
704 sw.bb101: br label %return
705 sw.bb102: br label %return
706 sw.bb103: br label %return
707 sw.bb104: br label %return
708 sw.bb105: br label %return
709 sw.bb106: br label %return
710 sw.bb107: br label %return
711 sw.bb108: br label %return
712 sw.bb109: br label %return
713 sw.bb110: br label %return
714 sw.bb111: br label %return
715 sw.bb112: br label %return
716 sw.bb113: br label %return
717 sw.bb114: br label %return
718 sw.bb115: br label %return
719 sw.bb116: br label %return
720 sw.bb117: br label %return
721 sw.bb118: br label %return
722 sw.bb119: br label %return
723 sw.bb120: br label %return
724 sw.bb121: br label %return
725 sw.bb122: br label %return
726 sw.bb123: br label %return
727 sw.bb124: br label %return
728 sw.bb125: br label %return
729 sw.bb126: br label %return
730 sw.bb127: br label %return
731 sw.bb128: br label %return
732 sw.bb129: br label %return
733 sw.bb130: br label %return
734 sw.bb131: br label %return
735 sw.bb132: br label %return
736 sw.bb133: br label %return
737 sw.bb134: br label %return
738 sw.bb135: br label %return
739 sw.bb136: br label %return
740 sw.bb137: br label %return
741 sw.bb138: br label %return
742 sw.bb139: br label %return
743 sw.bb140: br label %return
744 sw.bb141: br label %return
745 sw.bb142: br label %return
746 sw.bb143: br label %return
747 sw.bb144: br label %return
748 sw.bb145: br label %return
749 sw.bb146: br label %return
750 sw.bb147: br label %return
751 sw.bb148: br label %return
752 sw.bb149: br label %return
753 sw.bb150: br label %return
754 sw.bb151: br label %return
755 sw.bb152: br label %return
756 sw.bb153: br label %return
757 sw.bb154: br label %return
758 sw.bb155: br label %return
759 sw.bb156: br label %return
760 sw.bb157: br label %return
761 sw.bb158: br label %return
762 sw.bb159: br label %return
763 sw.bb160: br label %return
764 sw.bb161: br label %return
765 sw.bb162: br label %return
766 sw.bb163: br label %return
767 sw.bb164: br label %return
768 sw.bb165: br label %return
769 sw.bb166: br label %return
770 sw.bb167: br label %return
771 sw.bb168: br label %return
772 sw.bb169: br label %return
773 sw.bb170: br label %return
774 sw.bb171: br label %return
775 sw.bb172: br label %return
776 sw.bb173: br label %return
777 sw.bb174: br label %return
778 sw.bb175: br label %return
779 sw.bb176: br label %return
780 sw.bb177: br label %return
781 sw.bb178: br label %return
782 sw.bb179: br label %return
783 sw.bb180: br label %return
784 sw.bb181: br label %return
785 sw.bb182: br label %return
786 sw.bb183: br label %return
787 sw.bb184: br label %return
788 sw.bb185: br label %return
789 sw.bb186: br label %return
790 sw.bb187: br label %return
791 sw.bb188: br label %return
792 sw.bb189: br label %return
793 sw.bb190: br label %return
794 sw.bb191: br label %return
795 sw.bb192: br label %return
796 sw.bb193: br label %return
797 sw.bb194: br label %return
798 sw.bb195: br label %return
799 sw.bb196: br label %return
800 sw.bb197: br label %return
801 sw.bb198: br label %return
802 sw.bb199: br label %return
803 sw.bb200: br label %return
804 sw.bb201: br label %return
805 sw.bb202: br label %return
806 sw.bb203: br label %return
808 return:
809 %retval.0 = phi i32 [ 39204, %sw.bb202 ], [ 38809, %sw.bb201 ], [ 38416, %sw.bb200 ], [ 38025, %sw.bb199 ], [ 37636, %sw.bb198 ], [ 37249, %sw.bb197 ], [ 36864, %sw.bb196 ], [ 36481, %sw.bb195 ], [ 36100, %sw.bb194 ], [ 35721, %sw.bb193 ], [ 35344, %sw.bb192 ], [ 34969, %sw.bb191 ], [ 34596, %sw.bb190 ], [ 34225, %sw.bb189 ], [ 33856, %sw.bb188 ], [ 33489, %sw.bb187 ], [ 33124, %sw.bb186 ], [ 32761, %sw.bb185 ], [ 32400, %sw.bb184 ], [ 32041, %sw.bb183 ], [ 31684, %sw.bb182 ], [ 31329, %sw.bb181 ], [ 30976, %sw.bb180 ], [ 30625, %sw.bb179 ], [ 30276, %sw.bb178 ], [ 29929, %sw.bb177 ], [ 29584, %sw.bb176 ], [ 29241, %sw.bb175 ], [ 28900, %sw.bb174 ], [ 28561, %sw.bb173 ], [ 28224, %sw.bb172 ], [ 27889, %sw.bb171 ], [ 27556, %sw.bb170 ], [ 27225, %sw.bb169 ], [ 26896, %sw.bb168 ], [ 26569, %sw.bb167 ], [ 26244, %sw.bb166 ], [ 25921, %sw.bb165 ], [ 25600, %sw.bb164 ], [ 25281, %sw.bb163 ], [ 24964, %sw.bb162 ], [ 24649, %sw.bb161 ], [ 24336, %sw.bb160 ], [ 24025, %sw.bb159 ], [ 23716, %sw.bb158 ], [ 23409, %sw.bb157 ], [ 23104, %sw.bb156 ], [ 22801, %sw.bb155 ], [ 22500, %sw.bb154 ], [ 22201, %sw.bb153 ], [ 21904, %sw.bb152 ], [ 21609, %sw.bb151 ], [ 21316, %sw.bb150 ], [ 21025, %sw.bb149 ], [ 20736, %sw.bb148 ], [ 20449, %sw.bb147 ], [ 20164, %sw.bb146 ], [ 19881, %sw.bb145 ], [ 19600, %sw.bb144 ], [ 19321, %sw.bb143 ], [ 19044, %sw.bb142 ], [ 18769, %sw.bb141 ], [ 18496, %sw.bb140 ], [ 18225, %sw.bb139 ], [ 17956, %sw.bb138 ], [ 17689, %sw.bb137 ], [ 17424, %sw.bb136 ], [ 17161, %sw.bb135 ], [ 16900, %sw.bb134 ], [ 16641, %sw.bb133 ], [ 16384, %sw.bb132 ], [ 16129, %sw.bb131 ], [ 15876, %sw.bb130 ], [ 15625, %sw.bb129 ], [ 15376, %sw.bb128 ], [ 15129, %sw.bb127 ], [ 14884, %sw.bb126 ], [ 14641, %sw.bb125 ], [ 14400, %sw.bb124 ], [ 14161, %sw.bb123 ], [ 13924, %sw.bb122 ], [ 13689, %sw.bb121 ], [ 13456, %sw.bb120 ], [ 13225, %sw.bb119 ], [ 12996, %sw.bb118 ], [ 12769, %sw.bb117 ], [ 12544, %sw.bb116 ], [ 12321, %sw.bb115 ], [ 12100, %sw.bb114 ], [ 11881, %sw.bb113 ], [ 11664, %sw.bb112 ], [ 11449, %sw.bb111 ], [ 11236, %sw.bb110 ], [ 11025, %sw.bb109 ], [ 10816, %sw.bb108 ], [ 10609, %sw.bb107 ], [ 10404, %sw.bb106 ], [ 10201, %sw.bb105 ], [ 10000, %sw.bb104 ], [ 9801, %sw.bb103 ], [ 9604, %sw.bb102 ], [ 9409, %sw.bb101 ], [ 9216, %sw.bb100 ], [ 9025, %sw.bb99 ], [ 8836, %sw.bb98 ], [ 8649, %sw.bb97 ], [ 8464, %sw.bb96 ], [ 8281, %sw.bb95 ], [ 8100, %sw.bb94 ], [ 7921, %sw.bb93 ], [ 7744, %sw.bb92 ], [ 7569, %sw.bb91 ], [ 7396, %sw.bb90 ], [ 7225, %sw.bb89 ], [ 7056, %sw.bb88 ], [ 6889, %sw.bb87 ], [ 6724, %sw.bb86 ], [ 6561, %sw.bb85 ], [ 6400, %sw.bb84 ], [ 6241, %sw.bb83 ], [ 6084, %sw.bb82 ], [ 5929, %sw.bb81 ], [ 5776, %sw.bb80 ], [ 5625, %sw.bb79 ], [ 5476, %sw.bb78 ], [ 5329, %sw.bb77 ], [ 5184, %sw.bb76 ], [ 5112, %sw.bb74 ], [ 4900, %sw.bb73 ], [ 4761, %sw.bb72 ], [ 4624, %sw.bb71 ], [ 4489, %sw.bb70 ], [ 4356, %sw.bb69 ], [ 4225, %sw.bb68 ], [ 4096, %sw.bb67 ], [ 3969, %sw.bb66 ], [ 3844, %sw.bb65 ], [ 3721, %sw.bb64 ], [ 3600, %sw.bb63 ], [ 3481, %sw.bb62 ], [ 3364, %sw.bb61 ], [ 3249, %sw.bb60 ], [ 3136, %sw.bb59 ], [ 3025, %sw.bb58 ], [ 2970, %sw.bb56 ], [ 2809, %sw.bb55 ], [ 2704, %sw.bb54 ], [ 2601, %sw.bb53 ], [ 2500, %sw.bb52 ], [ 2401, %sw.bb51 ], [ 2304, %sw.bb50 ], [ 2209, %sw.bb49 ], [ 2116, %sw.bb48 ], [ 2025, %sw.bb47 ], [ 1980, %sw.bb45 ], [ 1849, %sw.bb44 ], [ 1764, %sw.bb43 ], [ 1681, %sw.bb42 ], [ 1600, %sw.bb41 ], [ 1521, %sw.bb40 ], [ 1444, %sw.bb39 ], [ 1369, %sw.bb38 ], [ 1296, %sw.bb37 ], [ 1260, %sw.bb35 ], [ 1156, %sw.bb34 ], [ 1089, %sw.bb33 ], [ 1024, %sw.bb32 ], [ 961, %sw.bb31 ], [ 900, %sw.bb30 ], [ 841, %sw.bb29 ], [ 784, %sw.bb28 ], [ 729, %sw.bb27 ], [ 676, %sw.bb26 ], [ 625, %sw.bb25 ], [ 576, %sw.bb24 ], [ 529, %sw.bb23 ], [ 484, %sw.bb22 ], [ 441, %sw.bb21 ], [ 400, %sw.bb20 ], [ 361, %sw.bb19 ], [ 342, %sw.bb18 ], [ 289, %sw.bb17 ], [ 256, %sw.bb16 ], [ 225, %sw.bb15 ], [ 196, %sw.bb14 ], [ 169, %sw.bb13 ], [ 144, %sw.bb12 ], [ 121, %sw.bb11 ], [ 100, %sw.bb10 ], [ 81, %sw.bb9 ], [ 64, %sw.bb8 ], [ 49, %sw.bb7 ], [ 36, %sw.bb6 ], [ 25, %sw.bb5 ], [ 16, %sw.bb4 ], [ 9, %sw.bb3 ], [ 4, %sw.bb2 ], [ 1, %sw.bb1 ], [ 39601, %sw.bb203 ], [ 0, %if.end ]
810 ret i32 %retval.0
811 }
813 define i32 @cprop(i32 %x, i32 %y) {
814 ; CHECK-LABEL: @cprop(
815 ; CHECK-NEXT: entry:
816 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[X:%.*]], 1
817 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 7
818 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
819 ; CHECK: switch.lookup:
820 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.cprop, i32 0, i32 [[SWITCH_TABLEIDX]]
821 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
822 ; CHECK-NEXT: br label [[RETURN]]
823 ; CHECK: return:
824 ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 123, [[ENTRY:%.*]] ]
825 ; CHECK-NEXT: ret i32 [[RETVAL_0]]
826 ;
827 entry:
828 switch i32 %x, label %sw.default [
829 i32 1, label %return
830 i32 2, label %sw.bb1
831 i32 3, label %sw.bb2
832 i32 4, label %sw.bb2
833 i32 5, label %sw.bb2
834 i32 6, label %sw.bb3
835 i32 7, label %sw.bb3
836 ]
838 sw.bb1: br label %return
840 sw.bb2:
841 %and = and i32 %x, 1
842 %and.ptr = inttoptr i32 %and to i8*
843 %tobool = icmp ne i8* %and.ptr, null
844 %cond = select i1 %tobool, i32 -123, i32 456
845 %sub = sub nsw i32 %x, %cond
846 br label %return
848 sw.bb3:
849 %trunc = trunc i32 %x to i8
850 %sext = sext i8 %trunc to i32
851 %select.i = icmp sgt i32 %sext, 0
852 %select = select i1 %select.i, i32 %sext, i32 %y
853 br label %return
855 sw.default:
856 br label %return
858 return:
859 %retval.0 = phi i32 [ 123, %sw.default ], [ %select, %sw.bb3 ], [ %sub, %sw.bb2 ], [ 42, %sw.bb1 ], [ 5, %entry ]
860 ret i32 %retval.0
862 }
864 define i32 @unreachable_case(i32 %x) {
865 ; CHECK-LABEL: @unreachable_case(
866 ; CHECK-NEXT: entry:
867 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 9
868 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
869 ; CHECK: switch.lookup:
870 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [9 x i32], [9 x i32]* @switch.table.unreachable_case, i32 0, i32 [[X]]
871 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
872 ; CHECK-NEXT: br label [[RETURN]]
873 ; CHECK: return:
874 ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 2, [[ENTRY:%.*]] ]
875 ; CHECK-NEXT: ret i32 [[RETVAL_0]]
876 ;
877 entry:
878 switch i32 %x, label %sw.default [
879 i32 0, label %sw.bb
880 i32 1, label %sw.bb
881 i32 2, label %sw.bb
882 i32 3, label %sw.bb1
883 i32 4, label %sw.bb2
884 i32 5, label %sw.bb3
885 i32 6, label %sw.bb3
886 i32 7, label %sw.bb3
887 i32 8, label %sw.bb3
888 ]
890 sw.bb: br label %return
891 sw.bb1: unreachable
892 sw.bb2: br label %return
893 sw.bb3: br label %return
894 sw.default: br label %return
896 return:
897 %retval.0 = phi i32 [ 1, %sw.bb3 ], [ -1, %sw.bb2 ], [ 0, %sw.bb ], [ 2, %sw.default ]
898 ret i32 %retval.0
900 }
902 define i32 @unreachable_default(i32 %x) {
903 ; CHECK-LABEL: @unreachable_default(
904 ; CHECK-NEXT: entry:
905 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.unreachable_default, i32 0, i32 [[X:%.*]]
906 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
907 ; CHECK-NEXT: ret i32 [[SWITCH_LOAD]]
908 ;
909 entry:
910 switch i32 %x, label %default [
911 i32 0, label %bb0
912 i32 1, label %bb1
913 i32 2, label %bb2
914 i32 3, label %bb3
915 ]
917 bb0: br label %return
918 bb1: br label %return
919 bb2: br label %return
920 bb3: br label %return
921 default: unreachable
923 return:
924 %retval = phi i32 [ 42, %bb0 ], [ 52, %bb1 ], [ 1, %bb2 ], [ 2, %bb3 ]
925 ret i32 %retval
927 }
929 ; Don't create a table with illegal type
930 define i96 @illegaltype(i32 %c) {
931 ; CHECK-LABEL: @illegaltype(
932 ; CHECK-NEXT: entry:
933 ; CHECK-NEXT: switch i32 [[C:%.*]], label [[SW_DEFAULT:%.*]] [
934 ; CHECK-NEXT: i32 42, label [[RETURN:%.*]]
935 ; CHECK-NEXT: i32 43, label [[SW_BB1:%.*]]
936 ; CHECK-NEXT: i32 44, label [[SW_BB2:%.*]]
937 ; CHECK-NEXT: i32 45, label [[SW_BB3:%.*]]
938 ; CHECK-NEXT: i32 46, label [[SW_BB4:%.*]]
939 ; CHECK-NEXT: ]
940 ; CHECK: sw.bb1:
941 ; CHECK-NEXT: br label [[RETURN]]
942 ; CHECK: sw.bb2:
943 ; CHECK-NEXT: br label [[RETURN]]
944 ; CHECK: sw.bb3:
945 ; CHECK-NEXT: br label [[RETURN]]
946 ; CHECK: sw.bb4:
947 ; CHECK-NEXT: br label [[RETURN]]
948 ; CHECK: sw.default:
949 ; CHECK-NEXT: br label [[RETURN]]
950 ; CHECK: return:
951 ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i96 [ 15, [[SW_DEFAULT]] ], [ 27, [[SW_BB4]] ], [ -1, [[SW_BB3]] ], [ 0, [[SW_BB2]] ], [ 123, [[SW_BB1]] ], [ 55, [[ENTRY:%.*]] ]
952 ; CHECK-NEXT: ret i96 [[RETVAL_0]]
953 ;
954 entry:
955 switch i32 %c, label %sw.default [
956 i32 42, label %return
957 i32 43, label %sw.bb1
958 i32 44, label %sw.bb2
959 i32 45, label %sw.bb3
960 i32 46, label %sw.bb4
961 ]
963 sw.bb1: br label %return
964 sw.bb2: br label %return
965 sw.bb3: br label %return
966 sw.bb4: br label %return
967 sw.default: br label %return
968 return:
969 %retval.0 = phi i96 [ 15, %sw.default ], [ 27, %sw.bb4 ], [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
970 ret i96 %retval.0
972 }
974 ; If we can build a lookup table without any holes, we don't need a default result.
975 declare void @exit(i32)
976 define i32 @nodefaultnoholes(i32 %c) {
977 ; CHECK-LABEL: @nodefaultnoholes(
978 ; CHECK-NEXT: entry:
979 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[C:%.*]], 4
980 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[SW_DEFAULT:%.*]]
981 ; CHECK: sw.default:
982 ; CHECK-NEXT: call void @exit(i32 1)
983 ; CHECK-NEXT: unreachable
984 ; CHECK: switch.lookup:
985 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.nodefaultnoholes, i32 0, i32 [[C]]
986 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
987 ; CHECK-NEXT: ret i32 [[SWITCH_LOAD]]
988 ;
989 entry:
990 switch i32 %c, label %sw.default [
991 i32 0, label %return
992 i32 1, label %sw.bb1
993 i32 2, label %sw.bb2
994 i32 3, label %sw.bb3
995 ]
997 sw.bb1: br label %return
998 sw.bb2: br label %return
999 sw.bb3: br label %return
1000 sw.default: call void @exit(i32 1)
1001 unreachable
1002 return:
1003 %x = phi i32 [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
1004 ret i32 %x
1006 }
1008 ; This lookup table will have holes, so we need to test for the holes.
1009 define i32 @nodefaultwithholes(i32 %c) {
1010 ; CHECK-LABEL: @nodefaultwithholes(
1011 ; CHECK-NEXT: entry:
1012 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[C:%.*]], 6
1013 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_HOLE_CHECK:%.*]], label [[SW_DEFAULT:%.*]]
1014 ; CHECK: sw.default:
1015 ; CHECK-NEXT: call void @exit(i32 1)
1016 ; CHECK-NEXT: unreachable
1017 ; CHECK: switch.hole_check:
1018 ; CHECK-NEXT: [[SWITCH_MASKINDEX:%.*]] = trunc i32 [[C]] to i8
1019 ; CHECK-NEXT: [[SWITCH_SHIFTED:%.*]] = lshr i8 47, [[SWITCH_MASKINDEX]]
1020 ; CHECK-NEXT: [[SWITCH_LOBIT:%.*]] = trunc i8 [[SWITCH_SHIFTED]] to i1
1021 ; CHECK-NEXT: br i1 [[SWITCH_LOBIT]], label [[SWITCH_LOOKUP:%.*]], label [[SW_DEFAULT]]
1022 ; CHECK: switch.lookup:
1023 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i32], [6 x i32]* @switch.table.nodefaultwithholes, i32 0, i32 [[C]]
1024 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
1025 ; CHECK-NEXT: ret i32 [[SWITCH_LOAD]]
1026 ;
1027 entry:
1028 switch i32 %c, label %sw.default [
1029 i32 0, label %return
1030 i32 1, label %sw.bb1
1031 i32 2, label %sw.bb2
1032 i32 3, label %sw.bb3
1033 i32 5, label %sw.bb3
1034 ]
1036 sw.bb1: br label %return
1037 sw.bb2: br label %return
1038 sw.bb3: br label %return
1039 sw.default: call void @exit(i32 1)
1040 unreachable
1041 return:
1042 %x = phi i32 [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
1043 ret i32 %x
1045 ; The mask is binary 101111.
1046 }
1048 ; We don't build lookup tables with holes for switches with less than four cases.
1049 define i32 @threecasesholes(i32 %c) {
1050 ; CHECK-LABEL: @threecasesholes(
1051 ; CHECK-NEXT: entry:
1052 ; CHECK-NEXT: switch i32 [[C:%.*]], label [[SW_DEFAULT:%.*]] [
1053 ; CHECK-NEXT: i32 0, label [[RETURN:%.*]]
1054 ; CHECK-NEXT: i32 1, label [[SW_BB1:%.*]]
1055 ; CHECK-NEXT: i32 3, label [[SW_BB2:%.*]]
1056 ; CHECK-NEXT: ]
1057 ; CHECK: sw.bb1:
1058 ; CHECK-NEXT: br label [[RETURN]]
1059 ; CHECK: sw.bb2:
1060 ; CHECK-NEXT: br label [[RETURN]]
1061 ; CHECK: sw.default:
1062 ; CHECK-NEXT: br label [[RETURN]]
1063 ; CHECK: return:
1064 ; CHECK-NEXT: [[X:%.*]] = phi i32 [ [[C]], [[SW_DEFAULT]] ], [ 5, [[SW_BB2]] ], [ 7, [[SW_BB1]] ], [ 9, [[ENTRY:%.*]] ]
1065 ; CHECK-NEXT: ret i32 [[X]]
1066 ;
1067 entry:
1068 switch i32 %c, label %sw.default [
1069 i32 0, label %return
1070 i32 1, label %sw.bb1
1071 i32 3, label %sw.bb2
1072 ]
1073 sw.bb1: br label %return
1074 sw.bb2: br label %return
1075 sw.default: br label %return
1076 return:
1077 %x = phi i32 [ %c, %sw.default ], [ 5, %sw.bb2 ], [ 7, %sw.bb1 ], [ 9, %entry ]
1078 ret i32 %x
1079 }
1081 ; We build lookup tables for switches with three or more cases.
1082 define i32 @threecases(i32 %c) {
1083 ; CHECK-LABEL: @threecases(
1084 ; CHECK-NEXT: entry:
1085 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[C:%.*]], 3
1086 ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
1087 ; CHECK: switch.lookup:
1088 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [3 x i32], [3 x i32]* @switch.table.threecases, i32 0, i32 [[C]]
1089 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
1090 ; CHECK-NEXT: br label [[RETURN]]
1091 ; CHECK: return:
1092 ; CHECK-NEXT: [[X:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 3, [[ENTRY:%.*]] ]
1093 ; CHECK-NEXT: ret i32 [[X]]
1094 ;
1095 entry:
1096 switch i32 %c, label %sw.default [
1097 i32 0, label %return
1098 i32 1, label %sw.bb1
1099 i32 2, label %sw.bb2
1100 ]
1101 sw.bb1:
1102 br label %return
1103 sw.bb2:
1104 br label %return
1105 sw.default:
1106 br label %return
1107 return:
1108 %x = phi i32 [ 3, %sw.default ], [ 5, %sw.bb2 ], [ 7, %sw.bb1 ], [ 10, %entry ]
1109 ret i32 %x
1110 }
1112 ; We don't build tables for switches with two cases.
1113 define i32 @twocases(i32 %c) {
1114 ; CHECK-LABEL: @twocases(
1115 ; CHECK-NEXT: entry:
1116 ; CHECK-NEXT: [[SWITCH_SELECTCMP:%.*]] = icmp eq i32 [[C:%.*]], 1
1117 ; CHECK-NEXT: [[SWITCH_SELECT:%.*]] = select i1 [[SWITCH_SELECTCMP]], i32 7, i32 3
1118 ; CHECK-NEXT: [[SWITCH_SELECTCMP1:%.*]] = icmp eq i32 [[C]], 0
1119 ; CHECK-NEXT: [[SWITCH_SELECT2:%.*]] = select i1 [[SWITCH_SELECTCMP1]], i32 9, i32 [[SWITCH_SELECT]]
1120 ; CHECK-NEXT: ret i32 [[SWITCH_SELECT2]]
1121 ;
1122 entry:
1123 switch i32 %c, label %sw.default [
1124 i32 0, label %return
1125 i32 1, label %sw.bb1
1126 ]
1127 sw.bb1:
1128 br label %return
1129 sw.default:
1130 br label %return
1131 return:
1132 %x = phi i32 [ 3, %sw.default ], [ 7, %sw.bb1 ], [ 9, %entry ]
1133 ret i32 %x
1134 }
1136 ; Don't build tables for switches with TLS variables.
1137 @tls_a = thread_local global i32 0
1138 @tls_b = thread_local global i32 0
1139 @tls_c = thread_local global i32 0
1140 @tls_d = thread_local global i32 0
1141 define i32* @tls(i32 %x) {
1142 ; CHECK-LABEL: @tls(
1143 ; CHECK-NEXT: entry:
1144 ; CHECK-NEXT: switch i32 [[X:%.*]], label [[SW_DEFAULT:%.*]] [
1145 ; CHECK-NEXT: i32 0, label [[RETURN:%.*]]
1146 ; CHECK-NEXT: i32 1, label [[SW_BB1:%.*]]
1147 ; CHECK-NEXT: i32 2, label [[SW_BB2:%.*]]
1148 ; CHECK-NEXT: ]
1149 ; CHECK: sw.bb1:
1150 ; CHECK-NEXT: br label [[RETURN]]
1151 ; CHECK: sw.bb2:
1152 ; CHECK-NEXT: br label [[RETURN]]
1153 ; CHECK: sw.default:
1154 ; CHECK-NEXT: br label [[RETURN]]
1155 ; CHECK: return:
1156 ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32* [ @tls_d, [[SW_DEFAULT]] ], [ @tls_c, [[SW_BB2]] ], [ @tls_b, [[SW_BB1]] ], [ @tls_a, [[ENTRY:%.*]] ]
1157 ; CHECK-NEXT: ret i32* [[RETVAL_0]]
1158 ;
1159 entry:
1160 switch i32 %x, label %sw.default [
1161 i32 0, label %return
1162 i32 1, label %sw.bb1
1163 i32 2, label %sw.bb2
1164 ]
1165 sw.bb1:
1166 br label %return
1167 sw.bb2:
1168 br label %return
1169 sw.default:
1170 br label %return
1171 return:
1172 %retval.0 = phi i32* [ @tls_d, %sw.default ], [ @tls_c, %sw.bb2 ], [ @tls_b, %sw.bb1 ], [ @tls_a, %entry ]
1173 ret i32* %retval.0
1174 }
1176 ; Don't build tables for switches with dllimport variables.
1177 @dllimport_a = external dllimport global [3x i32]
1178 @dllimport_b = external dllimport global [3x i32]
1179 @dllimport_c = external dllimport global [3x i32]
1180 @dllimport_d = external dllimport global [3x i32]
1181 define i32* @dllimport(i32 %x) {
1182 ; CHECK-LABEL: @dllimport(
1183 ; CHECK-NEXT: entry:
1184 ; CHECK-NEXT: switch i32 [[X:%.*]], label [[SW_DEFAULT:%.*]] [
1185 ; CHECK-NEXT: i32 0, label [[RETURN:%.*]]
1186 ; CHECK-NEXT: i32 1, label [[SW_BB1:%.*]]
1187 ; CHECK-NEXT: i32 2, label [[SW_BB2:%.*]]
1188 ; CHECK-NEXT: ]
1189 ; CHECK: sw.bb1:
1190 ; CHECK-NEXT: br label [[RETURN]]
1191 ; CHECK: sw.bb2:
1192 ; CHECK-NEXT: br label [[RETURN]]
1193 ; CHECK: sw.default:
1194 ; CHECK-NEXT: br label [[RETURN]]
1195 ; CHECK: return:
1196 ; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32* [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_d, i32 0, i32 0), [[SW_DEFAULT]] ], [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_c, i32 0, i32 0), [[SW_BB2]] ], [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_b, i32 0, i32 0), [[SW_BB1]] ], [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_a, i32 0, i32 0), [[ENTRY:%.*]] ]
1197 ; CHECK-NEXT: ret i32* [[RETVAL_0]]
1198 ;
1199 entry:
1200 switch i32 %x, label %sw.default [
1201 i32 0, label %return
1202 i32 1, label %sw.bb1
1203 i32 2, label %sw.bb2
1204 ]
1205 sw.bb1:
1206 br label %return
1207 sw.bb2:
1208 br label %return
1209 sw.default:
1210 br label %return
1211 return:
1212 %retval.0 = phi i32* [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_d, i32 0, i32 0), %sw.default ],
1213 [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_c, i32 0, i32 0), %sw.bb2 ],
1214 [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_b, i32 0, i32 0), %sw.bb1 ],
1215 [ getelementptr inbounds ([3 x i32], [3 x i32]* @dllimport_a, i32 0, i32 0), %entry ]
1216 ret i32* %retval.0
1217 }
1219 ; We can use linear mapping.
1220 define i8 @linearmap1(i32 %c) {
1221 ; CHECK-LABEL: @linearmap1(
1222 ; CHECK-NEXT: entry:
1223 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 10
1224 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4
1225 ; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = trunc i32 [[SWITCH_TABLEIDX]] to i8
1226 ; CHECK-NEXT: [[SWITCH_IDX_MULT:%.*]] = mul i8 [[SWITCH_IDX_CAST]], -5
1227 ; CHECK-NEXT: [[SWITCH_OFFSET:%.*]] = add i8 [[SWITCH_IDX_MULT]], 18
1228 ; CHECK-NEXT: [[X:%.*]] = select i1 [[TMP0]], i8 [[SWITCH_OFFSET]], i8 3
1229 ; CHECK-NEXT: ret i8 [[X]]
1230 ;
1231 entry:
1232 switch i32 %c, label %sw.default [
1233 i32 10, label %return
1234 i32 11, label %sw.bb1
1235 i32 12, label %sw.bb2
1236 i32 13, label %sw.bb3
1237 ]
1238 sw.bb1: br label %return
1239 sw.bb2: br label %return
1240 sw.bb3: br label %return
1241 sw.default: br label %return
1242 return:
1243 %x = phi i8 [ 3, %sw.default ], [ 3, %sw.bb3 ], [ 8, %sw.bb2 ], [ 13, %sw.bb1 ], [ 18, %entry ]
1244 ret i8 %x
1245 }
1247 ; Linear mapping in a different configuration.
1248 define i32 @linearmap2(i8 %c) {
1249 ; CHECK-LABEL: @linearmap2(
1250 ; CHECK-NEXT: entry:
1251 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i8 [[C:%.*]], -13
1252 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[SWITCH_TABLEIDX]], 4
1253 ; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = zext i8 [[SWITCH_TABLEIDX]] to i32
1254 ; CHECK-NEXT: [[SWITCH_OFFSET:%.*]] = add i32 [[SWITCH_IDX_CAST]], 18
1255 ; CHECK-NEXT: [[X:%.*]] = select i1 [[TMP0]], i32 [[SWITCH_OFFSET]], i32 3
1256 ; CHECK-NEXT: ret i32 [[X]]
1257 ;
1258 entry:
1259 switch i8 %c, label %sw.default [
1260 i8 -10, label %return
1261 i8 -11, label %sw.bb1
1262 i8 -12, label %sw.bb2
1263 i8 -13, label %sw.bb3
1264 ]
1265 sw.bb1: br label %return
1266 sw.bb2: br label %return
1267 sw.bb3: br label %return
1268 sw.default: br label %return
1269 return:
1270 %x = phi i32 [ 3, %sw.default ], [ 18, %sw.bb3 ], [ 19, %sw.bb2 ], [ 20, %sw.bb1 ], [ 21, %entry ]
1271 ret i32 %x
1272 }
1274 ; Linear mapping with overflows.
1275 define i8 @linearmap3(i32 %c) {
1276 ; CHECK-LABEL: @linearmap3(
1277 ; CHECK-NEXT: entry:
1278 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], 10
1279 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4
1280 ; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = trunc i32 [[SWITCH_TABLEIDX]] to i8
1281 ; CHECK-NEXT: [[SWITCH_IDX_MULT:%.*]] = mul i8 [[SWITCH_IDX_CAST]], 100
1282 ; CHECK-NEXT: [[X:%.*]] = select i1 [[TMP0]], i8 [[SWITCH_IDX_MULT]], i8 3
1283 ; CHECK-NEXT: ret i8 [[X]]
1284 ;
1285 entry:
1286 switch i32 %c, label %sw.default [
1287 i32 10, label %return
1288 i32 11, label %sw.bb1
1289 i32 12, label %sw.bb2
1290 i32 13, label %sw.bb3
1291 ]
1292 sw.bb1: br label %return
1293 sw.bb2: br label %return
1294 sw.bb3: br label %return
1295 sw.default: br label %return
1296 return:
1297 %x = phi i8 [ 3, %sw.default ], [ 44, %sw.bb3 ], [ -56, %sw.bb2 ], [ 100, %sw.bb1 ], [ 0, %entry ]
1298 ret i8 %x
1299 }
1301 ; Linear mapping with with multiplier 1 and offset 0.
1302 define i8 @linearmap4(i32 %c) {
1303 ; CHECK-LABEL: @linearmap4(
1304 ; CHECK-NEXT: entry:
1305 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i32 [[C:%.*]], -2
1306 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 4
1307 ; CHECK-NEXT: [[SWITCH_IDX_CAST:%.*]] = trunc i32 [[SWITCH_TABLEIDX]] to i8
1308 ; CHECK-NEXT: [[X:%.*]] = select i1 [[TMP0]], i8 [[SWITCH_IDX_CAST]], i8 3
1309 ; CHECK-NEXT: ret i8 [[X]]
1310 ;
1311 entry:
1312 switch i32 %c, label %sw.default [
1313 i32 -2, label %return
1314 i32 -1, label %sw.bb1
1315 i32 0, label %sw.bb2
1316 i32 1, label %sw.bb3
1317 ]
1318 sw.bb1: br label %return
1319 sw.bb2: br label %return
1320 sw.bb3: br label %return
1321 sw.default: br label %return
1322 return:
1323 %x = phi i8 [ 3, %sw.default ], [ 3, %sw.bb3 ], [ 2, %sw.bb2 ], [ 1, %sw.bb1 ], [ 0, %entry ]
1324 ret i8 %x
1325 }
1327 ; Reuse the inverted table range compare.
1328 define i32 @reuse_cmp1(i32 %x) {
1329 ; CHECK-LABEL: @reuse_cmp1(
1330 ; CHECK-NEXT: entry:
1331 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
1332 ; CHECK-NEXT: [[INVERTED_CMP:%.*]] = xor i1 [[TMP0]], true
1333 ; CHECK-NEXT: [[SWITCH_OFFSET:%.*]] = add i32 [[X]], 10
1334 ; CHECK-NEXT: [[R_0:%.*]] = select i1 [[TMP0]], i32 [[SWITCH_OFFSET]], i32 0
1335 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[R_0]], 0
1336 ; CHECK-NEXT: [[DOTR_0:%.*]] = select i1 [[INVERTED_CMP]], i32 100, i32 [[R_0]]
1337 ; CHECK-NEXT: ret i32 [[DOTR_0]]
1338 ;
1339 entry:
1340 switch i32 %x, label %sw.default [
1341 i32 0, label %sw.bb
1342 i32 1, label %sw.bb1
1343 i32 2, label %sw.bb2
1344 i32 3, label %sw.bb3
1345 ]
1346 sw.bb: br label %sw.epilog
1347 sw.bb1: br label %sw.epilog
1348 sw.bb2: br label %sw.epilog
1349 sw.bb3: br label %sw.epilog
1350 sw.default: br label %sw.epilog
1351 sw.epilog:
1352 %r.0 = phi i32 [ 0, %sw.default ], [ 13, %sw.bb3 ], [ 12, %sw.bb2 ], [ 11, %sw.bb1 ], [ 10, %sw.bb ]
1353 %cmp = icmp eq i32 %r.0, 0 ; This compare can be "replaced".
1354 br i1 %cmp, label %if.then, label %if.end
1355 if.then: br label %return
1356 if.end: br label %return
1357 return:
1358 %retval.0 = phi i32 [ 100, %if.then ], [ %r.0, %if.end ]
1359 ret i32 %retval.0
1360 }
1362 ; Reuse the table range compare.
1363 define i32 @reuse_cmp2(i32 %x) {
1364 ; CHECK-LABEL: @reuse_cmp2(
1365 ; CHECK-NEXT: entry:
1366 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
1367 ; CHECK-NEXT: [[X_:%.*]] = select i1 [[TMP0]], i32 [[X]], i32 4
1368 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[X_]], 4
1369 ; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[TMP0]], i32 [[X_]], i32 100
1370 ; CHECK-NEXT: ret i32 [[RETVAL_0]]
1371 ;
1372 entry:
1373 switch i32 %x, label %sw.default [
1374 i32 0, label %sw.bb
1375 i32 1, label %sw.bb1
1376 i32 2, label %sw.bb2
1377 i32 3, label %sw.bb3
1378 ]
1379 sw.bb: br label %sw.epilog
1380 sw.bb1: br label %sw.epilog
1381 sw.bb2: br label %sw.epilog
1382 sw.bb3: br label %sw.epilog
1383 sw.default: br label %sw.epilog
1384 sw.epilog:
1385 %r.0 = phi i32 [ 4, %sw.default ], [ 3, %sw.bb3 ], [ 2, %sw.bb2 ], [ 1, %sw.bb1 ], [ 0, %sw.bb ]
1386 %cmp = icmp ne i32 %r.0, 4 ; This compare can be "replaced".
1387 br i1 %cmp, label %if.then, label %if.end
1388 if.then: br label %return
1389 if.end: br label %return
1390 return:
1391 %retval.0 = phi i32 [ %r.0, %if.then ], [ 100, %if.end ]
1392 ret i32 %retval.0
1393 }
1395 ; Cannot reuse the table range compare, because the default value is the same
1396 ; as one of the case values.
1397 define i32 @no_reuse_cmp(i32 %x) {
1398 ; CHECK-LABEL: @no_reuse_cmp(
1399 ; CHECK-NEXT: entry:
1400 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
1401 ; CHECK-NEXT: [[SWITCH_OFFSET:%.*]] = add i32 [[X]], 10
1402 ; CHECK-NEXT: [[R_0:%.*]] = select i1 [[TMP0]], i32 [[SWITCH_OFFSET]], i32 12
1403 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[R_0]], 0
1404 ; CHECK-NEXT: [[R_0_:%.*]] = select i1 [[CMP]], i32 [[R_0]], i32 100
1405 ; CHECK-NEXT: ret i32 [[R_0_]]
1406 ;
1407 entry:
1408 switch i32 %x, label %sw.default [
1409 i32 0, label %sw.bb
1410 i32 1, label %sw.bb1
1411 i32 2, label %sw.bb2
1412 i32 3, label %sw.bb3
1413 ]
1414 sw.bb: br label %sw.epilog
1415 sw.bb1: br label %sw.epilog
1416 sw.bb2: br label %sw.epilog
1417 sw.bb3: br label %sw.epilog
1418 sw.default: br label %sw.epilog
1419 sw.epilog:
1420 %r.0 = phi i32 [ 12, %sw.default ], [ 13, %sw.bb3 ], [ 12, %sw.bb2 ], [ 11, %sw.bb1 ], [ 10, %sw.bb ]
1421 %cmp = icmp ne i32 %r.0, 0
1422 br i1 %cmp, label %if.then, label %if.end
1423 if.then: br label %return
1424 if.end: br label %return
1425 return:
1426 %retval.0 = phi i32 [ %r.0, %if.then ], [ 100, %if.end ]
1427 ret i32 %retval.0
1428 }
1430 ; Cannot reuse the table range compare, because the phi at the switch merge
1431 ; point is not dominated by the switch.
1432 define i32 @no_reuse_cmp2(i32 %x, i32 %y) {
1433 ; CHECK-LABEL: @no_reuse_cmp2(
1434 ; CHECK-NEXT: entry:
1435 ; CHECK-NEXT: [[EC:%.*]] = icmp ne i32 [[Y:%.*]], 0
1436 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
1437 ; CHECK-NEXT: [[SWITCH_OFFSET:%.*]] = add i32 [[X]], 10
1438 ; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP0]], i32 [[SWITCH_OFFSET]], i32 0
1439 ; CHECK-NEXT: [[R_0:%.*]] = select i1 [[EC]], i32 [[SPEC_SELECT]], i32 100
1440 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[R_0]], 0
1441 ; CHECK-NEXT: [[DOTR_0:%.*]] = select i1 [[CMP]], i32 100, i32 [[R_0]]
1442 ; CHECK-NEXT: ret i32 [[DOTR_0]]
1443 ;
1444 entry:
1445 %ec = icmp ne i32 %y, 0
1446 br i1 %ec, label %switch.entry, label %sw.epilog
1447 switch.entry:
1448 switch i32 %x, label %sw.default [
1449 i32 0, label %sw.bb
1450 i32 1, label %sw.bb1
1451 i32 2, label %sw.bb2
1452 i32 3, label %sw.bb3
1453 ]
1454 sw.bb: br label %sw.epilog
1455 sw.bb1: br label %sw.epilog
1456 sw.bb2: br label %sw.epilog
1457 sw.bb3: br label %sw.epilog
1458 sw.default: br label %sw.epilog
1459 sw.epilog:
1460 %r.0 = phi i32 [100, %entry], [ 0, %sw.default ], [ 13, %sw.bb3 ], [ 12, %sw.bb2 ], [ 11, %sw.bb1 ], [ 10, %sw.bb ]
1461 %cmp = icmp eq i32 %r.0, 0 ; This compare can be "replaced".
1462 br i1 %cmp, label %if.then, label %if.end
1463 if.then: br label %return
1464 if.end: br label %return
1465 return:
1466 %retval.0 = phi i32 [ 100, %if.then ], [ %r.0, %if.end ]
1467 ret i32 %retval.0
1468 }
1470 define void @pr20210(i8 %x, i1 %y) {
1471 ; %z has uses outside of its BB or the phi it feeds into,
1472 ; so doing a table lookup and jumping directly to while.cond would
1473 ; cause %z to cease dominating all its uses.
1474 ; CHECK-LABEL: @pr20210(
1475 ; CHECK-NEXT: entry:
1476 ; CHECK-NEXT: br i1 [[Y:%.*]], label [[SW:%.*]], label [[INTERMEDIATE:%.*]]
1477 ; CHECK: sw:
1478 ; CHECK-NEXT: switch i8 [[X:%.*]], label [[END:%.*]] [
1479 ; CHECK-NEXT: i8 7, label [[INTERMEDIATE]]
1480 ; CHECK-NEXT: i8 3, label [[INTERMEDIATE]]
1481 ; CHECK-NEXT: i8 2, label [[INTERMEDIATE]]
1482 ; CHECK-NEXT: i8 1, label [[INTERMEDIATE]]
1483 ; CHECK-NEXT: i8 0, label [[INTERMEDIATE]]
1484 ; CHECK-NEXT: ]
1485 ; CHECK: intermediate:
1486 ; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X]] to i32
1487 ; CHECK-NEXT: br label [[WHILE_COND:%.*]]
1488 ; CHECK: while.cond:
1489 ; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[Z]], [[INTERMEDIATE]] ], [ [[J:%.*]], [[WHILE_BODY:%.*]] ]
1490 ; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[I]], 7
1491 ; CHECK-NEXT: br i1 [[B]], label [[WHILE_BODY]], label [[WHILE_END:%.*]]
1492 ; CHECK: while.body:
1493 ; CHECK-NEXT: [[J]] = add i32 [[I]], 1
1494 ; CHECK-NEXT: br label [[WHILE_COND]]
1495 ; CHECK: while.end:
1496 ; CHECK-NEXT: call void @exit(i32 [[Z]])
1497 ; CHECK-NEXT: unreachable
1498 ; CHECK: end:
1499 ; CHECK-NEXT: ret void
1500 ;
1501 entry:
1502 br i1 %y, label %sw, label %intermediate
1504 sw:
1505 switch i8 %x, label %end [
1506 i8 7, label %intermediate
1507 i8 3, label %intermediate
1508 i8 2, label %intermediate
1509 i8 1, label %intermediate
1510 i8 0, label %intermediate
1511 ]
1513 intermediate:
1514 %z = zext i8 %x to i32
1515 br label %while.cond
1517 while.cond:
1518 %i = phi i32 [ %z, %intermediate ], [ %j, %while.body ]
1519 %b = icmp ne i32 %i, 7
1520 br i1 %b, label %while.body, label %while.end
1522 while.body:
1523 %j = add i32 %i, 1
1524 br label %while.cond
1526 while.end:
1527 call void @exit(i32 %z)
1528 unreachable
1530 end:
1531 ret void
1532 }
1534 ; Make sure we do not crash due to trying to generate an unguarded
1535 ; lookup (since i3 can only hold values in the range of explicit
1536 ; values) and simultaneously trying to generate a branch to deal with
1537 ; the fact that we have holes in the range.
1538 define i32 @covered_switch_with_bit_tests(i3) {
1539 ; CHECK-LABEL: @covered_switch_with_bit_tests(
1540 ; CHECK-NEXT: entry:
1541 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = sub i3 [[TMP0:%.*]], -4
1542 ; CHECK-NEXT: [[SWITCH_MASKINDEX:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i8
1543 ; CHECK-NEXT: [[SWITCH_SHIFTED:%.*]] = lshr i8 -61, [[SWITCH_MASKINDEX]]
1544 ; CHECK-NEXT: [[SWITCH_LOBIT:%.*]] = trunc i8 [[SWITCH_SHIFTED]] to i1
1545 ; CHECK-NEXT: br i1 [[SWITCH_LOBIT]], label [[SWITCH_LOOKUP:%.*]], label [[L6:%.*]]
1546 ; CHECK: switch.lookup:
1547 ; CHECK-NEXT: [[SWITCH_TABLEIDX_ZEXT:%.*]] = zext i3 [[SWITCH_TABLEIDX]] to i4
1548 ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], [8 x i32]* @switch.table.covered_switch_with_bit_tests, i32 0, i4 [[SWITCH_TABLEIDX_ZEXT]]
1549 ; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
1550 ; CHECK-NEXT: br label [[L6]]
1551 ; CHECK: l6:
1552 ; CHECK-NEXT: [[R:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ]
1553 ; CHECK-NEXT: ret i32 [[R]]
1554 ;
1555 entry:
1556 switch i3 %0, label %l6 [
1557 i3 -3, label %l5
1558 i3 -4, label %l5
1559 i3 3, label %l1
1560 i3 2, label %l1
1561 ]
1563 l1: br label %l2
1565 l2:
1566 %x = phi i32 [ 1, %l1 ], [ 2, %l5 ]
1567 br label %l6
1569 l5: br label %l2
1571 l6:
1572 %r = phi i32 [ %x, %l2 ], [ 0, %entry ]
1573 ret i32 %r
1574 }
1576 ; Speculation depth must be limited to avoid a zero-cost instruction cycle.
1578 define i32 @PR26308(i1 %B, i64 %load) {
1579 ; CHECK-LABEL: @PR26308(
1580 ; CHECK-NEXT: entry:
1581 ; CHECK-NEXT: br label [[CLEANUP4:%.*]]
1582 ; CHECK: cleanup4:
1583 ; CHECK-NEXT: br label [[CLEANUP4]]
1584 ;
1585 entry:
1586 br label %while.body
1588 while.body:
1589 br label %cleanup
1591 cleanup:
1592 %cleanup.dest.slot.0 = phi i1 [ false, %while.body ]
1593 br i1 %cleanup.dest.slot.0, label %for.cond, label %cleanup4
1595 for.cond:
1596 %e.0 = phi i64* [ undef, %cleanup ], [ %incdec.ptr, %for.cond2 ]
1597 %pi = ptrtoint i64* %e.0 to i64
1598 %incdec.ptr = getelementptr inbounds i64, i64* %e.0, i64 1
1599 br label %for.cond2
1601 for.cond2:
1602 %storemerge = phi i64 [ %pi, %for.cond ], [ %load, %for.cond2 ]
1603 br i1 %B, label %for.cond2, label %for.cond
1605 cleanup4:
1606 br label %while.body
1607 }
1609 declare void @throw(i1)
1611 define void @wineh_test(i64 %val) personality i32 (...)* @__CxxFrameHandler3 {
1612 ; CHECK-LABEL: @wineh_test(
1613 ; CHECK-NEXT: entry:
1614 ; CHECK-NEXT: invoke void @throw(i1 false)
1615 ; CHECK-NEXT: to label [[UNREACHABLE:%.*]] unwind label [[CLEANUP1:%.*]]
1616 ; CHECK: unreachable:
1617 ; CHECK-NEXT: unreachable
1618 ; CHECK: cleanup1:
1619 ; CHECK-NEXT: [[CLEANUPPAD1:%.*]] = cleanuppad within none []
1620 ; CHECK-NEXT: switch i64 [[VAL:%.*]], label [[CLEANUPDONE2:%.*]] [
1621 ; CHECK-NEXT: i64 0, label [[CLEANUPDONE1:%.*]]
1622 ; CHECK-NEXT: i64 1, label [[CLEANUPDONE1]]
1623 ; CHECK-NEXT: i64 6, label [[CLEANUPDONE1]]
1624 ; CHECK-NEXT: ]
1625 ; CHECK: cleanupdone1:
1626 ; CHECK-NEXT: cleanupret from [[CLEANUPPAD1]] unwind label [[CLEANUP2:%.*]]
1627 ; CHECK: cleanupdone2:
1628 ; CHECK-NEXT: cleanupret from [[CLEANUPPAD1]] unwind label [[CLEANUP2]]
1629 ; CHECK: cleanup2:
1630 ; CHECK-NEXT: [[PHI:%.*]] = phi i1 [ true, [[CLEANUPDONE1]] ], [ false, [[CLEANUPDONE2]] ]
1631 ; CHECK-NEXT: [[CLEANUPPAD2:%.*]] = cleanuppad within none []
1632 ; CHECK-NEXT: call void @throw(i1 [[PHI]]) [ "funclet"(token [[CLEANUPPAD2]]) ]
1633 ; CHECK-NEXT: unreachable
1634 ;
1635 entry:
1636 invoke void @throw(i1 false)
1637 to label %unreachable unwind label %cleanup1
1639 unreachable:
1640 unreachable
1642 cleanup1:
1643 %cleanuppad1 = cleanuppad within none []
1644 switch i64 %val, label %cleanupdone2 [
1645 i64 0, label %cleanupdone1
1646 i64 1, label %cleanupdone1
1647 i64 6, label %cleanupdone1
1648 ]
1650 cleanupdone1:
1651 cleanupret from %cleanuppad1 unwind label %cleanup2
1653 cleanupdone2:
1654 cleanupret from %cleanuppad1 unwind label %cleanup2
1656 cleanup2:
1657 %phi = phi i1 [ true, %cleanupdone1 ], [ false, %cleanupdone2 ]
1658 %cleanuppad2 = cleanuppad within none []
1659 call void @throw(i1 %phi) [ "funclet"(token %cleanuppad2) ]
1660 unreachable
1661 }
1663 declare i32 @__CxxFrameHandler3(...)