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[ORC] Add std::tuple support to SimplePackedSerialization.
[llvm-project.git] / llvm / utils / TableGen / CodeGenTarget.cpp
blob137f99078faf6b43102d27b2a3f0b8f0b69c01d3
1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class wraps target description classes used by the various code
10 // generation TableGen backends. This makes it easier to access the data and
11 // provides a single place that needs to check it for validity. All of these
12 // classes abort on error conditions.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "CodeGenTarget.h"
17 #include "CodeGenDAGPatterns.h"
18 #include "CodeGenIntrinsics.h"
19 #include "CodeGenSchedule.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/Timer.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include "llvm/TableGen/TableGenBackend.h"
27 #include <algorithm>
28 using namespace llvm;
29
30 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
31 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");
32
33 static cl::opt<unsigned>
34 AsmParserNum("asmparsernum", cl::init(0),
35 cl::desc("Make -gen-asm-parser emit assembly parser #N"),
36 cl::cat(AsmParserCat));
37
38 static cl::opt<unsigned>
39 AsmWriterNum("asmwriternum", cl::init(0),
40 cl::desc("Make -gen-asm-writer emit assembly writer #N"),
41 cl::cat(AsmWriterCat));
42
43 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
44 /// record corresponds to.
45 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
47 }
48
49 StringRef llvm::getName(MVT::SimpleValueType T) {
50 switch (T) {
51 case MVT::Other: return "UNKNOWN";
52 case MVT::iPTR: return "TLI.getPointerTy()";
53 case MVT::iPTRAny: return "TLI.getPointerTy()";
54 default: return getEnumName(T);
55 }
56 }
57
58 StringRef llvm::getEnumName(MVT::SimpleValueType T) {
59 switch (T) {
60 case MVT::Other: return "MVT::Other";
61 case MVT::i1: return "MVT::i1";
62 case MVT::i8: return "MVT::i8";
63 case MVT::i16: return "MVT::i16";
64 case MVT::i32: return "MVT::i32";
65 case MVT::i64: return "MVT::i64";
66 case MVT::i128: return "MVT::i128";
67 case MVT::Any: return "MVT::Any";
68 case MVT::iAny: return "MVT::iAny";
69 case MVT::fAny: return "MVT::fAny";
70 case MVT::vAny: return "MVT::vAny";
71 case MVT::f16: return "MVT::f16";
72 case MVT::bf16: return "MVT::bf16";
73 case MVT::f32: return "MVT::f32";
74 case MVT::f64: return "MVT::f64";
75 case MVT::f80: return "MVT::f80";
76 case MVT::f128: return "MVT::f128";
77 case MVT::ppcf128: return "MVT::ppcf128";
78 case MVT::x86mmx: return "MVT::x86mmx";
79 case MVT::x86amx: return "MVT::x86amx";
80 case MVT::i64x8: return "MVT::i64x8";
81 case MVT::Glue: return "MVT::Glue";
82 case MVT::isVoid: return "MVT::isVoid";
83 case MVT::v1i1: return "MVT::v1i1";
84 case MVT::v2i1: return "MVT::v2i1";
85 case MVT::v4i1: return "MVT::v4i1";
86 case MVT::v8i1: return "MVT::v8i1";
87 case MVT::v16i1: return "MVT::v16i1";
88 case MVT::v32i1: return "MVT::v32i1";
89 case MVT::v64i1: return "MVT::v64i1";
90 case MVT::v128i1: return "MVT::v128i1";
91 case MVT::v256i1: return "MVT::v256i1";
92 case MVT::v512i1: return "MVT::v512i1";
93 case MVT::v1024i1: return "MVT::v1024i1";
94 case MVT::v1i8: return "MVT::v1i8";
95 case MVT::v2i8: return "MVT::v2i8";
96 case MVT::v4i8: return "MVT::v4i8";
97 case MVT::v8i8: return "MVT::v8i8";
98 case MVT::v16i8: return "MVT::v16i8";
99 case MVT::v32i8: return "MVT::v32i8";
100 case MVT::v64i8: return "MVT::v64i8";
101 case MVT::v128i8: return "MVT::v128i8";
102 case MVT::v256i8: return "MVT::v256i8";
103 case MVT::v512i8: return "MVT::v512i8";
104 case MVT::v1024i8: return "MVT::v1024i8";
105 case MVT::v1i16: return "MVT::v1i16";
106 case MVT::v2i16: return "MVT::v2i16";
107 case MVT::v3i16: return "MVT::v3i16";
108 case MVT::v4i16: return "MVT::v4i16";
109 case MVT::v8i16: return "MVT::v8i16";
110 case MVT::v16i16: return "MVT::v16i16";
111 case MVT::v32i16: return "MVT::v32i16";
112 case MVT::v64i16: return "MVT::v64i16";
113 case MVT::v128i16: return "MVT::v128i16";
114 case MVT::v256i16: return "MVT::v256i16";
115 case MVT::v512i16: return "MVT::v512i16";
116 case MVT::v1i32: return "MVT::v1i32";
117 case MVT::v2i32: return "MVT::v2i32";
118 case MVT::v3i32: return "MVT::v3i32";
119 case MVT::v4i32: return "MVT::v4i32";
120 case MVT::v5i32: return "MVT::v5i32";
121 case MVT::v6i32: return "MVT::v6i32";
122 case MVT::v7i32: return "MVT::v7i32";
123 case MVT::v8i32: return "MVT::v8i32";
124 case MVT::v16i32: return "MVT::v16i32";
125 case MVT::v32i32: return "MVT::v32i32";
126 case MVT::v64i32: return "MVT::v64i32";
127 case MVT::v128i32: return "MVT::v128i32";
128 case MVT::v256i32: return "MVT::v256i32";
129 case MVT::v512i32: return "MVT::v512i32";
130 case MVT::v1024i32: return "MVT::v1024i32";
131 case MVT::v2048i32: return "MVT::v2048i32";
132 case MVT::v1i64: return "MVT::v1i64";
133 case MVT::v2i64: return "MVT::v2i64";
134 case MVT::v3i64: return "MVT::v3i64";
135 case MVT::v4i64: return "MVT::v4i64";
136 case MVT::v8i64: return "MVT::v8i64";
137 case MVT::v16i64: return "MVT::v16i64";
138 case MVT::v32i64: return "MVT::v32i64";
139 case MVT::v64i64: return "MVT::v64i64";
140 case MVT::v128i64: return "MVT::v128i64";
141 case MVT::v256i64: return "MVT::v256i64";
142 case MVT::v1i128: return "MVT::v1i128";
143 case MVT::v1f16: return "MVT::v1f16";
144 case MVT::v2f16: return "MVT::v2f16";
145 case MVT::v3f16: return "MVT::v3f16";
146 case MVT::v4f16: return "MVT::v4f16";
147 case MVT::v8f16: return "MVT::v8f16";
148 case MVT::v16f16: return "MVT::v16f16";
149 case MVT::v32f16: return "MVT::v32f16";
150 case MVT::v64f16: return "MVT::v64f16";
151 case MVT::v128f16: return "MVT::v128f16";
152 case MVT::v256f16: return "MVT::v256f16";
153 case MVT::v512f16: return "MVT::v512f16";
154 case MVT::v2bf16: return "MVT::v2bf16";
155 case MVT::v3bf16: return "MVT::v3bf16";
156 case MVT::v4bf16: return "MVT::v4bf16";
157 case MVT::v8bf16: return "MVT::v8bf16";
158 case MVT::v16bf16: return "MVT::v16bf16";
159 case MVT::v32bf16: return "MVT::v32bf16";
160 case MVT::v64bf16: return "MVT::v64bf16";
161 case MVT::v128bf16: return "MVT::v128bf16";
162 case MVT::v1f32: return "MVT::v1f32";
163 case MVT::v2f32: return "MVT::v2f32";
164 case MVT::v3f32: return "MVT::v3f32";
165 case MVT::v4f32: return "MVT::v4f32";
166 case MVT::v5f32: return "MVT::v5f32";
167 case MVT::v6f32: return "MVT::v6f32";
168 case MVT::v7f32: return "MVT::v7f32";
169 case MVT::v8f32: return "MVT::v8f32";
170 case MVT::v16f32: return "MVT::v16f32";
171 case MVT::v32f32: return "MVT::v32f32";
172 case MVT::v64f32: return "MVT::v64f32";
173 case MVT::v128f32: return "MVT::v128f32";
174 case MVT::v256f32: return "MVT::v256f32";
175 case MVT::v512f32: return "MVT::v512f32";
176 case MVT::v1024f32: return "MVT::v1024f32";
177 case MVT::v2048f32: return "MVT::v2048f32";
178 case MVT::v1f64: return "MVT::v1f64";
179 case MVT::v2f64: return "MVT::v2f64";
180 case MVT::v3f64: return "MVT::v3f64";
181 case MVT::v4f64: return "MVT::v4f64";
182 case MVT::v8f64: return "MVT::v8f64";
183 case MVT::v16f64: return "MVT::v16f64";
184 case MVT::v32f64: return "MVT::v32f64";
185 case MVT::v64f64: return "MVT::v64f64";
186 case MVT::v128f64: return "MVT::v128f64";
187 case MVT::v256f64: return "MVT::v256f64";
188 case MVT::nxv1i1: return "MVT::nxv1i1";
189 case MVT::nxv2i1: return "MVT::nxv2i1";
190 case MVT::nxv4i1: return "MVT::nxv4i1";
191 case MVT::nxv8i1: return "MVT::nxv8i1";
192 case MVT::nxv16i1: return "MVT::nxv16i1";
193 case MVT::nxv32i1: return "MVT::nxv32i1";
194 case MVT::nxv64i1: return "MVT::nxv64i1";
195 case MVT::nxv1i8: return "MVT::nxv1i8";
196 case MVT::nxv2i8: return "MVT::nxv2i8";
197 case MVT::nxv4i8: return "MVT::nxv4i8";
198 case MVT::nxv8i8: return "MVT::nxv8i8";
199 case MVT::nxv16i8: return "MVT::nxv16i8";
200 case MVT::nxv32i8: return "MVT::nxv32i8";
201 case MVT::nxv64i8: return "MVT::nxv64i8";
202 case MVT::nxv1i16: return "MVT::nxv1i16";
203 case MVT::nxv2i16: return "MVT::nxv2i16";
204 case MVT::nxv4i16: return "MVT::nxv4i16";
205 case MVT::nxv8i16: return "MVT::nxv8i16";
206 case MVT::nxv16i16: return "MVT::nxv16i16";
207 case MVT::nxv32i16: return "MVT::nxv32i16";
208 case MVT::nxv1i32: return "MVT::nxv1i32";
209 case MVT::nxv2i32: return "MVT::nxv2i32";
210 case MVT::nxv4i32: return "MVT::nxv4i32";
211 case MVT::nxv8i32: return "MVT::nxv8i32";
212 case MVT::nxv16i32: return "MVT::nxv16i32";
213 case MVT::nxv32i32: return "MVT::nxv32i32";
214 case MVT::nxv1i64: return "MVT::nxv1i64";
215 case MVT::nxv2i64: return "MVT::nxv2i64";
216 case MVT::nxv4i64: return "MVT::nxv4i64";
217 case MVT::nxv8i64: return "MVT::nxv8i64";
218 case MVT::nxv16i64: return "MVT::nxv16i64";
219 case MVT::nxv32i64: return "MVT::nxv32i64";
220 case MVT::nxv1f16: return "MVT::nxv1f16";
221 case MVT::nxv2f16: return "MVT::nxv2f16";
222 case MVT::nxv4f16: return "MVT::nxv4f16";
223 case MVT::nxv8f16: return "MVT::nxv8f16";
224 case MVT::nxv16f16: return "MVT::nxv16f16";
225 case MVT::nxv32f16: return "MVT::nxv32f16";
226 case MVT::nxv1bf16: return "MVT::nxv1bf16";
227 case MVT::nxv2bf16: return "MVT::nxv2bf16";
228 case MVT::nxv4bf16: return "MVT::nxv4bf16";
229 case MVT::nxv8bf16: return "MVT::nxv8bf16";
230 case MVT::nxv1f32: return "MVT::nxv1f32";
231 case MVT::nxv2f32: return "MVT::nxv2f32";
232 case MVT::nxv4f32: return "MVT::nxv4f32";
233 case MVT::nxv8f32: return "MVT::nxv8f32";
234 case MVT::nxv16f32: return "MVT::nxv16f32";
235 case MVT::nxv1f64: return "MVT::nxv1f64";
236 case MVT::nxv2f64: return "MVT::nxv2f64";
237 case MVT::nxv4f64: return "MVT::nxv4f64";
238 case MVT::nxv8f64: return "MVT::nxv8f64";
239 case MVT::token: return "MVT::token";
240 case MVT::Metadata: return "MVT::Metadata";
241 case MVT::iPTR: return "MVT::iPTR";
242 case MVT::iPTRAny: return "MVT::iPTRAny";
243 case MVT::Untyped: return "MVT::Untyped";
244 case MVT::funcref: return "MVT::funcref";
245 case MVT::externref: return "MVT::externref";
246 default: llvm_unreachable("ILLEGAL VALUE TYPE!");
247 }
248 }
249
250 /// getQualifiedName - Return the name of the specified record, with a
251 /// namespace qualifier if the record contains one.
252 ///
253 std::string llvm::getQualifiedName(const Record *R) {
254 std::string Namespace;
255 if (R->getValue("Namespace"))
256 Namespace = std::string(R->getValueAsString("Namespace"));
257 if (Namespace.empty())
258 return std::string(R->getName());
259 return Namespace + "::" + R->getName().str();
260 }
261
262
263 /// getTarget - Return the current instance of the Target class.
264 ///
265 CodeGenTarget::CodeGenTarget(RecordKeeper &records)
266 : Records(records), CGH(records) {
267 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
268 if (Targets.size() == 0)
269 PrintFatalError("No 'Target' subclasses defined!");
270 if (Targets.size() != 1)
271 PrintFatalError("Multiple subclasses of Target defined!");
272 TargetRec = Targets[0];
273 }
274
275 CodeGenTarget::~CodeGenTarget() {
276 }
277
278 StringRef CodeGenTarget::getName() const { return TargetRec->getName(); }
279
280 /// getInstNamespace - Find and return the target machine's instruction
281 /// namespace. The namespace is cached because it is requested multiple times.
282 StringRef CodeGenTarget::getInstNamespace() const {
283 if (InstNamespace.empty()) {
284 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
285 // We are not interested in the "TargetOpcode" namespace.
286 if (Inst->Namespace != "TargetOpcode") {
287 InstNamespace = Inst->Namespace;
288 break;
289 }
290 }
291 }
292
293 return InstNamespace;
294 }
295
296 StringRef CodeGenTarget::getRegNamespace() const {
297 auto &RegClasses = RegBank->getRegClasses();
298 return RegClasses.size() > 0 ? RegClasses.front().Namespace : "";
299 }
300
301 Record *CodeGenTarget::getInstructionSet() const {
302 return TargetRec->getValueAsDef("InstructionSet");
303 }
304
305 bool CodeGenTarget::getAllowRegisterRenaming() const {
306 return TargetRec->getValueAsInt("AllowRegisterRenaming");
307 }
308
309 /// getAsmParser - Return the AssemblyParser definition for this target.
310 ///
311 Record *CodeGenTarget::getAsmParser() const {
312 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
313 if (AsmParserNum >= LI.size())
314 PrintFatalError("Target does not have an AsmParser #" +
315 Twine(AsmParserNum) + "!");
316 return LI[AsmParserNum];
317 }
318
319 /// getAsmParserVariant - Return the AssemblyParserVariant definition for
320 /// this target.
321 ///
322 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
323 std::vector<Record*> LI =
324 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
325 if (i >= LI.size())
326 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
327 "!");
328 return LI[i];
329 }
330
331 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition
332 /// available for this target.
333 ///
334 unsigned CodeGenTarget::getAsmParserVariantCount() const {
335 std::vector<Record*> LI =
336 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
337 return LI.size();
338 }
339
340 /// getAsmWriter - Return the AssemblyWriter definition for this target.
341 ///
342 Record *CodeGenTarget::getAsmWriter() const {
343 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
344 if (AsmWriterNum >= LI.size())
345 PrintFatalError("Target does not have an AsmWriter #" +
346 Twine(AsmWriterNum) + "!");
347 return LI[AsmWriterNum];
348 }
349
350 CodeGenRegBank &CodeGenTarget::getRegBank() const {
351 if (!RegBank)
352 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes());
353 return *RegBank;
354 }
355
356 Optional<CodeGenRegisterClass *>
357 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy,
358 CodeGenRegBank &RegBank,
359 const CodeGenSubRegIndex *SubIdx,
360 bool MustBeAllocatable) const {
361 std::vector<CodeGenRegisterClass *> Candidates;
362 auto &RegClasses = RegBank.getRegClasses();
363
364 // Try to find a register class which supports ValueTy, and also contains
365 // SubIdx.
366 for (CodeGenRegisterClass &RC : RegClasses) {
367 // Is there a subclass of this class which contains this subregister index?
368 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx);
369 if (!SubClassWithSubReg)
370 continue;
371
372 // We have a class. Check if it supports this value type.
373 if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy))
374 continue;
375
376 // If necessary, check that it is allocatable.
377 if (MustBeAllocatable && !SubClassWithSubReg->Allocatable)
378 continue;
379
380 // We have a register class which supports both the value type and
381 // subregister index. Remember it.
382 Candidates.push_back(SubClassWithSubReg);
383 }
384
385 // If we didn't find anything, we're done.
386 if (Candidates.empty())
387 return None;
388
389 // Find and return the largest of our candidate classes.
390 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A,
391 const CodeGenRegisterClass *B) {
392 if (A->getMembers().size() > B->getMembers().size())
393 return true;
394
395 if (A->getMembers().size() < B->getMembers().size())
396 return false;
397
398 // Order by name as a tie-breaker.
399 return StringRef(A->getName()) < B->getName();
400 });
401
402 return Candidates[0];
403 }
404
405 void CodeGenTarget::ReadRegAltNameIndices() const {
406 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
407 llvm::sort(RegAltNameIndices, LessRecord());
408 }
409
410 /// getRegisterByName - If there is a register with the specific AsmName,
411 /// return it.
412 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
413 return getRegBank().getRegistersByName().lookup(Name);
414 }
415
416 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
417 const {
418 const CodeGenRegister *Reg = getRegBank().getReg(R);
419 std::vector<ValueTypeByHwMode> Result;
420 for (const auto &RC : getRegBank().getRegClasses()) {
421 if (RC.contains(Reg)) {
422 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
423 llvm::append_range(Result, InVTs);
424 }
425 }
426
427 // Remove duplicates.
428 llvm::sort(Result);
429 Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
430 return Result;
431 }
432
433
434 void CodeGenTarget::ReadLegalValueTypes() const {
435 for (const auto &RC : getRegBank().getRegClasses())
436 llvm::append_range(LegalValueTypes, RC.VTs);
437
438 // Remove duplicates.
439 llvm::sort(LegalValueTypes);
440 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
441 LegalValueTypes.end()),
442 LegalValueTypes.end());
443 }
444
445 CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
446 if (!SchedModels)
447 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this);
448 return *SchedModels;
449 }
450
451 void CodeGenTarget::ReadInstructions() const {
452 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
453 if (Insts.size() <= 2)
454 PrintFatalError("No 'Instruction' subclasses defined!");
455
456 // Parse the instructions defined in the .td file.
457 for (unsigned i = 0, e = Insts.size(); i != e; ++i)
458 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]);
459 }
460
461 static const CodeGenInstruction *
462 GetInstByName(const char *Name,
463 const DenseMap<const Record*,
464 std::unique_ptr<CodeGenInstruction>> &Insts,
465 RecordKeeper &Records) {
466 const Record *Rec = Records.getDef(Name);
467
468 const auto I = Insts.find(Rec);
469 if (!Rec || I == Insts.end())
470 PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
471 return I->second.get();
472 }
473
474 static const char *const FixedInstrs[] = {
475 #define HANDLE_TARGET_OPCODE(OPC) #OPC,
476 #include "llvm/Support/TargetOpcodes.def"
477 nullptr};
478
479 unsigned CodeGenTarget::getNumFixedInstructions() {
480 return array_lengthof(FixedInstrs) - 1;
481 }
482
483 /// Return all of the instructions defined by the target, ordered by
484 /// their enum value.
485 void CodeGenTarget::ComputeInstrsByEnum() const {
486 const auto &Insts = getInstructions();
487 for (const char *const *p = FixedInstrs; *p; ++p) {
488 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
489 assert(Instr && "Missing target independent instruction");
490 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
491 InstrsByEnum.push_back(Instr);
492 }
493 unsigned EndOfPredefines = InstrsByEnum.size();
494 assert(EndOfPredefines == getNumFixedInstructions() &&
495 "Missing generic opcode");
496
497 for (const auto &I : Insts) {
498 const CodeGenInstruction *CGI = I.second.get();
499 if (CGI->Namespace != "TargetOpcode") {
500 InstrsByEnum.push_back(CGI);
501 if (CGI->TheDef->getValueAsBit("isPseudo"))
502 ++NumPseudoInstructions;
503 }
504 }
505
506 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
507
508 // All of the instructions are now in random order based on the map iteration.
509 llvm::sort(
510 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
511 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
512 const auto &D1 = *Rec1->TheDef;
513 const auto &D2 = *Rec2->TheDef;
514 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) <
515 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName());
516 });
517 }
518
519
520 /// isLittleEndianEncoding - Return whether this target encodes its instruction
521 /// in little-endian format, i.e. bits laid out in the order [0..n]
522 ///
523 bool CodeGenTarget::isLittleEndianEncoding() const {
524 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
525 }
526
527 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
528 /// encodings, reverse the bit order of all instructions.
529 void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
530 if (!isLittleEndianEncoding())
531 return;
532
533 std::vector<Record *> Insts =
534 Records.getAllDerivedDefinitions("InstructionEncoding");
535 for (Record *R : Insts) {
536 if (R->getValueAsString("Namespace") == "TargetOpcode" ||
537 R->getValueAsBit("isPseudo"))
538 continue;
539
540 BitsInit *BI = R->getValueAsBitsInit("Inst");
541
542 unsigned numBits = BI->getNumBits();
543
544 SmallVector<Init *, 16> NewBits(numBits);
545
546 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
547 unsigned bitSwapIdx = numBits - bit - 1;
548 Init *OrigBit = BI->getBit(bit);
549 Init *BitSwap = BI->getBit(bitSwapIdx);
550 NewBits[bit] = BitSwap;
551 NewBits[bitSwapIdx] = OrigBit;
552 }
553 if (numBits % 2) {
554 unsigned middle = (numBits + 1) / 2;
555 NewBits[middle] = BI->getBit(middle);
556 }
557
558 BitsInit *NewBI = BitsInit::get(NewBits);
559
560 // Update the bits in reversed order so that emitInstrOpBits will get the
561 // correct endianness.
562 R->getValue("Inst")->setValue(NewBI);
563 }
564 }
565
566 /// guessInstructionProperties - Return true if it's OK to guess instruction
567 /// properties instead of raising an error.
568 ///
569 /// This is configurable as a temporary migration aid. It will eventually be
570 /// permanently false.
571 bool CodeGenTarget::guessInstructionProperties() const {
572 return getInstructionSet()->getValueAsBit("guessInstructionProperties");
573 }
574
575 //===----------------------------------------------------------------------===//
576 // ComplexPattern implementation
577 //
578 ComplexPattern::ComplexPattern(Record *R) {
579 Ty = ::getValueType(R->getValueAsDef("Ty"));
580 NumOperands = R->getValueAsInt("NumOperands");
581 SelectFunc = std::string(R->getValueAsString("SelectFunc"));
582 RootNodes = R->getValueAsListOfDefs("RootNodes");
583
584 // FIXME: This is a hack to statically increase the priority of patterns which
585 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
586 // possible pattern match we'll need to dynamically calculate the complexity
587 // of all patterns a dag can potentially map to.
588 int64_t RawComplexity = R->getValueAsInt("Complexity");
589 if (RawComplexity == -1)
590 Complexity = NumOperands * 3;
591 else
592 Complexity = RawComplexity;
593
594 // FIXME: Why is this different from parseSDPatternOperatorProperties?
595 // Parse the properties.
596 Properties = 0;
597 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
598 for (unsigned i = 0, e = PropList.size(); i != e; ++i)
599 if (PropList[i]->getName() == "SDNPHasChain") {
600 Properties |= 1 << SDNPHasChain;
601 } else if (PropList[i]->getName() == "SDNPOptInGlue") {
602 Properties |= 1 << SDNPOptInGlue;
603 } else if (PropList[i]->getName() == "SDNPMayStore") {
604 Properties |= 1 << SDNPMayStore;
605 } else if (PropList[i]->getName() == "SDNPMayLoad") {
606 Properties |= 1 << SDNPMayLoad;
607 } else if (PropList[i]->getName() == "SDNPSideEffect") {
608 Properties |= 1 << SDNPSideEffect;
609 } else if (PropList[i]->getName() == "SDNPMemOperand") {
610 Properties |= 1 << SDNPMemOperand;
611 } else if (PropList[i]->getName() == "SDNPVariadic") {
612 Properties |= 1 << SDNPVariadic;
613 } else if (PropList[i]->getName() == "SDNPWantRoot") {
614 Properties |= 1 << SDNPWantRoot;
615 } else if (PropList[i]->getName() == "SDNPWantParent") {
616 Properties |= 1 << SDNPWantParent;
617 } else {
618 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" +
619 PropList[i]->getName() +
620 "' on ComplexPattern '" + R->getName() +
621 "'!");
622 }
623 }
624
625 //===----------------------------------------------------------------------===//
626 // CodeGenIntrinsic Implementation
627 //===----------------------------------------------------------------------===//
628
629 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) {
630 std::vector<Record *> IntrProperties =
631 RC.getAllDerivedDefinitions("IntrinsicProperty");
632
633 std::vector<Record *> DefaultProperties;
634 for (Record *Rec : IntrProperties)
635 if (Rec->getValueAsBit("IsDefault"))
636 DefaultProperties.push_back(Rec);
637
638 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic");
639 Intrinsics.reserve(Defs.size());
640
641 for (unsigned I = 0, e = Defs.size(); I != e; ++I)
642 Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties));
643
644 llvm::sort(Intrinsics,
645 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
646 return std::tie(LHS.TargetPrefix, LHS.Name) <
647 std::tie(RHS.TargetPrefix, RHS.Name);
648 });
649 Targets.push_back({"", 0, 0});
650 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I)
651 if (Intrinsics[I].TargetPrefix != Targets.back().Name) {
652 Targets.back().Count = I - Targets.back().Offset;
653 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0});
654 }
655 Targets.back().Count = Intrinsics.size() - Targets.back().Offset;
656 }
657
658 CodeGenIntrinsic::CodeGenIntrinsic(Record *R,
659 std::vector<Record *> DefaultProperties) {
660 TheDef = R;
661 std::string DefName = std::string(R->getName());
662 ArrayRef<SMLoc> DefLoc = R->getLoc();
663 ModRef = ReadWriteMem;
664 Properties = 0;
665 isOverloaded = false;
666 isCommutative = false;
667 canThrow = false;
668 isNoReturn = false;
669 isNoSync = false;
670 isNoFree = false;
671 isWillReturn = false;
672 isCold = false;
673 isNoDuplicate = false;
674 isNoMerge = false;
675 isConvergent = false;
676 isSpeculatable = false;
677 hasSideEffects = false;
678
679 if (DefName.size() <= 4 ||
680 std::string(DefName.begin(), DefName.begin() + 4) != "int_")
681 PrintFatalError(DefLoc,
682 "Intrinsic '" + DefName + "' does not start with 'int_'!");
683
684 EnumName = std::string(DefName.begin()+4, DefName.end());
685
686 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
687 GCCBuiltinName = std::string(R->getValueAsString("GCCBuiltinName"));
688 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field.
689 MSBuiltinName = std::string(R->getValueAsString("MSBuiltinName"));
690
691 TargetPrefix = std::string(R->getValueAsString("TargetPrefix"));
692 Name = std::string(R->getValueAsString("LLVMName"));
693
694 if (Name == "") {
695 // If an explicit name isn't specified, derive one from the DefName.
696 Name = "llvm.";
697
698 for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
699 Name += (EnumName[i] == '_') ? '.' : EnumName[i];
700 } else {
701 // Verify it starts with "llvm.".
702 if (Name.size() <= 5 ||
703 std::string(Name.begin(), Name.begin() + 5) != "llvm.")
704 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
705 "'s name does not start with 'llvm.'!");
706 }
707
708 // If TargetPrefix is specified, make sure that Name starts with
709 // "llvm.<targetprefix>.".
710 if (!TargetPrefix.empty()) {
711 if (Name.size() < 6+TargetPrefix.size() ||
712 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
713 != (TargetPrefix + "."))
714 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
715 "' does not start with 'llvm." +
716 TargetPrefix + ".'!");
717 }
718
719 ListInit *RetTypes = R->getValueAsListInit("RetTypes");
720 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes");
721
722 // First collate a list of overloaded types.
723 std::vector<MVT::SimpleValueType> OverloadedVTs;
724 for (ListInit *TypeList : {RetTypes, ParamTypes}) {
725 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
726 Record *TyEl = TypeList->getElementAsRecord(i);
727 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
728
729 if (TyEl->isSubClassOf("LLVMMatchType"))
730 continue;
731
732 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT"));
733 if (MVT(VT).isOverloaded()) {
734 OverloadedVTs.push_back(VT);
735 isOverloaded = true;
736 }
737 }
738 }
739
740 // Parse the list of return types.
741 ListInit *TypeList = RetTypes;
742 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
743 Record *TyEl = TypeList->getElementAsRecord(i);
744 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
745 MVT::SimpleValueType VT;
746 if (TyEl->isSubClassOf("LLVMMatchType")) {
747 unsigned MatchTy = TyEl->getValueAsInt("Number");
748 assert(MatchTy < OverloadedVTs.size() &&
749 "Invalid matching number!");
750 VT = OverloadedVTs[MatchTy];
751 // It only makes sense to use the extended and truncated vector element
752 // variants with iAny types; otherwise, if the intrinsic is not
753 // overloaded, all the types can be specified directly.
754 assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
755 !TyEl->isSubClassOf("LLVMTruncatedType")) ||
756 VT == MVT::iAny || VT == MVT::vAny) &&
757 "Expected iAny or vAny type");
758 } else {
759 VT = getValueType(TyEl->getValueAsDef("VT"));
760 }
761
762 // Reject invalid types.
763 if (VT == MVT::isVoid)
764 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
765 " has void in result type list!");
766
767 IS.RetVTs.push_back(VT);
768 IS.RetTypeDefs.push_back(TyEl);
769 }
770
771 // Parse the list of parameter types.
772 TypeList = ParamTypes;
773 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) {
774 Record *TyEl = TypeList->getElementAsRecord(i);
775 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
776 MVT::SimpleValueType VT;
777 if (TyEl->isSubClassOf("LLVMMatchType")) {
778 unsigned MatchTy = TyEl->getValueAsInt("Number");
779 if (MatchTy >= OverloadedVTs.size()) {
780 PrintError(R->getLoc(),
781 "Parameter #" + Twine(i) + " has out of bounds matching "
782 "number " + Twine(MatchTy));
783 PrintFatalError(DefLoc,
784 Twine("ParamTypes is ") + TypeList->getAsString());
785 }
786 VT = OverloadedVTs[MatchTy];
787 // It only makes sense to use the extended and truncated vector element
788 // variants with iAny types; otherwise, if the intrinsic is not
789 // overloaded, all the types can be specified directly.
790 assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
791 !TyEl->isSubClassOf("LLVMTruncatedType")) ||
792 VT == MVT::iAny || VT == MVT::vAny) &&
793 "Expected iAny or vAny type");
794 } else
795 VT = getValueType(TyEl->getValueAsDef("VT"));
796
797 // Reject invalid types.
798 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
799 PrintFatalError(DefLoc, "Intrinsic '" + DefName +
800 " has void in result type list!");
801
802 IS.ParamVTs.push_back(VT);
803 IS.ParamTypeDefs.push_back(TyEl);
804 }
805
806 // Parse the intrinsic properties.
807 ListInit *PropList = R->getValueAsListInit("IntrProperties");
808 for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
809 Record *Property = PropList->getElementAsRecord(i);
810 assert(Property->isSubClassOf("IntrinsicProperty") &&
811 "Expected a property!");
812
813 setProperty(Property);
814 }
815
816 // Set default properties to true.
817 setDefaultProperties(R, DefaultProperties);
818
819 // Also record the SDPatternOperator Properties.
820 Properties = parseSDPatternOperatorProperties(R);
821
822 // Sort the argument attributes for later benefit.
823 llvm::sort(ArgumentAttributes);
824 }
825
826 void CodeGenIntrinsic::setDefaultProperties(
827 Record *R, std::vector<Record *> DefaultProperties) {
828 // opt-out of using default attributes.
829 if (R->getValueAsBit("DisableDefaultAttributes"))
830 return;
831
832 for (Record *Rec : DefaultProperties)
833 setProperty(Rec);
834 }
835
836 void CodeGenIntrinsic::setProperty(Record *R) {
837 if (R->getName() == "IntrNoMem")
838 ModRef = NoMem;
839 else if (R->getName() == "IntrReadMem") {
840 if (!(ModRef & MR_Ref))
841 PrintFatalError(TheDef->getLoc(),
842 Twine("IntrReadMem cannot be used after IntrNoMem or "
843 "IntrWriteMem. Default is ReadWrite"));
844 ModRef = ModRefBehavior(ModRef & ~MR_Mod);
845 } else if (R->getName() == "IntrWriteMem") {
846 if (!(ModRef & MR_Mod))
847 PrintFatalError(TheDef->getLoc(),
848 Twine("IntrWriteMem cannot be used after IntrNoMem or "
849 "IntrReadMem. Default is ReadWrite"));
850 ModRef = ModRefBehavior(ModRef & ~MR_Ref);
851 } else if (R->getName() == "IntrArgMemOnly")
852 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem);
853 else if (R->getName() == "IntrInaccessibleMemOnly")
854 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem);
855 else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly")
856 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem |
857 MR_InaccessibleMem);
858 else if (R->getName() == "Commutative")
859 isCommutative = true;
860 else if (R->getName() == "Throws")
861 canThrow = true;
862 else if (R->getName() == "IntrNoDuplicate")
863 isNoDuplicate = true;
864 else if (R->getName() == "IntrNoMerge")
865 isNoMerge = true;
866 else if (R->getName() == "IntrConvergent")
867 isConvergent = true;
868 else if (R->getName() == "IntrNoReturn")
869 isNoReturn = true;
870 else if (R->getName() == "IntrNoSync")
871 isNoSync = true;
872 else if (R->getName() == "IntrNoFree")
873 isNoFree = true;
874 else if (R->getName() == "IntrWillReturn")
875 isWillReturn = !isNoReturn;
876 else if (R->getName() == "IntrCold")
877 isCold = true;
878 else if (R->getName() == "IntrSpeculatable")
879 isSpeculatable = true;
880 else if (R->getName() == "IntrHasSideEffects")
881 hasSideEffects = true;
882 else if (R->isSubClassOf("NoCapture")) {
883 unsigned ArgNo = R->getValueAsInt("ArgNo");
884 ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0);
885 } else if (R->isSubClassOf("NoAlias")) {
886 unsigned ArgNo = R->getValueAsInt("ArgNo");
887 ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0);
888 } else if (R->isSubClassOf("NoUndef")) {
889 unsigned ArgNo = R->getValueAsInt("ArgNo");
890 ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0);
891 } else if (R->isSubClassOf("Returned")) {
892 unsigned ArgNo = R->getValueAsInt("ArgNo");
893 ArgumentAttributes.emplace_back(ArgNo, Returned, 0);
894 } else if (R->isSubClassOf("ReadOnly")) {
895 unsigned ArgNo = R->getValueAsInt("ArgNo");
896 ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0);
897 } else if (R->isSubClassOf("WriteOnly")) {
898 unsigned ArgNo = R->getValueAsInt("ArgNo");
899 ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0);
900 } else if (R->isSubClassOf("ReadNone")) {
901 unsigned ArgNo = R->getValueAsInt("ArgNo");
902 ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0);
903 } else if (R->isSubClassOf("ImmArg")) {
904 unsigned ArgNo = R->getValueAsInt("ArgNo");
905 ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0);
906 } else if (R->isSubClassOf("Align")) {
907 unsigned ArgNo = R->getValueAsInt("ArgNo");
908 uint64_t Align = R->getValueAsInt("Align");
909 ArgumentAttributes.emplace_back(ArgNo, Alignment, Align);
910 } else
911 llvm_unreachable("Unknown property!");
912 }
913
914 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const {
915 if (ParamIdx >= IS.ParamVTs.size())
916 return false;
917 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]);
918 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny;
919 }
920
921 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const {
922 // Convert argument index to attribute index starting from `FirstArgIndex`.
923 ArgAttribute Val{ParamIdx + 1, ImmArg, 0};
924 return std::binary_search(ArgumentAttributes.begin(),
925 ArgumentAttributes.end(), Val);
926 }
LLVM monorepo