llvm/utils/TableGen/CodeGenTarget.h

   1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines wrappers for the Target class and related global
  10 // functionality.  This makes it easier to access the data and provides a single
  11 // place that needs to check it for validity.  All of these classes abort
  12 // on error conditions.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
  17 #define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
  18
  19 #include "CodeGenHwModes.h"
  20 #include "CodeGenInstruction.h"
  21 #include "CodeGenRegisters.h"
  22 #include "InfoByHwMode.h"
  23 #include "SDNodeProperties.h"
  24 #include "llvm/Support/raw_ostream.h"
  25 #include "llvm/TableGen/Record.h"
  26 #include <algorithm>
  27
  28 namespace llvm {
  29
  30 struct CodeGenRegister;
  31 class CodeGenSchedModels;
  32 class CodeGenTarget;
  33
  34 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
  35 /// record corresponds to.
  36 MVT::SimpleValueType getValueType(Record *Rec);
  37
  38 StringRef getName(MVT::SimpleValueType T);
  39 StringRef getEnumName(MVT::SimpleValueType T);
  40
  41 /// getQualifiedName - Return the name of the specified record, with a
  42 /// namespace qualifier if the record contains one.
  43 std::string getQualifiedName(const Record *R);
  44
  45 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
  46 ///
  47 class CodeGenTarget {
  48   RecordKeeper &Records;
  49   Record *TargetRec;
  50
  51   mutable DenseMap<const Record*,
  52                    std::unique_ptr<CodeGenInstruction>> Instructions;
  53   mutable std::unique_ptr<CodeGenRegBank> RegBank;
  54   mutable std::vector<Record*> RegAltNameIndices;
  55   mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
  56   CodeGenHwModes CGH;
  57   void ReadRegAltNameIndices() const;
  58   void ReadInstructions() const;
  59   void ReadLegalValueTypes() const;
  60
  61   mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
  62
  63   mutable StringRef InstNamespace;
  64   mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
  65   mutable unsigned NumPseudoInstructions = 0;
  66 public:
  67   CodeGenTarget(RecordKeeper &Records);
  68   ~CodeGenTarget();
  69
  70   Record *getTargetRecord() const { return TargetRec; }
  71   StringRef getName() const;
  72
  73   /// getInstNamespace - Return the target-specific instruction namespace.
  74   ///
  75   StringRef getInstNamespace() const;
  76
  77   /// getRegNamespace - Return the target-specific register namespace.
  78   StringRef getRegNamespace() const;
  79
  80   /// getInstructionSet - Return the InstructionSet object.
  81   ///
  82   Record *getInstructionSet() const;
  83
  84   /// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for
  85   /// this target.
  86   ///
  87   bool getAllowRegisterRenaming() const;
  88
  89   /// getAsmParser - Return the AssemblyParser definition for this target.
  90   ///
  91   Record *getAsmParser() const;
  92
  93   /// getAsmParserVariant - Return the AssemblyParserVariant definition for
  94   /// this target.
  95   ///
  96   Record *getAsmParserVariant(unsigned i) const;
  97
  98   /// getAsmParserVariantCount - Return the AssemblyParserVariant definition
  99   /// available for this target.
 100   ///
 101   unsigned getAsmParserVariantCount() const;
 102
 103   /// getAsmWriter - Return the AssemblyWriter definition for this target.
 104   ///
 105   Record *getAsmWriter() const;
 106
 107   /// getRegBank - Return the register bank description.
 108   CodeGenRegBank &getRegBank() const;
 109
 110   /// Return the largest register class on \p RegBank which supports \p Ty and
 111   /// covers \p SubIdx if it exists.
 112   Optional<CodeGenRegisterClass *>
 113   getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
 114                        const CodeGenSubRegIndex *SubIdx,
 115                        bool MustBeAllocatable = false) const;
 116
 117   /// getRegisterByName - If there is a register with the specific AsmName,
 118   /// return it.
 119   const CodeGenRegister *getRegisterByName(StringRef Name) const;
 120
 121   const std::vector<Record*> &getRegAltNameIndices() const {
 122     if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
 123     return RegAltNameIndices;
 124   }
 125
 126   const CodeGenRegisterClass &getRegisterClass(Record *R) const {
 127     return *getRegBank().getRegClass(R);
 128   }
 129
 130   /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
 131   /// specified physical register.
 132   std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
 133
 134   ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
 135     if (LegalValueTypes.empty())
 136       ReadLegalValueTypes();
 137     return LegalValueTypes;
 138   }
 139
 140   CodeGenSchedModels &getSchedModels() const;
 141
 142   const CodeGenHwModes &getHwModes() const { return CGH; }
 143
 144 private:
 145   DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> &
 146   getInstructions() const {
 147     if (Instructions.empty()) ReadInstructions();
 148     return Instructions;
 149   }
 150 public:
 151
 152   CodeGenInstruction &getInstruction(const Record *InstRec) const {
 153     if (Instructions.empty()) ReadInstructions();
 154     auto I = Instructions.find(InstRec);
 155     assert(I != Instructions.end() && "Not an instruction");
 156     return *I->second;
 157   }
 158
 159   /// Returns the number of predefined instructions.
 160   static unsigned getNumFixedInstructions();
 161
 162   /// Returns the number of pseudo instructions.
 163   unsigned getNumPseudoInstructions() const {
 164     if (InstrsByEnum.empty())
 165       ComputeInstrsByEnum();
 166     return NumPseudoInstructions;
 167   }
 168
 169   /// Return all of the instructions defined by the target, ordered by their
 170   /// enum value.
 171   /// The following order of instructions is also guaranteed:
 172   /// - fixed / generic instructions as declared in TargetOpcodes.def, in order;
 173   /// - pseudo instructions in lexicographical order sorted by name;
 174   /// - other instructions in lexicographical order sorted by name.
 175   ArrayRef<const CodeGenInstruction *> getInstructionsByEnumValue() const {
 176     if (InstrsByEnum.empty())
 177       ComputeInstrsByEnum();
 178     return InstrsByEnum;
 179   }
 180
 181   typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator;
 182   inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
 183   inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
 184
 185
 186   /// isLittleEndianEncoding - are instruction bit patterns defined as  [0..n]?
 187   ///
 188   bool isLittleEndianEncoding() const;
 189
 190   /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
 191   /// encodings, reverse the bit order of all instructions.
 192   void reverseBitsForLittleEndianEncoding();
 193
 194   /// guessInstructionProperties - should we just guess unset instruction
 195   /// properties?
 196   bool guessInstructionProperties() const;
 197
 198 private:
 199   void ComputeInstrsByEnum() const;
 200 };
 201
 202 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
 203 /// tablegen class in TargetSelectionDAG.td
 204 class ComplexPattern {
 205   MVT::SimpleValueType Ty;
 206   unsigned NumOperands;
 207   std::string SelectFunc;
 208   std::vector<Record*> RootNodes;
 209   unsigned Properties; // Node properties
 210   unsigned Complexity;
 211 public:
 212   ComplexPattern(Record *R);
 213
 214   MVT::SimpleValueType getValueType() const { return Ty; }
 215   unsigned getNumOperands() const { return NumOperands; }
 216   const std::string &getSelectFunc() const { return SelectFunc; }
 217   const std::vector<Record*> &getRootNodes() const {
 218     return RootNodes;
 219   }
 220   bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
 221   unsigned getComplexity() const { return Complexity; }
 222 };
 223
 224 } // End llvm namespace
 225
 226 #endif