clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals --include-generated-funcs
   2 // RUN: %clang_cc1 -std=c++11 -triple aarch64-linux-gnu -emit-llvm %s -o - | FileCheck %s
   3
   4 int __attribute__((target_clones("ls64_v+fp16", "default"))) foo_ovl(int) { return 1; }
   5 int __attribute__((target_clones("ls64_accdata+ls64"))) foo_ovl(void) { return 2; }
   6
   7 int bar() {
   8   return foo_ovl(1) + foo_ovl();
   9 }
  10
  11 template <typename T1, typename T2> struct MyClass {
  12   int __attribute__((target_clones("frintts", "ssbs+sme-f64f64"))) foo_tml() { return 1; }
  13 };
  14
  15 template <typename T> struct MyClass<int, T> {
  16   int __attribute__((target_clones("frintts", "ssbs+sme-f64f64"))) foo_tml() { return 2; }
  17 };
  18
  19 template <typename T> struct MyClass<float, T> {
  20   int foo_tml() { return 3; }
  21 };
  22
  23 template <> struct MyClass<double, float> {
  24   int __attribute__((target_clones("default"))) foo_tml() { return 4; }
  25 };
  26
  27 void run_foo_tml() {
  28   MyClass<short, short> Mc1;
  29   Mc1.foo_tml();
  30   MyClass<int, short> Mc2;
  31   Mc2.foo_tml();
  32   MyClass<float, short> Mc3;
  33   Mc3.foo_tml();
  34   MyClass<double, float> Mc4;
  35   Mc4.foo_tml();
  36 }
  37
  38
  39 // CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
  40 // CHECK: @_Z7foo_ovli.ifunc = weak_odr ifunc i32 (i32), ptr @_Z7foo_ovli.resolver
  41 // CHECK: @_Z7foo_ovlv.ifunc = weak_odr ifunc i32 (), ptr @_Z7foo_ovlv.resolver
  42 // CHECK: @_ZN7MyClassIssE7foo_tmlEv.ifunc = weak_odr ifunc i32 (ptr), ptr @_ZN7MyClassIssE7foo_tmlEv.resolver
  43 // CHECK: @_ZN7MyClassIisE7foo_tmlEv.ifunc = weak_odr ifunc i32 (ptr), ptr @_ZN7MyClassIisE7foo_tmlEv.resolver
  44
  45 // CHECK-LABEL: @_Z7foo_ovli._Mfp16Mls64_v(
  46 // CHECK-NEXT:  entry:
  47 // CHECK-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
  48 // CHECK-NEXT:    store i32 [[TMP0:%.*]], ptr [[DOTADDR]], align 4
  49 // CHECK-NEXT:    ret i32 1
  50 // CHECK-LABEL: @_Z7foo_ovli(
  51 // CHECK-NEXT:  entry:
  52 // CHECK-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
  53 // CHECK-NEXT:    store i32 [[TMP0:%.*]], ptr [[DOTADDR]], align 4
  54 // CHECK-NEXT:    ret i32 1
  55 // CHECK-LABEL: @_Z7foo_ovli.resolver(
  56 // CHECK-NEXT:  resolver_entry:
  57 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
  58 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
  59 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 4503599627436032
  60 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4503599627436032
  61 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
  62 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
  63 // CHECK:       resolver_return:
  64 // CHECK-NEXT:    ret ptr @_Z7foo_ovli._Mfp16Mls64_v
  65 // CHECK:       resolver_else:
  66 // CHECK-NEXT:    ret ptr @_Z7foo_ovli
  67 // CHECK-LABEL: @_Z7foo_ovlv._Mls64Mls64_accdata(
  68 // CHECK-NEXT:  entry:
  69 // CHECK-NEXT:    ret i32 2
  70 // CHECK-LABEL: @_Z7foo_ovlv(
  71 // CHECK-NEXT:  entry:
  72 // CHECK-NEXT:    ret i32 2
  73 // CHECK-LABEL: @_Z7foo_ovlv.resolver(
  74 // CHECK-NEXT:  resolver_entry:
  75 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
  76 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
  77 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 11258999068426240
  78 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 11258999068426240
  79 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
  80 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
  81 // CHECK:       resolver_return:
  82 // CHECK-NEXT:    ret ptr @_Z7foo_ovlv._Mls64Mls64_accdata
  83 // CHECK:       resolver_else:
  84 // CHECK-NEXT:    ret ptr @_Z7foo_ovlv
  85 // CHECK-LABEL: @_Z3barv(
  86 // CHECK-NEXT:  entry:
  87 // CHECK-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z7foo_ovli.ifunc(i32 noundef 1)
  88 // CHECK-NEXT:    [[CALL1:%.*]] = call noundef i32 @_Z7foo_ovlv.ifunc()
  89 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
  90 // CHECK-NEXT:    ret i32 [[ADD]]
  91 // CHECK-LABEL: @_Z11run_foo_tmlv(
  92 // CHECK-NEXT:  entry:
  93 // CHECK-NEXT:    [[MC1:%.*]] = alloca [[STRUCT_MYCLASS:%.*]], align 1
  94 // CHECK-NEXT:    [[MC2:%.*]] = alloca [[STRUCT_MYCLASS_0:%.*]], align 1
  95 // CHECK-NEXT:    [[MC3:%.*]] = alloca [[STRUCT_MYCLASS_1:%.*]], align 1
  96 // CHECK-NEXT:    [[MC4:%.*]] = alloca [[STRUCT_MYCLASS_2:%.*]], align 1
  97 // CHECK-NEXT:    [[CALL:%.*]] = call noundef i32 @_ZN7MyClassIssE7foo_tmlEv.ifunc(ptr noundef nonnull align 1 dereferenceable(1) [[MC1]])
  98 // CHECK-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN7MyClassIisE7foo_tmlEv.ifunc(ptr noundef nonnull align 1 dereferenceable(1) [[MC2]])
  99 // CHECK-NEXT:    [[CALL2:%.*]] = call noundef i32 @_ZN7MyClassIfsE7foo_tmlEv(ptr noundef nonnull align 1 dereferenceable(1) [[MC3]])
 100 // CHECK-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZN7MyClassIdfE7foo_tmlEv(ptr noundef nonnull align 1 dereferenceable(1) [[MC4]])
 101 // CHECK-NEXT:    ret void
 102 // CHECK-LABEL: @_ZN7MyClassIssE7foo_tmlEv.resolver(
 103 // CHECK-NEXT:  resolver_entry:
 104 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 105 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 106 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 36310271995674624
 107 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36310271995674624
 108 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 109 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 110 // CHECK:       resolver_return:
 111 // CHECK-NEXT:    ret ptr @_ZN7MyClassIssE7foo_tmlEv._MssbsMsme-f64f64
 112 // CHECK:       resolver_else:
 113 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 114 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 16777216
 115 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 16777216
 116 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 117 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 118 // CHECK:       resolver_return1:
 119 // CHECK-NEXT:    ret ptr @_ZN7MyClassIssE7foo_tmlEv._Mfrintts
 120 // CHECK:       resolver_else2:
 121 // CHECK-NEXT:    ret ptr @_ZN7MyClassIssE7foo_tmlEv
 122 // CHECK-LABEL: @_ZN7MyClassIisE7foo_tmlEv.resolver(
 123 // CHECK-NEXT:  resolver_entry:
 124 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 125 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 126 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 36310271995674624
 127 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36310271995674624
 128 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 129 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 130 // CHECK:       resolver_return:
 131 // CHECK-NEXT:    ret ptr @_ZN7MyClassIisE7foo_tmlEv._MssbsMsme-f64f64
 132 // CHECK:       resolver_else:
 133 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 134 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 16777216
 135 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 16777216
 136 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 137 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 138 // CHECK:       resolver_return1:
 139 // CHECK-NEXT:    ret ptr @_ZN7MyClassIisE7foo_tmlEv._Mfrintts
 140 // CHECK:       resolver_else2:
 141 // CHECK-NEXT:    ret ptr @_ZN7MyClassIisE7foo_tmlEv
 142 // CHECK-LABEL: @_ZN7MyClassIfsE7foo_tmlEv(
 143 // CHECK-NEXT:  entry:
 144 // CHECK-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 145 // CHECK-NEXT:    store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
 146 // CHECK-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 147 // CHECK-NEXT:    ret i32 3
 148 // CHECK-LABEL: @_ZN7MyClassIdfE7foo_tmlEv(
 149 // CHECK-NEXT:  entry:
 150 // CHECK-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 151 // CHECK-NEXT:    store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
 152 // CHECK-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 153 // CHECK-NEXT:    ret i32 4
 154 // CHECK-LABEL: @_ZN7MyClassIssE7foo_tmlEv._Mfrintts(
 155 // CHECK-NEXT:  entry:
 156 // CHECK-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 157 // CHECK-NEXT:    store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
 158 // CHECK-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 159 // CHECK-NEXT:    ret i32 1
 160 // CHECK-LABEL: @_ZN7MyClassIssE7foo_tmlEv._MssbsMsme-f64f64(
 161 // CHECK-NEXT:  entry:
 162 // CHECK-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 163 // CHECK-NEXT:    store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
 164 // CHECK-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 165 // CHECK-NEXT:    ret i32 1
 166 // CHECK-LABEL: @_ZN7MyClassIssE7foo_tmlEv(
 167 // CHECK-NEXT:  entry:
 168 // CHECK-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 169 // CHECK-NEXT:    store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
 170 // CHECK-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 171 // CHECK-NEXT:    ret i32 1
 172 // CHECK-LABEL: @_ZN7MyClassIisE7foo_tmlEv._Mfrintts(
 173 // CHECK-NEXT:  entry:
 174 // CHECK-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 175 // CHECK-NEXT:    store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
 176 // CHECK-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 177 // CHECK-NEXT:    ret i32 2
 178 // CHECK-LABEL: @_ZN7MyClassIisE7foo_tmlEv._MssbsMsme-f64f64(
 179 // CHECK-NEXT:  entry:
 180 // CHECK-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 181 // CHECK-NEXT:    store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
 182 // CHECK-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 183 // CHECK-NEXT:    ret i32 2
 184 // CHECK-LABEL: @_ZN7MyClassIisE7foo_tmlEv(
 185 // CHECK-NEXT:  entry:
 186 // CHECK-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 187 // CHECK-NEXT:    store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8
 188 // CHECK-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 189 // CHECK-NEXT:    ret i32 2
 190
 191 // CHECK: attributes #0 = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
 192 // CHECK: attributes #1 = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
 193 // CHECK: attributes #2 = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ls64" }
 194 // CHECK: attributes #3 = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint" }
 195 // CHECK: attributes #4 = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sme,+sme-f64f64" }