llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

   1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file provides AArch64 specific target descriptions.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
  14 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
  15
  16 #include "llvm/Support/DataTypes.h"
  17
  18 #include <memory>
  19
  20 namespace llvm {
  21 class formatted_raw_ostream;
  22 class MCAsmBackend;
  23 class MCCodeEmitter;
  24 class MCContext;
  25 class MCInst;
  26 class MCInstrInfo;
  27 class MCInstPrinter;
  28 class MCRegisterInfo;
  29 class MCObjectTargetWriter;
  30 class MCStreamer;
  31 class MCSubtargetInfo;
  32 class MCTargetOptions;
  33 class MCTargetStreamer;
  34 class Target;
  35
  36 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
  37                                           MCContext &Ctx);
  38 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
  39                                         const MCSubtargetInfo &STI,
  40                                         const MCRegisterInfo &MRI,
  41                                         const MCTargetOptions &Options);
  42 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
  43                                         const MCSubtargetInfo &STI,
  44                                         const MCRegisterInfo &MRI,
  45                                         const MCTargetOptions &Options);
  46
  47 std::unique_ptr<MCObjectTargetWriter>
  48 createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
  49
  50 std::unique_ptr<MCObjectTargetWriter>
  51 createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype,
  52                               bool IsILP32);
  53
  54 std::unique_ptr<MCObjectTargetWriter> createAArch64WinCOFFObjectWriter();
  55
  56 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
  57                                                  formatted_raw_ostream &OS,
  58                                                  MCInstPrinter *InstPrint,
  59                                                  bool isVerboseAsm);
  60
  61 namespace AArch64_MC {
  62 void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
  63 bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);
  64 bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
  65 }
  66
  67 } // End llvm namespace
  68
  69 // Defines symbolic names for AArch64 registers.  This defines a mapping from
  70 // register name to register number.
  71 //
  72 #define GET_REGINFO_ENUM
  73 #include "AArch64GenRegisterInfo.inc"
  74
  75 // Defines symbolic names for the AArch64 instructions.
  76 //
  77 #define GET_INSTRINFO_ENUM
  78 #define GET_INSTRINFO_MC_HELPER_DECLS
  79 #include "AArch64GenInstrInfo.inc"
  80
  81 #define GET_SUBTARGETINFO_ENUM
  82 #include "AArch64GenSubtargetInfo.inc"
  83
  84 #endif