| blob | 350315e9aefdae3ccf719d6dbc630f111d753b80 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2 ; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefix=XTENSA %s
5 define i32 @rotl_32(i32 %x, i32 %y) nounwind {
6 ; XTENSA-LABEL: rotl_32:
7 ; XTENSA: ssl a3
8 ; XTENSA-NEXT: sll a8, a2
9 ; XTENSA-NEXT: movi a9, 32
10 ; XTENSA-NEXT: sub a9, a9, a3
11 ; XTENSA-NEXT: ssr a9
12 ; XTENSA-NEXT: srl a9, a2
13 ; XTENSA-NEXT: or a2, a8, a9
14 ; XTENSA-NEXT: ret
15 %z = sub i32 32, %y
16 %b = shl i32 %x, %y
17 %c = lshr i32 %x, %z
18 %d = or i32 %b, %c
19 ret i32 %d
20 }
22 define i32 @rotr_32(i32 %x, i32 %y) nounwind {
23 ; XTENSA-LABEL: rotr_32:
24 ; XTENSA: ssr a3
25 ; XTENSA-NEXT: srl a8, a2
26 ; XTENSA-NEXT: movi a9, 32
27 ; XTENSA-NEXT: sub a9, a9, a3
28 ; XTENSA-NEXT: ssl a9
29 ; XTENSA-NEXT: sll a9, a2
30 ; XTENSA-NEXT: or a2, a8, a9
31 ; XTENSA-NEXT: ret
32 %z = sub i32 32, %y
33 %b = lshr i32 %x, %y
34 %c = shl i32 %x, %z
35 %d = or i32 %b, %c
36 ret i32 %d
37 }
39 define i64 @rotl_64(i64 %x, i64 %y) nounwind {
40 ; XTENSA-LABEL: rotl_64:
41 ; XTENSA: movi a8, 64
42 ; XTENSA-NEXT: sub a8, a8, a4
43 ; XTENSA-NEXT: ssr a8
44 ; XTENSA-NEXT: src a11, a3, a2
45 ; XTENSA-NEXT: movi a9, 32
46 ; XTENSA-NEXT: sub a9, a9, a4
47 ; XTENSA-NEXT: ssr a9
48 ; XTENSA-NEXT: srl a7, a3
49 ; XTENSA-NEXT: movi a10, 0
50 ; XTENSA-NEXT: blt a9, a10, .LBB2_2
51 ; XTENSA-NEXT: # %bb.1:
52 ; XTENSA-NEXT: or a11, a7, a7
53 ; XTENSA-NEXT: .LBB2_2:
54 ; XTENSA-NEXT: ssl a4
55 ; XTENSA-NEXT: sll a7, a2
56 ; XTENSA-NEXT: addi a5, a4, -32
57 ; XTENSA-NEXT: blt a5, a10, .LBB2_4
58 ; XTENSA-NEXT: # %bb.3:
59 ; XTENSA-NEXT: or a7, a10, a10
60 ; XTENSA-NEXT: .LBB2_4:
61 ; XTENSA-NEXT: ssl a4
62 ; XTENSA-NEXT: src a6, a3, a2
63 ; XTENSA-NEXT: ssl a5
64 ; XTENSA-NEXT: sll a4, a2
65 ; XTENSA-NEXT: blt a5, a10, .LBB2_6
66 ; XTENSA-NEXT: # %bb.5:
67 ; XTENSA-NEXT: or a6, a4, a4
68 ; XTENSA-NEXT: .LBB2_6:
69 ; XTENSA-NEXT: or a2, a7, a11
70 ; XTENSA-NEXT: ssr a8
71 ; XTENSA-NEXT: srl a8, a3
72 ; XTENSA-NEXT: blt a9, a10, .LBB2_8
73 ; XTENSA-NEXT: # %bb.7:
74 ; XTENSA-NEXT: or a8, a10, a10
75 ; XTENSA-NEXT: .LBB2_8:
76 ; XTENSA-NEXT: or a3, a6, a8
77 ; XTENSA-NEXT: ret
78 %z = sub i64 64, %y
79 %b = shl i64 %x, %y
80 %c = lshr i64 %x, %z
81 %d = or i64 %b, %c
82 ret i64 %d
83 }
85 define i64 @rotr_64(i64 %x, i64 %y) nounwind {
86 ; XTENSA-LABEL: rotr_64:
87 ; XTENSA: ssr a4
88 ; XTENSA-NEXT: src a10, a3, a2
89 ; XTENSA-NEXT: addi a8, a4, -32
90 ; XTENSA-NEXT: ssr a8
91 ; XTENSA-NEXT: srl a11, a3
92 ; XTENSA-NEXT: movi a9, 0
93 ; XTENSA-NEXT: blt a8, a9, .LBB3_2
94 ; XTENSA-NEXT: # %bb.1:
95 ; XTENSA-NEXT: or a10, a11, a11
96 ; XTENSA-NEXT: .LBB3_2:
97 ; XTENSA-NEXT: movi a11, 32
98 ; XTENSA-NEXT: sub a7, a11, a4
99 ; XTENSA-NEXT: movi a11, 64
100 ; XTENSA-NEXT: sub a11, a11, a4
101 ; XTENSA-NEXT: ssl a11
102 ; XTENSA-NEXT: sll a6, a2
103 ; XTENSA-NEXT: blt a7, a9, .LBB3_4
104 ; XTENSA-NEXT: # %bb.3:
105 ; XTENSA-NEXT: or a6, a9, a9
106 ; XTENSA-NEXT: .LBB3_4:
107 ; XTENSA-NEXT: ssl a11
108 ; XTENSA-NEXT: src a11, a3, a2
109 ; XTENSA-NEXT: ssl a7
110 ; XTENSA-NEXT: sll a5, a2
111 ; XTENSA-NEXT: blt a7, a9, .LBB3_6
112 ; XTENSA-NEXT: # %bb.5:
113 ; XTENSA-NEXT: or a11, a5, a5
114 ; XTENSA-NEXT: .LBB3_6:
115 ; XTENSA-NEXT: or a2, a10, a6
116 ; XTENSA-NEXT: ssr a4
117 ; XTENSA-NEXT: srl a10, a3
118 ; XTENSA-NEXT: blt a8, a9, .LBB3_8
119 ; XTENSA-NEXT: # %bb.7:
120 ; XTENSA-NEXT: or a10, a9, a9
121 ; XTENSA-NEXT: .LBB3_8:
122 ; XTENSA-NEXT: or a3, a10, a11
123 ; XTENSA-NEXT: ret
124 %z = sub i64 64, %y
125 %b = lshr i64 %x, %y
126 %c = shl i64 %x, %z
127 %d = or i64 %b, %c
128 ret i64 %d
129 }
131 define i32 @rotl_32_mask(i32 %x, i32 %y) nounwind {
132 ; XTENSA-LABEL: rotl_32_mask:
133 ; XTENSA: ssl a3
134 ; XTENSA-NEXT: sll a8, a2
135 ; XTENSA-NEXT: neg a9, a3
136 ; XTENSA-NEXT: movi a10, 31
137 ; XTENSA-NEXT: and a9, a9, a10
138 ; XTENSA-NEXT: ssr a9
139 ; XTENSA-NEXT: srl a9, a2
140 ; XTENSA-NEXT: or a2, a8, a9
141 ; XTENSA-NEXT: ret
142 %z = sub i32 0, %y
143 %and = and i32 %z, 31
144 %b = shl i32 %x, %y
145 %c = lshr i32 %x, %and
146 %d = or i32 %b, %c
147 ret i32 %d
148 }
150 define i32 @rotl_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {
151 ; XTENSA-LABEL: rotl_32_mask_and_63_and_31:
152 ; XTENSA: movi a8, 63
153 ; XTENSA-NEXT: and a8, a3, a8
154 ; XTENSA-NEXT: ssl a8
155 ; XTENSA-NEXT: sll a8, a2
156 ; XTENSA-NEXT: neg a9, a3
157 ; XTENSA-NEXT: movi a10, 31
158 ; XTENSA-NEXT: and a9, a9, a10
159 ; XTENSA-NEXT: ssr a9
160 ; XTENSA-NEXT: srl a9, a2
161 ; XTENSA-NEXT: or a2, a8, a9
162 ; XTENSA-NEXT: ret
163 %a = and i32 %y, 63
164 %b = shl i32 %x, %a
165 %c = sub i32 0, %y
166 %d = and i32 %c, 31
167 %e = lshr i32 %x, %d
168 %f = or i32 %b, %e
169 ret i32 %f
170 }
172 define i32 @rotr_32_mask(i32 %x, i32 %y) nounwind {
173 ; XTENSA-LABEL: rotr_32_mask:
174 ; XTENSA: ssr a3
175 ; XTENSA-NEXT: srl a8, a2
176 ; XTENSA-NEXT: neg a9, a3
177 ; XTENSA-NEXT: movi a10, 31
178 ; XTENSA-NEXT: and a9, a9, a10
179 ; XTENSA-NEXT: ssl a9
180 ; XTENSA-NEXT: sll a9, a2
181 ; XTENSA-NEXT: or a2, a8, a9
182 ; XTENSA-NEXT: ret
183 %z = sub i32 0, %y
184 %and = and i32 %z, 31
185 %b = lshr i32 %x, %y
186 %c = shl i32 %x, %and
187 %d = or i32 %b, %c
188 ret i32 %d
189 }
191 define i32 @rotr_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {
192 ; XTENSA-LABEL: rotr_32_mask_and_63_and_31:
193 ; XTENSA: movi a8, 63
194 ; XTENSA-NEXT: and a8, a3, a8
195 ; XTENSA-NEXT: ssr a8
196 ; XTENSA-NEXT: srl a8, a2
197 ; XTENSA-NEXT: neg a9, a3
198 ; XTENSA-NEXT: movi a10, 31
199 ; XTENSA-NEXT: and a9, a9, a10
200 ; XTENSA-NEXT: ssl a9
201 ; XTENSA-NEXT: sll a9, a2
202 ; XTENSA-NEXT: or a2, a8, a9
203 ; XTENSA-NEXT: ret
204 %a = and i32 %y, 63
205 %b = lshr i32 %x, %a
206 %c = sub i32 0, %y
207 %d = and i32 %c, 31
208 %e = shl i32 %x, %d
209 %f = or i32 %b, %e
210 ret i32 %f
211 }
213 define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
214 ; XTENSA-LABEL: rotl_64_mask:
215 ; XTENSA: ssl a4
216 ; XTENSA-NEXT: src a10, a3, a2
217 ; XTENSA-NEXT: addi a8, a4, -32
218 ; XTENSA-NEXT: ssl a8
219 ; XTENSA-NEXT: sll a11, a2
220 ; XTENSA-NEXT: movi a9, 0
221 ; XTENSA-NEXT: blt a8, a9, .LBB8_2
222 ; XTENSA-NEXT: # %bb.1:
223 ; XTENSA-NEXT: or a10, a11, a11
224 ; XTENSA-NEXT: .LBB8_2:
225 ; XTENSA-NEXT: neg a11, a4
226 ; XTENSA-NEXT: movi a7, 63
227 ; XTENSA-NEXT: and a7, a11, a7
228 ; XTENSA-NEXT: ssr a7
229 ; XTENSA-NEXT: srl a11, a3
230 ; XTENSA-NEXT: addi a6, a7, -32
231 ; XTENSA-NEXT: blt a6, a9, .LBB8_4
232 ; XTENSA-NEXT: # %bb.3:
233 ; XTENSA-NEXT: or a11, a9, a9
234 ; XTENSA-NEXT: .LBB8_4:
235 ; XTENSA-NEXT: ssr a7
236 ; XTENSA-NEXT: src a7, a3, a2
237 ; XTENSA-NEXT: ssr a6
238 ; XTENSA-NEXT: srl a5, a3
239 ; XTENSA-NEXT: blt a6, a9, .LBB8_6
240 ; XTENSA-NEXT: # %bb.5:
241 ; XTENSA-NEXT: or a7, a5, a5
242 ; XTENSA-NEXT: .LBB8_6:
243 ; XTENSA-NEXT: or a3, a10, a11
244 ; XTENSA-NEXT: ssl a4
245 ; XTENSA-NEXT: sll a10, a2
246 ; XTENSA-NEXT: blt a8, a9, .LBB8_8
247 ; XTENSA-NEXT: # %bb.7:
248 ; XTENSA-NEXT: or a10, a9, a9
249 ; XTENSA-NEXT: .LBB8_8:
250 ; XTENSA-NEXT: or a2, a10, a7
251 ; XTENSA-NEXT: ret
252 %z = sub i64 0, %y
253 %and = and i64 %z, 63
254 %b = shl i64 %x, %y
255 %c = lshr i64 %x, %and
256 %d = or i64 %b, %c
257 ret i64 %d
258 }
260 define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
261 ; XTENSA-LABEL: rotl_64_mask_and_127_and_63:
262 ; XTENSA: movi a8, 127
263 ; XTENSA-NEXT: and a8, a4, a8
264 ; XTENSA-NEXT: ssl a8
265 ; XTENSA-NEXT: src a11, a3, a2
266 ; XTENSA-NEXT: addi a9, a8, -32
267 ; XTENSA-NEXT: ssl a9
268 ; XTENSA-NEXT: sll a7, a2
269 ; XTENSA-NEXT: movi a10, 0
270 ; XTENSA-NEXT: blt a9, a10, .LBB9_2
271 ; XTENSA-NEXT: # %bb.1:
272 ; XTENSA-NEXT: or a11, a7, a7
273 ; XTENSA-NEXT: .LBB9_2:
274 ; XTENSA-NEXT: neg a7, a4
275 ; XTENSA-NEXT: movi a6, 63
276 ; XTENSA-NEXT: and a6, a7, a6
277 ; XTENSA-NEXT: ssr a6
278 ; XTENSA-NEXT: srl a7, a3
279 ; XTENSA-NEXT: addi a5, a6, -32
280 ; XTENSA-NEXT: blt a5, a10, .LBB9_4
281 ; XTENSA-NEXT: # %bb.3:
282 ; XTENSA-NEXT: or a7, a10, a10
283 ; XTENSA-NEXT: .LBB9_4:
284 ; XTENSA-NEXT: ssr a6
285 ; XTENSA-NEXT: src a6, a3, a2
286 ; XTENSA-NEXT: ssr a5
287 ; XTENSA-NEXT: srl a4, a3
288 ; XTENSA-NEXT: blt a5, a10, .LBB9_6
289 ; XTENSA-NEXT: # %bb.5:
290 ; XTENSA-NEXT: or a6, a4, a4
291 ; XTENSA-NEXT: .LBB9_6:
292 ; XTENSA-NEXT: or a3, a11, a7
293 ; XTENSA-NEXT: ssl a8
294 ; XTENSA-NEXT: sll a8, a2
295 ; XTENSA-NEXT: blt a9, a10, .LBB9_8
296 ; XTENSA-NEXT: # %bb.7:
297 ; XTENSA-NEXT: or a8, a10, a10
298 ; XTENSA-NEXT: .LBB9_8:
299 ; XTENSA-NEXT: or a2, a8, a6
300 ; XTENSA-NEXT: ret
301 %a = and i64 %y, 127
302 %b = shl i64 %x, %a
303 %c = sub i64 0, %y
304 %d = and i64 %c, 63
305 %e = lshr i64 %x, %d
306 %f = or i64 %b, %e
307 ret i64 %f
308 }
310 define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind {
311 ; XTENSA-LABEL: rotr_64_mask:
312 ; XTENSA: ssr a4
313 ; XTENSA-NEXT: src a10, a3, a2
314 ; XTENSA-NEXT: addi a8, a4, -32
315 ; XTENSA-NEXT: ssr a8
316 ; XTENSA-NEXT: srl a11, a3
317 ; XTENSA-NEXT: movi a9, 0
318 ; XTENSA-NEXT: blt a8, a9, .LBB10_2
319 ; XTENSA-NEXT: # %bb.1:
320 ; XTENSA-NEXT: or a10, a11, a11
321 ; XTENSA-NEXT: .LBB10_2:
322 ; XTENSA-NEXT: neg a11, a4
323 ; XTENSA-NEXT: movi a7, 63
324 ; XTENSA-NEXT: and a7, a11, a7
325 ; XTENSA-NEXT: ssl a7
326 ; XTENSA-NEXT: sll a11, a2
327 ; XTENSA-NEXT: addi a6, a7, -32
328 ; XTENSA-NEXT: blt a6, a9, .LBB10_4
329 ; XTENSA-NEXT: # %bb.3:
330 ; XTENSA-NEXT: or a11, a9, a9
331 ; XTENSA-NEXT: .LBB10_4:
332 ; XTENSA-NEXT: ssl a7
333 ; XTENSA-NEXT: src a7, a3, a2
334 ; XTENSA-NEXT: ssl a6
335 ; XTENSA-NEXT: sll a5, a2
336 ; XTENSA-NEXT: blt a6, a9, .LBB10_6
337 ; XTENSA-NEXT: # %bb.5:
338 ; XTENSA-NEXT: or a7, a5, a5
339 ; XTENSA-NEXT: .LBB10_6:
340 ; XTENSA-NEXT: or a2, a10, a11
341 ; XTENSA-NEXT: ssr a4
342 ; XTENSA-NEXT: srl a10, a3
343 ; XTENSA-NEXT: blt a8, a9, .LBB10_8
344 ; XTENSA-NEXT: # %bb.7:
345 ; XTENSA-NEXT: or a10, a9, a9
346 ; XTENSA-NEXT: .LBB10_8:
347 ; XTENSA-NEXT: or a3, a10, a7
348 ; XTENSA-NEXT: ret
349 %z = sub i64 0, %y
350 %and = and i64 %z, 63
351 %b = lshr i64 %x, %y
352 %c = shl i64 %x, %and
353 %d = or i64 %b, %c
354 ret i64 %d
355 }
357 define i64 @rotr_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
358 ; XTENSA-LABEL: rotr_64_mask_and_127_and_63:
359 ; XTENSA: movi a8, 127
360 ; XTENSA-NEXT: and a8, a4, a8
361 ; XTENSA-NEXT: ssr a8
362 ; XTENSA-NEXT: src a11, a3, a2
363 ; XTENSA-NEXT: addi a9, a8, -32
364 ; XTENSA-NEXT: ssr a9
365 ; XTENSA-NEXT: srl a7, a3
366 ; XTENSA-NEXT: movi a10, 0
367 ; XTENSA-NEXT: blt a9, a10, .LBB11_2
368 ; XTENSA-NEXT: # %bb.1:
369 ; XTENSA-NEXT: or a11, a7, a7
370 ; XTENSA-NEXT: .LBB11_2:
371 ; XTENSA-NEXT: neg a7, a4
372 ; XTENSA-NEXT: movi a6, 63
373 ; XTENSA-NEXT: and a6, a7, a6
374 ; XTENSA-NEXT: ssl a6
375 ; XTENSA-NEXT: sll a7, a2
376 ; XTENSA-NEXT: addi a5, a6, -32
377 ; XTENSA-NEXT: blt a5, a10, .LBB11_4
378 ; XTENSA-NEXT: # %bb.3:
379 ; XTENSA-NEXT: or a7, a10, a10
380 ; XTENSA-NEXT: .LBB11_4:
381 ; XTENSA-NEXT: ssl a6
382 ; XTENSA-NEXT: src a6, a3, a2
383 ; XTENSA-NEXT: ssl a5
384 ; XTENSA-NEXT: sll a4, a2
385 ; XTENSA-NEXT: blt a5, a10, .LBB11_6
386 ; XTENSA-NEXT: # %bb.5:
387 ; XTENSA-NEXT: or a6, a4, a4
388 ; XTENSA-NEXT: .LBB11_6:
389 ; XTENSA-NEXT: or a2, a11, a7
390 ; XTENSA-NEXT: ssr a8
391 ; XTENSA-NEXT: srl a8, a3
392 ; XTENSA-NEXT: blt a9, a10, .LBB11_8
393 ; XTENSA-NEXT: # %bb.7:
394 ; XTENSA-NEXT: or a8, a10, a10
395 ; XTENSA-NEXT: .LBB11_8:
396 ; XTENSA-NEXT: or a3, a8, a6
397 ; XTENSA-NEXT: ret
398 %a = and i64 %y, 127
399 %b = lshr i64 %x, %a
400 %c = sub i64 0, %y
401 %d = and i64 %c, 63
402 %e = shl i64 %x, %d
403 %f = or i64 %b, %e
404 ret i64 %f
405 }
407 define signext i32 @rotl_32_mask_shared(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {
408 ; XTENSA-LABEL: rotl_32_mask_shared:
409 ; XTENSA: movi a8, 31
410 ; XTENSA-NEXT: and a9, a4, a8
411 ; XTENSA-NEXT: ssl a9
412 ; XTENSA-NEXT: sll a10, a2
413 ; XTENSA-NEXT: neg a11, a4
414 ; XTENSA-NEXT: and a8, a11, a8
415 ; XTENSA-NEXT: ssr a8
416 ; XTENSA-NEXT: srl a8, a2
417 ; XTENSA-NEXT: or a8, a10, a8
418 ; XTENSA-NEXT: ssl a9
419 ; XTENSA-NEXT: sll a9, a3
420 ; XTENSA-NEXT: add a2, a8, a9
421 ; XTENSA-NEXT: ret
422 %maskedamt = and i32 %amt, 31
423 %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %maskedamt)
424 %2 = shl i32 %b, %maskedamt
425 %3 = add i32 %1, %2
426 ret i32 %3
427 }
428 declare i32 @llvm.fshl.i32(i32, i32, i32)
430 define signext i32 @rotr_32_mask_shared(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {
431 ; XTENSA-LABEL: rotr_32_mask_shared:
432 ; XTENSA: movi a8, 31
433 ; XTENSA-NEXT: and a9, a4, a8
434 ; XTENSA-NEXT: ssr a9
435 ; XTENSA-NEXT: srl a10, a2
436 ; XTENSA-NEXT: neg a11, a4
437 ; XTENSA-NEXT: and a8, a11, a8
438 ; XTENSA-NEXT: ssl a8
439 ; XTENSA-NEXT: sll a8, a2
440 ; XTENSA-NEXT: or a8, a10, a8
441 ; XTENSA-NEXT: ssl a9
442 ; XTENSA-NEXT: sll a9, a3
443 ; XTENSA-NEXT: add a2, a8, a9
444 ; XTENSA-NEXT: ret
445 %maskedamt = and i32 %amt, 31
446 %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %maskedamt)
447 %2 = shl i32 %b, %maskedamt
448 %3 = add i32 %1, %2
449 ret i32 %3
450 }
451 declare i32 @llvm.fshr.i32(i32, i32, i32)
453 define signext i32 @rotl_32_mask_multiple(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {
454 ; XTENSA-LABEL: rotl_32_mask_multiple:
455 ; XTENSA: movi a8, 31
456 ; XTENSA-NEXT: and a9, a4, a8
457 ; XTENSA-NEXT: ssl a9
458 ; XTENSA-NEXT: sll a10, a3
459 ; XTENSA-NEXT: neg a11, a4
460 ; XTENSA-NEXT: and a8, a11, a8
461 ; XTENSA-NEXT: ssr a8
462 ; XTENSA-NEXT: srl a11, a3
463 ; XTENSA-NEXT: or a10, a10, a11
464 ; XTENSA-NEXT: ssl a9
465 ; XTENSA-NEXT: sll a9, a2
466 ; XTENSA-NEXT: ssr a8
467 ; XTENSA-NEXT: srl a8, a2
468 ; XTENSA-NEXT: or a8, a9, a8
469 ; XTENSA-NEXT: add a2, a8, a10
470 ; XTENSA-NEXT: ret
471 %maskedamt = and i32 %amt, 31
472 %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %maskedamt)
473 %2 = tail call i32 @llvm.fshl.i32(i32 %b, i32 %b, i32 %maskedamt)
474 %3 = add i32 %1, %2
475 ret i32 %3
476 }
478 define signext i32 @rotr_32_mask_multiple(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {
479 ; XTENSA-LABEL: rotr_32_mask_multiple:
480 ; XTENSA: movi a8, 31
481 ; XTENSA-NEXT: and a9, a4, a8
482 ; XTENSA-NEXT: ssr a9
483 ; XTENSA-NEXT: srl a10, a3
484 ; XTENSA-NEXT: neg a11, a4
485 ; XTENSA-NEXT: and a8, a11, a8
486 ; XTENSA-NEXT: ssl a8
487 ; XTENSA-NEXT: sll a11, a3
488 ; XTENSA-NEXT: or a10, a10, a11
489 ; XTENSA-NEXT: ssr a9
490 ; XTENSA-NEXT: srl a9, a2
491 ; XTENSA-NEXT: ssl a8
492 ; XTENSA-NEXT: sll a8, a2
493 ; XTENSA-NEXT: or a8, a9, a8
494 ; XTENSA-NEXT: add a2, a8, a10
495 ; XTENSA-NEXT: ret
496 %maskedamt = and i32 %amt, 31
497 %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %maskedamt)
498 %2 = tail call i32 @llvm.fshr.i32(i32 %b, i32 %b, i32 %maskedamt)
499 %3 = add i32 %1, %2
500 ret i32 %3
501 }