llvm/test/MC/AArch64/SME/fmopa-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-f64f64 2>&1 < %s| FileCheck %s
   2
   3 // ------------------------------------------------------------------------- //
   4 // Invalid tile
   5 //
   6 // expected: .s => za0-za3, .d => za0-za7
   7
   8 // non-widening
   9
  10 fmopa za4.s, p0/m, p0/m, z0.s, z0.s
  11 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  12 // CHECK-NEXT: fmopa za4.s, p0/m, p0/m, z0.s, z0.s
  13 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  14
  15 fmopa za8.d, p0/m, p0/m, z0.d, z0.d
  16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  17 // CHECK-NEXT: fmopa za8.d, p0/m, p0/m, z0.d, z0.d
  18 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  19
  20 // widening
  21
  22 fmopa za4.s, p0/m, p0/m, z0.h, z0.h
  23 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  24 // CHECK-NEXT: fmopa za4.s, p0/m, p0/m, z0.h, z0.h
  25 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  26
  27 // ------------------------------------------------------------------------- //
  28 // Invalid predicate (expected: p0-p7)
  29
  30 // non-widening
  31
  32 fmopa za0.s, p8/m, p0/m, z0.s, z0.s
  33 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  34 // CHECK-NEXT: fmopa za0.s, p8/m, p0/m, z0.s, z0.s
  35 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  36
  37 fmopa za0.s, p0/m, p8/m, z0.s, z0.s
  38 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  39 // CHECK-NEXT: fmopa za0.s, p0/m, p8/m, z0.s, z0.s
  40 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  41
  42 fmopa za0.d, p8/m, p0/m, z0.d, z0.d
  43 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  44 // CHECK-NEXT: fmopa za0.d, p8/m, p0/m, z0.d, z0.d
  45 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  46
  47 fmopa za0.d, p0/m, p8/m, z0.d, z0.d
  48 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  49 // CHECK-NEXT: fmopa za0.d, p0/m, p8/m, z0.d, z0.d
  50 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  51
  52 // widening
  53
  54 fmopa za0.s, p8/m, p0/m, z0.h, z0.h
  55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  56 // CHECK-NEXT: fmopa za0.s, p8/m, p0/m, z0.h, z0.h
  57 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  58
  59 fmopa za0.s, p0/m, p8/m, z0.h, z0.h
  60 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  61 // CHECK-NEXT: fmopa za0.s, p0/m, p8/m, z0.h, z0.h
  62 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  63
  64 // ------------------------------------------------------------------------- //
  65 // Invalid predicate qualifier (expected: /m)
  66
  67 // non-widening
  68
  69 fmopa za0.s, p0/z, p0/m, z0.s, z0.s
  70 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  71 // CHECK-NEXT: fmopa za0.s, p0/z, p0/m, z0.s, z0.s
  72 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  73
  74 fmopa za0.s, p0/m, p0/z, z0.s, z0.s
  75 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  76 // CHECK-NEXT: fmopa za0.s, p0/m, p0/z, z0.s, z0.s
  77 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  78
  79 fmopa za0.d, p0/z, p0/m, z0.d, z0.d
  80 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  81 // CHECK-NEXT: fmopa za0.d, p0/z, p0/m, z0.d, z0.d
  82 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  83
  84 fmopa za0.d, p0/m, p0/z, z0.d, z0.d
  85 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  86 // CHECK-NEXT: fmopa za0.d, p0/m, p0/z, z0.d, z0.d
  87 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  88
  89 // widening
  90
  91 fmopa za0.s, p0/z, p0/m, z0.h, z0.h
  92 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  93 // CHECK-NEXT: fmopa za0.s, p0/z, p0/m, z0.h, z0.h
  94 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  95
  96 fmopa za0.s, p0/m, p0/z, z0.h, z0.h
  97 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  98 // CHECK-NEXT: fmopa za0.s, p0/m, p0/z, z0.h, z0.h
  99 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 100
 101 // ------------------------------------------------------------------------- //
 102 // Invalid ZPR type suffix
 103 //
 104 // expected: .s => .s (non-widening), .h (widening), .d => .d
 105
 106 // non-widening
 107
 108 fmopa za0.s, p0/m, p0/m, z0.b, z0.s
 109 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 110 // CHECK-NEXT: fmopa za0.s, p0/m, p0/m, z0.b, z0.s
 111 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 112
 113 fmopa za0.s, p0/m, p0/m, z0.s, z0.h
 114 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 115 // CHECK-NEXT: fmopa za0.s, p0/m, p0/m, z0.s, z0.h
 116 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 117
 118 fmopa za0.d, p0/m, p0/m, z0.b, z0.d
 119 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 120 // CHECK-NEXT: fmopa za0.d, p0/m, p0/m, z0.b, z0.d
 121 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 122
 123 fmopa za0.d, p0/m, p0/m, z0.d, z0.h
 124 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 125 // CHECK-NEXT: fmopa za0.d, p0/m, p0/m, z0.d, z0.h
 126 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 127
 128 // widening
 129
 130 fmopa za0.s, p0/m, p0/m, z0.b, z0.h
 131 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 132 // CHECK-NEXT: fmopa za0.s, p0/m, p0/m, z0.b, z0.h
 133 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 134
 135 fmopa za0.s, p0/m, p0/m, z0.h, z0.d
 136 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 137 // CHECK-NEXT: fmopa za0.s, p0/m, p0/m, z0.h, z0.d
 138 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: