llvm/test/MC/AArch64/SME/zero-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Registers list not in ascending order
   5
   6 zero    {za1.s, za0.s}
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: warning: tile list not in ascending order
   8 // CHECK-NEXT: zero {za1.s, za0.s}
   9 // CHECK-NEXT:              ^
  10
  11 zero    {za0.d, za1.d, za4.d, za3.d}
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: warning: tile list not in ascending order
  13 // CHECK-NEXT: zero {za0.d, za1.d, za4.d, za3.d}
  14 // CHECK-NEXT:                            ^
  15
  16 // --------------------------------------------------------------------------//
  17 // Duplicate tile
  18
  19 zero    {za0.s, za0.s}
  20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: warning: duplicate tile in list
  21 // CHECK-NEXT: zero {za0.s, za0.s}
  22 // CHECK-NEXT:              ^
  23
  24 zero    {za0.d, za1.d, za2.d, za2.d, za3.d}
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: warning: duplicate tile in list
  26 // CHECK-NEXT: zero {za0.d, za1.d, za2.d, za2.d, za3.d}
  27 // CHECK-NEXT:                            ^
  28
  29 // --------------------------------------------------------------------------//
  30 // Mismatched register size suffix
  31
  32 zero    {za0.b, za5.d}
  33 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
  34 // CHECK-NEXT: zero {za0.b, za5.d}
  35 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  36
  37 // --------------------------------------------------------------------------//
  38 // Missing '}'
  39
  40 zero    {za
  41 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: '}' expected
  42 // CHECK-NEXT: zero {za
  43 // CHECK-NEXT:         ^
  44 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  45
  46 // --------------------------------------------------------------------------//
  47 // Invalid matrix tile
  48
  49 zero    {za0.b, za1.b}
  50 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  51 // CHECK-NEXT: zero    {za0.b, za1.b}
  52 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  53
  54 zero    {za2.h}
  55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  56 // CHECK-NEXT: zero    {za2.h}
  57 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  58
  59 zero    {za0.s, za1.s, za2.s, za3.s, za4.s}
  60 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  61 // CHECK-NEXT: zero    {za0.s, za1.s, za2.s, za3.s, za4.s}
  62 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  63
  64 zero    {za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d, za8.d}
  65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  66 // CHECK-NEXT: zero {za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d, za8.d}
  67 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  68
  69 zero    {za0h.b}
  70 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  71 // CHECK-NEXT: zero    {za0h.b}
  72 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  73
  74 zero    {za0.s, za1h.s}
  75 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  76 // CHECK-NEXT: zero    {za0.s, za1h.s}
  77 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  78
  79 zero    {za15.q}
  80 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  81 // CHECK-NEXT: zero {za15.q}
  82 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: