llvm/test/MC/AArch64/SME2/bfclamp-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sve-b16b16 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 bfclamp {z0.h-z2.h}, z0.h, z0.h
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: bfclamp {z0.h-z2.h}, z0.h, z0.h
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 bfclamp {z23.h-z24.h}, z13.h, z8.h
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  13 // CHECK-NEXT: bfclamp {z23.h-z24.h}, z13.h, z8.h
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 bfclamp {z21.h-z24.h}, z10.h, z21.h
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
  18 // CHECK-NEXT: bfclamp {z21.h-z24.h}, z10.h, z21.h
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21
  22 // --------------------------------------------------------------------------//
  23 // Invalid Register Suffix
  24
  25 bfclamp {z0.s-z1.s}, z0.h, z4.h
  26 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  27 // CHECK-NEXT: bfclamp {z0.s-z1.s}, z0.h, z4.h
  28 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  29
  30 bfclamp {z0.h-z3.h}, z5.d, z6.d
  31 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  32 // CHECK-NEXT: bfclamp {z0.h-z3.h}, z5.d, z6.d
  33 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: