[Frontend] Remove unused includes (NFC) (#116927)
[llvm-project.git] / llvm / test / MC / AArch64 / SME2 / bfmul-diagnostics.s
blobc28cc5cd426dda5078eaa530743eb664cafd88b9
1 // RUN: not llvm-mc -triple=aarch64 -mattr=+sme2,+sve-bfscale 2>&1 < %s| FileCheck %s
3 // Multiple and single, 2 regs
5 bfmul {z0.s-z1.s}, {z0.h-z1.h}, z0.h
6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8 bfmul {z1.h-z2.h}, {z0.h-z1.h}, z0.h
9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
11 bfmul {z0.h-z2.h}, {z0.h-z1.h}, z0.h
12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
14 bfmul {z0.h-z1.h}, {z0.s-z1.s}, z0.h
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
17 bfmul {z0.h-z1.h}, {z1.h-z2.h}, z0.h
18 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
20 bfmul {z0.h-z1.h}, {z0.h-z2.h}, z0.h
21 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
23 bfmul {z0.h-z1.h}, {z0.h-z1.h}, z0.s
24 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
26 bfmul {z0.h-z1.h}, {z0.h-z1.h}, z16.h
27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
29 // Multiple and single, 4 regs
31 bfmul {z0.s-z3.s}, {z0.h-z3.h}, z0.h
32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
34 bfmul {z1.h-z4.h}, {z0.h-z3.h}, z0.h
35 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
37 bfmul {z0.h-z4.h}, {z0.h-z3.h}, z0.h
38 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
40 bfmul {z0.h-z3.h}, {z0.s-z3.s}, z0.h
41 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
43 bfmul {z0.h-z3.h}, {z1.h-z4.h}, z0.h
44 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
46 bfmul {z0.h-z3.h}, {z0.h-z4.h}, z0.h
47 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
49 bfmul {z0.h-z3.h}, {z0.h-z3.h}, z0.s
50 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
52 bfmul {z0.h-z3.h}, {z0.h-z3.h}, z16.h
53 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
55 // Multiple, 2 regs
57 bfmul {z0.s-z1.s}, {z0.h-z1.h}, {z0.h-z1.h}
58 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
60 bfmul {z1.h-z2.h}, {z0.h-z1.h}, {z0.h-z1.h}
61 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
63 bfmul {z0.h-z2.h}, {z0.h-z1.h}, {z0.h-z1.h}
64 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
66 bfmul {z0.h-z1.h}, {z0.s-z1.s}, {z0.h-z1.h}
67 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
69 bfmul {z0.h-z1.h}, {z1.h-z2.h}, {z0.h-z1.h}
70 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
72 bfmul {z0.h-z1.h}, {z0.h-z2.h}, {z0.h-z1.h}
73 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
75 bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.s-z1.s}
76 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
78 bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z1.h-z2.h}
79 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
81 bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z2.h}
82 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
84 // Multiple, 4 regs
86 bfmul {z0.s-z3.s}, {z0.h-z3.h}, {z0.h-z3.h}
87 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
89 bfmul {z1.h-z4.h}, {z0.h-z3.h}, {z0.h-z3.h}
90 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
92 bfmul {z0.h-z4.h}, {z0.h-z3.h}, {z0.h-z3.h}
93 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
95 bfmul {z0.h-z3.h}, {z0.s-z3.s}, {z0.h-z3.h}
96 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
98 bfmul {z0.h-z3.h}, {z1.h-z4.h}, {z0.h-z3.h}
99 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
101 bfmul {z0.h-z3.h}, {z0.h-z4.h}, {z0.h-z3.h}
102 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
104 bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.s-z3.s}
105 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
107 bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z1.h-z4.h}
108 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
110 bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z4.h}
111 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors