llvm/test/MC/AArch64/SME2/fclamp-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 fclamp {z0.h-z2.h}, z0.h, z0.h
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: fclamp {z0.h-z2.h}, z0.h, z0.h
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 fclamp {z0.d-z4.d}, z5.d, z6.d
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  13 // CHECK-NEXT: fclamp {z0.d-z4.d}, z5.d, z6.d
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 fclamp {z23.s-z24.s}, z13.s, z8.s
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
  18 // CHECK-NEXT: fclamp {z23.s-z24.s}, z13.s, z8.s
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 fclamp {z21.h-z24.h}, z10.h, z21.h
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type
  23 // CHECK-NEXT: fclamp {z21.h-z24.h}, z10.h, z21.h
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26
  27 // --------------------------------------------------------------------------//
  28 // Invalid Register Suffix
  29
  30 fclamp {z0.h-z1.h}, z0.h, z4.s
  31 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  32 // CHECK-NEXT: fclamp {z0.h-z1.h}, z0.h, z4.s
  33 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  34
  35 fclamp {z0.s-z3.s}, z5.d, z6.d
  36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  37 // CHECK-NEXT: fclamp {z0.s-z3.s}, z5.d, z6.d
  38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: