llvm/test/MC/AArch64/SME2/scvtf-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 scvtf {z0.s-z3.s}, {z0.s-z4.s}
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
   8 // CHECK-NEXT: scvtf {z0.s-z3.s}, {z0.s-z4.s}
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 scvtf {z1.s-z2.s}, {z0.s-z1.s}
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  13 // CHECK-NEXT: scvtf {z1.s-z2.s}, {z0.s-z1.s}
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 scvtf {z0.s-z3.s}, {z1.s-z5.s}
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  18 // CHECK-NEXT: scvtf {z0.s-z3.s}, {z1.s-z5.s}
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 // --------------------------------------------------------------------------//
  22 // Invalid Register Suffix
  23
  24 scvtf {z0.s-z3.s}, {z1.h-z3.h}
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  26 // CHECK-NEXT: scvtf {z0.s-z3.s}, {z1.h-z3.h}
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: