llvm/test/MC/AArch64/SME2p2/bftmopa-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-b16b16 2>&1 < %s| FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid ZA register (range)
   5
   6 bftmopa  za2.h, {z30.h-z31.h}, z31.h, z31[3]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: bftmopa  za2.h, {z30.h-z31.h}, z31.h, z31[3]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 bftmopa  za4.s, {z30.h-z31.h}, z31.h, z31[3]
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  13 // CHECK-NEXT: bftmopa  za4.s, {z30.h-z31.h}, z31.h, z31[3]
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 // --------------------------------------------------------------------------//
  17 // Invalid ZA register (type-suffix)
  18
  19 bftmopa  za3.d, {z28.h-z29.h}, z31.h, z20[3]
  20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
  21 // CHECK-NEXT: bftmopa  za3.d, {z28.h-z29.h}, z31.h, z20[3]
  22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  23
  24 // --------------------------------------------------------------------------//
  25 // Invalid vector list operand
  26
  27 bftmopa  za0.h, {z28.h-z31.h}, z31.h, z31[3]
  28 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  29 // CHECK-NEXT: bftmopa  za0.h, {z28.h-z31.h}, z31.h, z31[3]
  30 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  31
  32 bftmopa  za0.h, {z29.h-z30.h}, z31.h, z31[3]
  33 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  34 // CHECK-NEXT: bftmopa  za0.h, {z29.h-z30.h}, z31.h, z31[3]
  35 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  36
  37 bftmopa  za0.s, {z28.h-z31.h}, z31.h, z31[3]
  38 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  39 // CHECK-NEXT: bftmopa  za0.s, {z28.h-z31.h}, z31.h, z31[3]
  40 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  41
  42 bftmopa  za3.s, {z29.h-z30.h}, z31.h, z31[3]
  43 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  44 // CHECK-NEXT: bftmopa  za3.s, {z29.h-z30.h}, z31.h, z31[3]
  45 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  46
  47 // --------------------------------------------------------------------------//
  48 // Invalid ZK register
  49
  50 bftmopa  za0.h, {z28.h-z29.h}, z31.h, z19[3]
  51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
  52 // CHECK-NEXT: bftmopa  za0.h, {z28.h-z29.h}, z31.h, z19[3]
  53 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  54
  55 bftmopa  za0.h, {z28.h-z29.h}, z31.h, z24[3]
  56 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
  57 // CHECK-NEXT: bftmopa  za0.h, {z28.h-z29.h}, z31.h, z24[3]
  58 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  59
  60 bftmopa  za3.s, {z28.h-z29.h}, z31.h, z19[3]
  61 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
  62 // CHECK-NEXT: bftmopa  za3.s, {z28.h-z29.h}, z31.h, z19[3]
  63 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  64
  65 bftmopa  za3.s, {z28.h-z29.h}, z31.h, z27[3]
  66 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
  67 // CHECK-NEXT: bftmopa  za3.s, {z28.h-z29.h}, z31.h, z27[3]
  68 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  69
  70 bftmopa  za0.h, {z28.h-z29.h}, z31.h, z21.h[3]
  71 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
  72 // CHECK-NEXT: bftmopa  za0.h, {z28.h-z29.h}, z31.h, z21.h[3]
  73 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  74
  75 bftmopa  za0.s, {z28.h-z29.h}, z31.h, z30.h[3]
  76 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
  77 // CHECK-NEXT: bftmopa  za0.s, {z28.h-z29.h}, z31.h, z30.h[3]
  78 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  79
  80 // --------------------------------------------------------------------------//
  81 // Invalid immediate
  82
  83 bftmopa  za0.h, {z28.h-z29.h}, z31.h, z20[4]
  84 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
  85 // CHECK-NEXT: bftmopa  za0.h, {z28.h-z29.h}, z31.h, z20[4]
  86 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  87
  88 bftmopa  za3.s, {z28.h-z29.h}, z31.h, z20[4]
  89 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
  90 // CHECK-NEXT: bftmopa  za3.s, {z28.h-z29.h}, z31.h, z20[4]
  91 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  92
  93 // --------------------------------------------------------------------------//
  94 // Invalid ZPR type suffix
  95
  96 bftmopa  za0.h, {z28.h-z29.h}, z31.s, z20[3]
  97 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  98 // CHECK-NEXT: bftmopa  za0.h, {z28.h-z29.h}, z31.s, z20[3]
  99 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 100
 101 bftmopa  za0.h, {z28.b-z29.b}, z31.b, z20[3]
 102 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 103 // CHECK-NEXT: bftmopa  za0.h, {z28.b-z29.b}, z31.b, z20[3]
 104 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 105
 106 bftmopa  za3.s, {z28.h-z29.h}, z31.s, z20[3]
 107 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 108 // CHECK-NEXT: bftmopa  za3.s, {z28.h-z29.h}, z31.s, z20[3]
 109 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 110
 111 bftmopa  za3.s, {z28.s-z29.s}, z31.s, z20[3]
 112 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 113 // CHECK-NEXT: bftmopa  za3.s, {z28.s-z29.s}, z31.s, z20[3]
 114 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: