llvm/test/MC/AArch64/SME2p2/fmul-diagnostics.s

   1
   2 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 2>&1 < %s| FileCheck %s
   3
   4 // Multiple and single, 2 regs
   5
   6 fmul    {z0.b-z1.b}, {z0.h-z1.h}, z0.h
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8
   9 fmul    {z1.s-z2.s}, {z0.s-z1.s}, z0.s
  10 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  11
  12 fmul    {z0.d-z2.d}, {z0.d-z1.d}, z0.d
  13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  14
  15 fmul    {z0.h-z1.h}, {z0.b-z1.b}, z0.h
  16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  17
  18 fmul    {z0.s-z1.s}, {z1.s-z2.s}, z0.s
  19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  20
  21 fmul    {z0.d-z1.d}, {z0.d-z2.d}, z0.d
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  23
  24 fmul    {z0.h-z1.h}, {z0.h-z1.h}, z0.b
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
  26
  27 fmul    {z0.s-z1.s}, {z0.s-z1.s}, z16.s
  28 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z15.s
  29
  30 // Multiple and single, 4 regs
  31
  32 fmul    {z0.b-z3.b}, {z0.h-z3.h}, z0.h
  33 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  34
  35 fmul    {z1.s-z3.s}, {z0.h-z3.h}, z0.s
  36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  37
  38 fmul    {z0.d-z4.d}, {z0.d-z3.d}, z0.d
  39 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  40
  41 fmul    {z0.h-z3.h}, {z0.b-z3.b}, z0.h
  42 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  43
  44 fmul    {z0.s-z3.s}, {z1.s-z3.s}, z0.s
  45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  46
  47 fmul    {z0.d-z3.d}, {z0.d-z4.d}, z0.d
  48 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  49
  50 fmul    {z0.h-z3.h}, {z0.h-z3.h}, z0.b
  51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
  52
  53 fmul    {z0.s-z3.s}, {z0.s-z3.s}, z16.s
  54 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z15.s
  55
  56 // Multiple, 2 regs
  57
  58 fmul    {z0.b-z1.b}, {z0.h-z1.h}, {z0.h-z1.h}
  59 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  60
  61 fmul    {z1.s-z2.s}, {z0.s-z1.s}, {z0.s-z1.s}
  62 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  63
  64 fmul    {z0.d-z2.d}, {z0.d-z1.d}, {z0.d-z1.d}
  65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  66
  67 fmul    {z0.h-z1.h}, {z0.b-z1.b}, {z0.h-z1.h}
  68 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  69
  70 fmul    {z0.s-z1.s}, {z1.s-z2.s}, {z0.s-z1.s}
  71 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  72
  73 fmul    {z0.d-z1.d}, {z0.d-z2.d}, {z0.d-z1.d}
  74 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  75
  76 fmul    {z0.h-z1.h}, {z0.h-z1.h}, {z0.b-z1.b}
  77 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  78
  79 fmul    {z0.s-z1.s}, {z0.s-z1.s}, {z1.s-z2.s}
  80 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  81
  82 fmul    {z0.d-z1.d}, {z0.d-z1.d}, {z0.d-z2.d}
  83 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  84
  85 // Multiple, 4 regs
  86
  87 fmul    {z0.b-z3.b}, {z0.h-z3.h}, {z0.h-z3.h}
  88 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  89
  90 fmul    {z1.s-z3.s}, {z0.s-z3.s}, {z0.s-z3.s}
  91 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  92
  93 fmul    {z0.d-z4.d}, {z0.d-z3.d}, {z0.d-z3.d}
  94 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  95
  96 fmul    {z0.h-z3.h}, {z0.b-z3.b}, {z0.h-z3.h}
  97 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  98
  99 fmul    {z0.s-z3.s}, {z1.s-z3.s}, {z0.s-z3.s}
 100 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 101
 102 fmul    {z0.d-z3.d}, {z0.d-z4.d}, {z0.d-z3.d}
 103 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
 104
 105 fmul    {z0.h-z3.h}, {z0.h-z3.h}, {z0.b-z3.b}
 106 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 107
 108 fmul    {z0.s-z3.s}, {z0.s-z3.s}, {z1.s-z3.s}
 109 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 110
 111 fmul    {z0.d-z3.d}, {z0.d-z3.d}, {z0.d-z4.d}
 112 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors