[Frontend] Remove unused includes (NFC) (#116927)
[llvm-project.git] / llvm / test / MC / AArch64 / SME2p2 / fmul.s
blobec6f523867cef512c9ce9a58cfa6bf586f7f4c9c
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
6 // RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
8 // RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9 // Disassemble encoding and check the re-encoding (-show-encoding) matches.
10 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
11 // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
12 // RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \
13 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
15 // Multiple and single, 2 regs
17 // 16-bit elements
19 fmul {z0.h-z1.h}, {z0.h-z1.h}, z0.h // 11000001-01100000-11101000-00000000
20 // CHECK-INST: fmul { z0.h, z1.h }, { z0.h, z1.h }, z0.h
21 // CHECK-ENCODING: [0x00,0xe8,0x60,0xc1]
22 // CHECK-ERROR: instruction requires: sme2p2
23 // CHECK-UNKNOWN: c160e800 <unknown>
25 fmul {z20.h-z21.h}, {z10.h-z11.h}, z10.h // 11000001-01110100-11101001-01010100
26 // CHECK-INST: fmul { z20.h, z21.h }, { z10.h, z11.h }, z10.h
27 // CHECK-ENCODING: [0x54,0xe9,0x74,0xc1]
28 // CHECK-ERROR: instruction requires: sme2p2
29 // CHECK-UNKNOWN: c174e954 <unknown>
31 fmul {z30.h-z31.h}, {z30.h-z31.h}, z15.h // 11000001-01111110-11101011-11011110
32 // CHECK-INST: fmul { z30.h, z31.h }, { z30.h, z31.h }, z15.h
33 // CHECK-ENCODING: [0xde,0xeb,0x7e,0xc1]
34 // CHECK-ERROR: instruction requires: sme2p2
35 // CHECK-UNKNOWN: c17eebde <unknown>
37 // 32-bit elements
39 fmul {z0.s-z1.s}, {z0.s-z1.s}, z0.s // 11000001-10100000-11101000-00000000
40 // CHECK-INST: fmul { z0.s, z1.s }, { z0.s, z1.s }, z0.s
41 // CHECK-ENCODING: [0x00,0xe8,0xa0,0xc1]
42 // CHECK-ERROR: instruction requires: sme2p2
43 // CHECK-UNKNOWN: c1a0e800 <unknown>
45 fmul {z20.s-z21.s}, {z10.s-z11.s}, z10.s // 11000001-10110100-11101001-01010100
46 // CHECK-INST: fmul { z20.s, z21.s }, { z10.s, z11.s }, z10.s
47 // CHECK-ENCODING: [0x54,0xe9,0xb4,0xc1]
48 // CHECK-ERROR: instruction requires: sme2p2
49 // CHECK-UNKNOWN: c1b4e954 <unknown>
51 fmul {z30.s-z31.s}, {z30.s-z31.s}, z15.s // 11000001-10111110-11101011-11011110
52 // CHECK-INST: fmul { z30.s, z31.s }, { z30.s, z31.s }, z15.s
53 // CHECK-ENCODING: [0xde,0xeb,0xbe,0xc1]
54 // CHECK-ERROR: instruction requires: sme2p2
55 // CHECK-UNKNOWN: c1beebde <unknown>
57 // 64-bit elements
59 fmul {z0.d-z1.d}, {z0.d-z1.d}, z0.d // 11000001-11100000-11101000-00000000
60 // CHECK-INST: fmul { z0.d, z1.d }, { z0.d, z1.d }, z0.d
61 // CHECK-ENCODING: [0x00,0xe8,0xe0,0xc1]
62 // CHECK-ERROR: instruction requires: sme2p2
63 // CHECK-UNKNOWN: c1e0e800 <unknown>
65 fmul {z20.d-z21.d}, {z10.d-z11.d}, z10.d // 11000001-11110100-11101001-01010100
66 // CHECK-INST: fmul { z20.d, z21.d }, { z10.d, z11.d }, z10.d
67 // CHECK-ENCODING: [0x54,0xe9,0xf4,0xc1]
68 // CHECK-ERROR: instruction requires: sme2p2
69 // CHECK-UNKNOWN: c1f4e954 <unknown>
71 fmul {z30.d-z31.d}, {z30.d-z31.d}, z15.d // 11000001-11111110-11101011-11011110
72 // CHECK-INST: fmul { z30.d, z31.d }, { z30.d, z31.d }, z15.d
73 // CHECK-ENCODING: [0xde,0xeb,0xfe,0xc1]
74 // CHECK-ERROR: instruction requires: sme2p2
75 // CHECK-UNKNOWN: c1feebde <unknown>
77 // Multiple and single, 4 regs
79 // 16-bit elements
81 fmul {z0.h-z3.h}, {z0.h-z3.h}, z0.h // 11000001-01100001-11101000-00000000
82 // CHECK-INST: fmul { z0.h - z3.h }, { z0.h - z3.h }, z0.h
83 // CHECK-ENCODING: [0x00,0xe8,0x61,0xc1]
84 // CHECK-ERROR: instruction requires: sme2p2
85 // CHECK-UNKNOWN: c161e800 <unknown>
87 fmul {z20.h-z23.h}, {z8.h-z11.h}, z10.h // 11000001-01110101-11101001-00010100
88 // CHECK-INST: fmul { z20.h - z23.h }, { z8.h - z11.h }, z10.h
89 // CHECK-ENCODING: [0x14,0xe9,0x75,0xc1]
90 // CHECK-ERROR: instruction requires: sme2p2
91 // CHECK-UNKNOWN: c175e914 <unknown>
93 fmul {z28.h-z31.h}, {z28.h-z31.h}, z15.h // 11000001-01111111-11101011-10011100
94 // CHECK-INST: fmul { z28.h - z31.h }, { z28.h - z31.h }, z15.h
95 // CHECK-ENCODING: [0x9c,0xeb,0x7f,0xc1]
96 // CHECK-ERROR: instruction requires: sme2p2
97 // CHECK-UNKNOWN: c17feb9c <unknown>
99 // 32-bit elements
101 fmul {z0.s-z3.s}, {z0.s-z3.s}, z0.s // 11000001-10100001-11101000-00000000
102 // CHECK-INST: fmul { z0.s - z3.s }, { z0.s - z3.s }, z0.s
103 // CHECK-ENCODING: [0x00,0xe8,0xa1,0xc1]
104 // CHECK-ERROR: instruction requires: sme2p2
105 // CHECK-UNKNOWN: c1a1e800 <unknown>
107 fmul {z20.s-z23.s}, {z8.s-z11.s}, z10.s // 11000001-10110101-11101001-00010100
108 // CHECK-INST: fmul { z20.s - z23.s }, { z8.s - z11.s }, z10.s
109 // CHECK-ENCODING: [0x14,0xe9,0xb5,0xc1]
110 // CHECK-ERROR: instruction requires: sme2p2
111 // CHECK-UNKNOWN: c1b5e914 <unknown>
113 fmul {z28.s-z31.s}, {z28.s-z31.s}, z15.s // 11000001-10111111-11101011-10011100
114 // CHECK-INST: fmul { z28.s - z31.s }, { z28.s - z31.s }, z15.s
115 // CHECK-ENCODING: [0x9c,0xeb,0xbf,0xc1]
116 // CHECK-ERROR: instruction requires: sme2p2
117 // CHECK-UNKNOWN: c1bfeb9c <unknown>
119 // 64-bit elements
121 fmul {z0.d-z3.d}, {z0.d-z3.d}, z0.d // 11000001-11100001-11101000-00000000
122 // CHECK-INST: fmul { z0.d - z3.d }, { z0.d - z3.d }, z0.d
123 // CHECK-ENCODING: [0x00,0xe8,0xe1,0xc1]
124 // CHECK-ERROR: instruction requires: sme2p2
125 // CHECK-UNKNOWN: c1e1e800 <unknown>
127 fmul {z20.d-z23.d}, {z8.d-z11.d}, z10.d // 11000001-11110101-11101001-00010100
128 // CHECK-INST: fmul { z20.d - z23.d }, { z8.d - z11.d }, z10.d
129 // CHECK-ENCODING: [0x14,0xe9,0xf5,0xc1]
130 // CHECK-ERROR: instruction requires: sme2p2
131 // CHECK-UNKNOWN: c1f5e914 <unknown>
133 fmul {z28.d-z31.d}, {z28.d-z31.d}, z15.d // 11000001-11111111-11101011-10011100
134 // CHECK-INST: fmul { z28.d - z31.d }, { z28.d - z31.d }, z15.d
135 // CHECK-ENCODING: [0x9c,0xeb,0xff,0xc1]
136 // CHECK-ERROR: instruction requires: sme2p2
137 // CHECK-UNKNOWN: c1ffeb9c <unknown>
139 // Multiple, 2 regs
141 // 16-bit elements
143 fmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} // 11000001-01100000-11100100-00000000
144 // CHECK-INST: fmul { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
145 // CHECK-ENCODING: [0x00,0xe4,0x60,0xc1]
146 // CHECK-ERROR: instruction requires: sme2p2
147 // CHECK-UNKNOWN: c160e400 <unknown>
149 fmul {z20.h-z21.h}, {z10.h-z11.h}, {z20.h-z21.h} // 11000001-01110100-11100101-01010100
150 // CHECK-INST: fmul { z20.h, z21.h }, { z10.h, z11.h }, { z20.h, z21.h }
151 // CHECK-ENCODING: [0x54,0xe5,0x74,0xc1]
152 // CHECK-ERROR: instruction requires: sme2p2
153 // CHECK-UNKNOWN: c174e554 <unknown>
155 fmul {z30.h-z31.h}, {z30.h-z31.h}, {z30.h-z31.h} // 11000001-01111110-11100111-11011110
156 // CHECK-INST: fmul { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
157 // CHECK-ENCODING: [0xde,0xe7,0x7e,0xc1]
158 // CHECK-ERROR: instruction requires: sme2p2
159 // CHECK-UNKNOWN: c17ee7de <unknown>
161 // 32-bit elememnts
163 fmul {z0.s-z1.s}, {z0.s-z1.s}, {z0.s-z1.s} // 11000001-10100000-11100100-00000000
164 // CHECK-INST: fmul { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
165 // CHECK-ENCODING: [0x00,0xe4,0xa0,0xc1]
166 // CHECK-ERROR: instruction requires: sme2p2
167 // CHECK-UNKNOWN: c1a0e400 <unknown>
169 fmul {z20.s-z21.s}, {z10.s-z11.s}, {z20.s-z21.s} // 11000001-10110100-11100101-01010100
170 // CHECK-INST: fmul { z20.s, z21.s }, { z10.s, z11.s }, { z20.s, z21.s }
171 // CHECK-ENCODING: [0x54,0xe5,0xb4,0xc1]
172 // CHECK-ERROR: instruction requires: sme2p2
173 // CHECK-UNKNOWN: c1b4e554 <unknown>
175 fmul {z30.s-z31.s}, {z30.s-z31.s}, {z30.s-z31.s} // 11000001-10111110-11100111-11011110
176 // CHECK-INST: fmul { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }
177 // CHECK-ENCODING: [0xde,0xe7,0xbe,0xc1]
178 // CHECK-ERROR: instruction requires: sme2p2
179 // CHECK-UNKNOWN: c1bee7de <unknown>
181 // 64-bit elements
183 fmul {z0.d-z1.d}, {z0.d-z1.d}, {z0.d-z1.d} // 11000001-11100000-11100100-00000000
184 // CHECK-INST: fmul { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }
185 // CHECK-ENCODING: [0x00,0xe4,0xe0,0xc1]
186 // CHECK-ERROR: instruction requires: sme2p2
187 // CHECK-UNKNOWN: c1e0e400 <unknown>
189 fmul {z20.d-z21.d}, {z10.d-z11.d}, {z20.d-z21.d} // 11000001-11110100-11100101-01010100
190 // CHECK-INST: fmul { z20.d, z21.d }, { z10.d, z11.d }, { z20.d, z21.d }
191 // CHECK-ENCODING: [0x54,0xe5,0xf4,0xc1]
192 // CHECK-ERROR: instruction requires: sme2p2
193 // CHECK-UNKNOWN: c1f4e554 <unknown>
195 fmul {z30.d-z31.d}, {z30.d-z31.d}, {z30.d-z31.d} // 11000001-11111110-11100111-11011110
196 // CHECK-INST: fmul { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }
197 // CHECK-ENCODING: [0xde,0xe7,0xfe,0xc1]
198 // CHECK-ERROR: instruction requires: sme2p2
199 // CHECK-UNKNOWN: c1fee7de <unknown>
201 // Multiple, 4 regs
203 // 16-bit elements
205 fmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h} // 11000001-01100001-11100100-00000000
206 // CHECK-INST: fmul { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
207 // CHECK-ENCODING: [0x00,0xe4,0x61,0xc1]
208 // CHECK-ERROR: instruction requires: sme2p2
209 // CHECK-UNKNOWN: c161e400 <unknown>
211 fmul {z20.h-z23.h}, {z8.h-z11.h}, {z20.h-z23.h} // 11000001-01110101-11100101-00010100
212 // CHECK-INST: fmul { z20.h - z23.h }, { z8.h - z11.h }, { z20.h - z23.h }
213 // CHECK-ENCODING: [0x14,0xe5,0x75,0xc1]
214 // CHECK-ERROR: instruction requires: sme2p2
215 // CHECK-UNKNOWN: c175e514 <unknown>
217 fmul {z28.h-z31.h}, {z28.h-z31.h}, {z28.h-z31.h} // 11000001-01111101-11100111-10011100
218 // CHECK-INST: fmul { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
219 // CHECK-ENCODING: [0x9c,0xe7,0x7d,0xc1]
220 // CHECK-ERROR: instruction requires: sme2p2
221 // CHECK-UNKNOWN: c17de79c <unknown>
223 // 32-bit elements
225 fmul {z0.s-z3.s}, {z0.s-z3.s}, {z0.s-z3.s} // 11000001-10100001-11100100-00000000
226 // CHECK-INST: fmul { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }
227 // CHECK-ENCODING: [0x00,0xe4,0xa1,0xc1]
228 // CHECK-ERROR: instruction requires: sme2p2
229 // CHECK-UNKNOWN: c1a1e400 <unknown>
231 fmul {z20.s-z23.s}, {z8.s-z11.s}, {z20.s-z23.s} // 11000001-10110101-11100101-00010100
232 // CHECK-INST: fmul { z20.s - z23.s }, { z8.s - z11.s }, { z20.s - z23.s }
233 // CHECK-ENCODING: [0x14,0xe5,0xb5,0xc1]
234 // CHECK-ERROR: instruction requires: sme2p2
235 // CHECK-UNKNOWN: c1b5e514 <unknown>
237 fmul {z28.s-z31.s}, {z28.s-z31.s}, {z28.s-z31.s} // 11000001-10111101-11100111-10011100
238 // CHECK-INST: fmul { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }
239 // CHECK-ENCODING: [0x9c,0xe7,0xbd,0xc1]
240 // CHECK-ERROR: instruction requires: sme2p2
241 // CHECK-UNKNOWN: c1bde79c <unknown>
243 // 64-bit elements
245 fmul {z0.d-z3.d}, {z0.d-z3.d}, {z0.d-z3.d} // 11000001-11100001-11100100-00000000
246 // CHECK-INST: fmul { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }
247 // CHECK-ENCODING: [0x00,0xe4,0xe1,0xc1]
248 // CHECK-ERROR: instruction requires: sme2p2
249 // CHECK-UNKNOWN: c1e1e400 <unknown>
251 fmul {z20.d-z23.d}, {z8.d-z11.d}, {z20.d-z23.d} // 11000001-11110101-11100101-00010100
252 // CHECK-INST: fmul { z20.d - z23.d }, { z8.d - z11.d }, { z20.d - z23.d }
253 // CHECK-ENCODING: [0x14,0xe5,0xf5,0xc1]
254 // CHECK-ERROR: instruction requires: sme2p2
255 // CHECK-UNKNOWN: c1f5e514 <unknown>
257 fmul {z28.d-z31.d}, {z28.d-z31.d}, {z28.d-z31.d} // 11000001-11111101-11100111-10011100
258 // CHECK-INST: fmul { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }
259 // CHECK-ENCODING: [0x9c,0xe7,0xfd,0xc1]
260 // CHECK-ERROR: instruction requires: sme2p2
261 // CHECK-UNKNOWN: c1fde79c <unknown>