1 // RUN
: not llvm-mc
-triple
=aarch64
-show-encoding
-mattr
=+sme2p2
,+sme-i16i64
2>&1 < %s| FileCheck
%s
3 // ------------------------------------------------------------------------- //
6 // expected
: .s => za0-za3, .d => za0-za7
8 sumop4s za4.s
, z0.
b, z16.
b
9 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: invalid operand for instruction
10 // CHECK-NEXT
: sumop4s za4.s
, z0.
b, z16.
b
11 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
13 sumop4s za8.d
, z0.h
, z16.h
14 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: invalid operand for instruction
15 // CHECK-NEXT
: sumop4s za8.d
, z0.h
, z16.h
16 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
18 // ------------------------------------------------------------------------- //
19 // Invalid first operand
(expected z0.
.z15)
21 sumop4s za0.d
, z16.h
, z16.h
22 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: Invalid restricted vector register
, expected even register in z0.h.
.z14.h
23 // CHECK-NEXT
: sumop4s za0.d
, z16.h
, z16.h
24 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
26 sumop4s za0.d
, {z16.h-z17.h
}, z16.h
27 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: Invalid vector list
, expected list with
2 consecutive SVE vectors in the range z0-z14
, where the first vector is
a multiple of
2 and with matching element types
28 // CHECK-NEXT
: sumop4s za0.d
, {z16.h-z17.h
}, z16.h
29 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
31 // ------------------------------------------------------------------------- //
32 // Invalid second operand
(expected z16.
.z31)
34 sumop4s za0.d
, z14.h
, z14.h
35 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: Invalid restricted vector register
, expected even register in z16.h.
.z30.h
36 // CHECK-NEXT
: sumop4s za0.d
, z14.h
, z14.h
37 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
39 sumop4s za0.d
, z14.h
, {z14.h-z15.h
}
40 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: Invalid vector list
, expected list with
2 consecutive SVE vectors in the range z16-z30
, where the first vector is
a multiple of
2 and with matching element types
41 // CHECK-NEXT
: sumop4s za0.d
, z14.h
, {z14.h-z15.h
}
42 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
45 // ------------------------------------------------------------------------- //
46 // Invalid ZPR type suffix
48 // expected
: .s => .b, .d => .h
50 sumop4s za3.s
, z0.h
, z16.
b
51 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: Invalid restricted vector register
, expected even register in z0.b.
.z14.b
52 // CHECK-NEXT
: sumop4s za3.s
, z0.h
, z16.
b
53 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
55 sumop4s za3.s
, z0.
b, z16.s
56 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: Invalid restricted vector register
, expected even register in z16.b.
.z30.b
57 // CHECK-NEXT
: sumop4s za3.s
, z0.
b, z16.s
58 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
60 sumop4s za3.d
, z0.h
, z16.
b
61 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: Invalid restricted vector register
, expected even register in z16.h.
.z30.h
62 // CHECK-NEXT
: sumop4s za3.d
, z0.h
, z16.
b
63 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
65 sumop4s za3.d
, z0.s
, z16.h
66 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: Invalid restricted vector register
, expected even register in z0.h.
.z14.h
67 // CHECK-NEXT
: sumop4s za3.d
, z0.s
, z16.h
68 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}: