llvm/test/MC/AArch64/SVE/bfmlal-diagnostics.s

   1 // RUN: not llvm-mc -o - -triple=aarch64 -mattr=+sve,bf16  2>&1 %s | FileCheck %s
   2
   3 bfmlalb z0.S, z1.H, z7.H[8]
   4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
   5 // CHECK-NEXT: bfmlalb z0.S, z1.H, z7.H[8]
   6 // CHECK-NEXT: ^
   7
   8 bfmlalb z0.S, z1.H, z8.H[7]
   9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  10 // CHECK-NEXT: bfmlalb z0.S, z1.H, z8.H[7]
  11 // CHECK-NEXT: ^
  12
  13 bfmlalt z0.S, z1.H, z7.H[8]
  14 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
  15 // CHECK-NEXT: bfmlalt z0.S, z1.H, z7.H[8]
  16 // CHECK-NEXT: ^
  17
  18 bfmlalt z0.S, z1.H, z8.H[7]
  19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  20 // CHECK-NEXT: bfmlalt z0.S, z1.H, z8.H[7]
  21 // CHECK-NEXT: ^
  22
  23 bfmlalt z0.S, z1.H, z7.2h[2]
  24 // CHECK: error: invalid vector kind qualifier
  25 // CHECK-NEXT: bfmlalt z0.S, z1.H, z7.2h[2]
  26 // CHECK-NEXT:                     ^
  27
  28 bfmlalt z0.S, z1.H, z2.s[2]
  29 // CHECK: error: Invalid restricted vector register, expected z0.h..z7.h
  30 // CHECK-NEXT: bfmlalt z0.S, z1.H, z2.s[2]
  31 // CHECK-NEXT:                     ^
  32
  33 bfmlalt z0.S, z1.s, z2.h[2]
  34 // CHECK: error: invalid element width
  35 // CHECK-NEXT: bfmlalt z0.S, z1.s, z2.h[2]
  36 // CHECK-NEXT:               ^
  37
  38 movprfx z0.s, p0/m, z7.s
  39 bfmlalt z0.s, z1.h, z2.h
  40 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx
  41 // CHECK-NEXT: bfmlalt z0.s, z1.h, z2.h
  42 // CHECK-NEXT: ^