llvm/test/MC/AArch64/SVE/matrix-multiply-fp-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+f32mm,+f64mm  2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // FMMLA (SVE)
   5
   6 // Mis-matched element size
   7
   8 fmmla z0.d, z1.s, z2.s
   9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  10 fmmla z0.s, z1.d, z2.s
  11 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  12 fmmla z0.s, z1.s, z2.d
  13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  14
  15
  16 // --------------------------------------------------------------------------//
  17 // LD1RO (SVE, scalar plus immediate)
  18
  19 // Immediate too high (>224)
  20 ld1rob { z0.b }, p1/z, [x2, #256]
  21 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
  22 ld1roh { z0.h }, p1/z, [x2, #256]
  23 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
  24 ld1row { z0.s }, p1/z, [x2, #256]
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
  26 ld1rod { z0.d }, p1/z, [x2, #256]
  27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
  28
  29 // Immediate too low (<-256)
  30 ld1rob { z0.b }, p1/z, [x2, #-288]
  31 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
  32 ld1roh { z0.h }, p1/z, [x2, #-288]
  33 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
  34 ld1row { z0.s }, p1/z, [x2, #-288]
  35 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
  36 ld1rod { z0.d }, p1/z, [x2, #-288]
  37 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
  38
  39 // Immediate not a multiple of 32
  40 ld1rob { z0.b }, p1/z, [x2, #16]
  41 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
  42 ld1roh { z0.h }, p1/z, [x2, #16]
  43 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
  44 ld1row { z0.s }, p1/z, [x2, #16]
  45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
  46 ld1rod { z0.d }, p1/z, [x2, #16]
  47 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
  48
  49 // Prediate register too high
  50 ld1rob { z0.b }, p8/z, [x2]
  51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  52 ld1roh { z0.h }, p8/z, [x2]
  53 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  54 ld1row { z0.s }, p8/z, [x2]
  55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  56 ld1rod { z0.d }, p8/z, [x2]
  57 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  58
  59
  60 // --------------------------------------------------------------------------//
  61 // LD1RO (SVE, scalar plus scalar)
  62
  63 // Shift amount not matched to data width
  64 ld1rob { z0.b }, p1/z, [x2, x3, lsl #1]
  65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
  66 ld1roh { z0.h }, p1/z, [x2, x3, lsl #0]
  67 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
  68 ld1row { z0.s }, p1/z, [x2, x3, lsl #3]
  69 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
  70 ld1rod { z0.d }, p1/z, [x2, x3, lsl #2]
  71 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
  72
  73 // Prediate register too high
  74 ld1rob { z0.b }, p8/z, [x2, x3, lsl #0]
  75 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  76 ld1roh { z0.h }, p8/z, [x2, x3, lsl #1]
  77 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  78 ld1row { z0.s }, p8/z, [x2, x3, lsl #2]
  79 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  80 ld1rod { z0.d }, p8/z, [x2, x3, lsl #3]
  81 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)