llvm/test/MC/AArch64/arm32-elf-relocs.s

   1 // RUN: llvm-mc -triple=arm64-linux-gnu_ilp32 -o - < %s | FileCheck %s
   2 // RUN: llvm-mc -triple=arm64-linux-gnu_ilp32 -show-encoding \
   3 // RUN:    -o - < %s | FileCheck --check-prefix=CHECK-ENCODING %s
   4 // RUN: llvm-mc -triple=arm64-linux-gnu_ilp32 -filetype=obj < %s | \
   5 // RUN:   llvm-objdump --triple=arm64-linux-gnu - -r | \
   6 // RUN:   FileCheck %s --check-prefix=CHECK-OBJ-ILP32
   7
   8    add x0, x2, #:lo12:sym
   9 // CHECK: add x0, x2, :lo12:sym
  10 // CHECK-OBJ-ILP32: 0 R_AARCH64_P32_ADD_ABS_LO12_NC sym
  11
  12    add x5, x7, #:dtprel_lo12:sym
  13 // CHECK: add x5, x7, :dtprel_lo12:sym
  14 // CHECK-OBJ-ILP32: 4 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym
  15
  16    add x9, x12, #:dtprel_lo12_nc:sym
  17 // CHECK: add x9, x12, :dtprel_lo12_nc:sym
  18 // CHECK-OBJ-ILP32: 8 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym
  19
  20    add x20, x30, #:tprel_lo12:sym
  21 // CHECK: add x20, x30, :tprel_lo12:sym
  22 // CHECK-OBJ-ILP32: c R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym
  23
  24    add x9, x12, #:tprel_lo12_nc:sym
  25 // CHECK: add x9, x12, :tprel_lo12_nc:sym
  26 // CHECK-OBJ-ILP32: 10 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym
  27
  28    add x5, x0, #:tlsdesc_lo12:sym
  29 // CHECK: add x5, x0, :tlsdesc_lo12:sym
  30 // CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12 sym
  31
  32         add x0, x2, #:lo12:sym+8
  33 // CHECK: add x0, x2, :lo12:sym
  34 // CHECK-OBJ-ILP32: 18 R_AARCH64_P32_ADD_ABS_LO12_NC sym+0x8
  35
  36    add x5, x7, #:dtprel_lo12:sym+1
  37 // CHECK: add x5, x7, :dtprel_lo12:sym+1
  38 // CHECK-OBJ-ILP32: 1c R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym+0x1
  39
  40    add x9, x12, #:dtprel_lo12_nc:sym+2
  41 // CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
  42 // CHECK-OBJ-ILP32:20 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym+0x2
  43
  44    add x20, x30, #:tprel_lo12:sym+12
  45 // CHECK: add x20, x30, :tprel_lo12:sym+12
  46 // CHECK-OBJ-ILP32: 24 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym+0xc
  47
  48    add x9, x12, #:tprel_lo12_nc:sym+54
  49 // CHECK: add x9, x12, :tprel_lo12_nc:sym+54
  50 // CHECK-OBJ-ILP32: 28 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym+0x36
  51
  52    add x5, x0, #:tlsdesc_lo12:sym+70
  53 // CHECK: add x5, x0, :tlsdesc_lo12:sym+70
  54 // CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12 sym+0x46
  55
  56         .hword sym + 4 - .
  57 // CHECK-OBJ-ILP32: 30 R_AARCH64_P32_PREL16 sym+0x4
  58         .word sym - . + 8
  59 // CHECK-OBJ-ILP32: 32 R_AARCH64_P32_PREL32 sym+0x8
  60
  61         .hword sym
  62 // CHECK-OBJ-ILP32: 36 R_AARCH64_P32_ABS16 sym
  63         .word sym+1
  64 // CHECK-OBJ-ILP32: 38 R_AARCH64_P32_ABS32 sym+0x1
  65
  66    adrp x0, sym
  67 // CHECK: adrp x0, sym
  68 // CHECK-OBJ-ILP32: 3c R_AARCH64_P32_ADR_PREL_PG_HI21 sym
  69
  70    adrp x15, :got:sym
  71 // CHECK: adrp x15, :got:sym
  72 // CHECK-OBJ-ILP32: 40 R_AARCH64_P32_ADR_GOT_PAGE sym
  73
  74    adrp x29, :gottprel:sym
  75 // CHECK: adrp x29, :gottprel:sym
  76 // CHECK-OBJ-ILP32: 44 R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym
  77
  78    adrp x2, :tlsdesc:sym
  79 // CHECK: adrp x2, :tlsdesc:sym
  80 // CHECK-OBJ-ILP32: 48 R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym
  81
  82    // LLVM is not competent enough to do this relocation because the
  83    // page boundary could occur anywhere after linking. A relocation
  84    // is needed.
  85    adrp x3, trickQuestion
  86    .global trickQuestion
  87 trickQuestion:
  88 // CHECK: adrp x3, trickQuestion
  89 // CHECK-OBJ-ILP32: 4c R_AARCH64_P32_ADR_PREL_PG_HI21 trickQuestion
  90
  91    ldrb w2, [x3, :lo12:sym]
  92    ldrsb w5, [x7, #:lo12:sym]
  93    ldrsb x11, [x13, :lo12:sym]
  94    ldr b17, [x19, #:lo12:sym]
  95 // CHECK: ldrb w2, [x3, :lo12:sym]
  96 // CHECK: ldrsb w5, [x7, :lo12:sym]
  97 // CHECK: ldrsb x11, [x13, :lo12:sym]
  98 // CHECK: ldr b17, [x19, :lo12:sym]
  99 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
 100 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
 101 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
 102 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST8_ABS_LO12_NC sym
 103
 104    ldrb w23, [x29, #:dtprel_lo12_nc:sym]
 105    ldrsb w23, [x19, #:dtprel_lo12:sym]
 106    ldrsb x17, [x13, :dtprel_lo12_nc:sym]
 107    ldr b11, [x7, #:dtprel_lo12:sym]
 108 // CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym]
 109 // CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
 110 // CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
 111 // CHECK: ldr b11, [x7, :dtprel_lo12:sym]
 112 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
 113 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
 114 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
 115 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
 116
 117    ldrb w1, [x2, :tprel_lo12:sym]
 118    ldrsb w3, [x4, #:tprel_lo12_nc:sym]
 119    ldrsb x5, [x6, :tprel_lo12:sym]
 120    ldr b7, [x8, #:tprel_lo12_nc:sym]
 121 // CHECK: ldrb w1, [x2, :tprel_lo12:sym]
 122 // CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
 123 // CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
 124 // CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
 125 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
 126 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
 127 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
 128 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
 129
 130    ldrh w2, [x3, #:lo12:sym]
 131    ldrsh w5, [x7, :lo12:sym]
 132    ldrsh x11, [x13, #:lo12:sym]
 133    ldr h17, [x19, :lo12:sym]
 134 // CHECK: ldrh w2, [x3, :lo12:sym]
 135 // CHECK: ldrsh w5, [x7, :lo12:sym]
 136 // CHECK: ldrsh x11, [x13, :lo12:sym]
 137 // CHECK: ldr h17, [x19, :lo12:sym]
 138 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
 139 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
 140 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
 141 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST16_ABS_LO12_NC sym
 142
 143    ldrh w23, [x29, #:dtprel_lo12_nc:sym]
 144    ldrsh w23, [x19, :dtprel_lo12:sym]
 145    ldrsh x17, [x13, :dtprel_lo12_nc:sym]
 146    ldr h11, [x7, #:dtprel_lo12:sym]
 147 // CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym]
 148 // CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
 149 // CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
 150 // CHECK: ldr h11, [x7, :dtprel_lo12:sym]
 151 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
 152 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
 153 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
 154 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
 155
 156    ldrh w1, [x2, :tprel_lo12:sym]
 157    ldrsh w3, [x4, #:tprel_lo12_nc:sym]
 158    ldrsh x5, [x6, :tprel_lo12:sym]
 159    ldr h7, [x8, #:tprel_lo12_nc:sym]
 160 // CHECK: ldrh w1, [x2, :tprel_lo12:sym]
 161 // CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
 162 // CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
 163 // CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
 164 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
 165 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
 166 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
 167 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
 168
 169    ldr w1, [x2, #:lo12:sym]
 170    ldrsw x3, [x4, #:lo12:sym]
 171    ldr s4, [x5, :lo12:sym]
 172 // CHECK: ldr w1, [x2, :lo12:sym]
 173 // CHECK: ldrsw x3, [x4, :lo12:sym]
 174 // CHECK: ldr s4, [x5, :lo12:sym]
 175 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym
 176 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym
 177 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST32_ABS_LO12_NC sym
 178
 179    ldr w1, [x2, :dtprel_lo12:sym]
 180    ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
 181    ldr s4, [x5, #:dtprel_lo12_nc:sym]
 182 // CHECK: ldr w1, [x2, :dtprel_lo12:sym]
 183 // CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
 184 // CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
 185 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 sym
 186 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
 187 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
 188
 189
 190    ldr w1, [x2, #:tprel_lo12:sym]
 191    ldrsw x3, [x4, :tprel_lo12_nc:sym]
 192    ldr s4, [x5, :tprel_lo12_nc:sym]
 193 // CHECK: ldr w1, [x2, :tprel_lo12:sym]
 194 // CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
 195 // CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
 196 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 sym
 197 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
 198 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
 199
 200    ldr x28, [x27, :lo12:sym]
 201    ldr d26, [x25, :lo12:sym]
 202 // CHECK: ldr x28, [x27, :lo12:sym]
 203 // CHECK: ldr d26, [x25, :lo12:sym]
 204 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST64_ABS_LO12_NC sym
 205 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST64_ABS_LO12_NC sym
 206
 207    ldr w24, [x23, :got_lo12:sym]
 208    ldr s22, [x21, :got_lo12:sym]
 209 // CHECK: ldr w24, [x23, :got_lo12:sym]
 210 // CHECK: ldr s22, [x21, :got_lo12:sym]
 211 // CHECK-OBJ-ILP32: R_AARCH64_P32_LD32_GOT_LO12_NC sym
 212 // CHECK-OBJ-ILP32: R_AARCH64_P32_LD32_GOT_LO12_NC sym
 213
 214    ldr x24, [x23, :dtprel_lo12_nc:sym]
 215    ldr d22, [x21, :dtprel_lo12:sym]
 216 // CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
 217 // CHECK: ldr d22, [x21, :dtprel_lo12:sym]
 218 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC sym
 219 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 sym
 220
 221    ldr q24, [x23, :dtprel_lo12_nc:sym]
 222    ldr q22, [x21, :dtprel_lo12:sym]
 223 // CHECK: ldr q24, [x23, :dtprel_lo12_nc:sym]
 224 // CHECK: ldr q22, [x21, :dtprel_lo12:sym]
 225 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC sym
 226 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12 sym
 227
 228    ldr x24, [x23, :tprel_lo12:sym]
 229    ldr d22, [x21, :tprel_lo12_nc:sym]
 230 // CHECK: ldr x24, [x23, :tprel_lo12:sym]
 231 // CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
 232 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 sym
 233 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC sym
 234
 235    ldr q24, [x23, :tprel_lo12:sym]
 236    ldr q22, [x21, :tprel_lo12_nc:sym]
 237 // CHECK: ldr q24, [x23, :tprel_lo12:sym]
 238 // CHECK: ldr q22, [x21, :tprel_lo12_nc:sym]
 239 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12 sym
 240 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC sym
 241
 242    ldr w24, [x23, :gottprel_lo12:sym]
 243    ldr s22, [x21, :gottprel_lo12:sym]
 244
 245    ldr w24, [x23, :tlsdesc_lo12:sym]
 246    ldr s22, [x21, :tlsdesc_lo12:sym]
 247 // CHECK: ldr w24, [x23, :tlsdesc_lo12:sym]
 248 // CHECK: ldr s22, [x21, :tlsdesc_lo12:sym]
 249 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSDESC_LD32_LO12 sym
 250 // CHECK-OBJ-ILP32: R_AARCH64_P32_TLSDESC_LD32_LO12 sym
 251
 252    ldr q20, [x19, #:lo12:sym]
 253 // CHECK: ldr q20, [x19, :lo12:sym]
 254 // CHECK-OBJ-ILP32: R_AARCH64_P32_LDST128_ABS_LO12_NC sym
 255 // check encoding here, since encoding test doesn't belong with TLS encoding
 256 // tests, as it isn't a TLS relocation.
 257 // CHECK-ENCODING: ldr q20, [x19, :lo12:sym] // encoding: [0x74,0bAAAAAA10,0b11AAAAAA,0x3d]
 258 // CHECK-ENCODING-NEXT:  0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale16
 259
 260 // Since relocated instructions print without a '#', that syntax should
 261 // certainly be accepted when assembling.
 262    add x3, x5, :lo12:imm
 263 // CHECK: add x3, x5, :lo12:imm