llvm/test/MC/AMDGPU/gfx8_asm_vop2.s

   1 // RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
   2
   3 v_cndmask_b32 v5, v1, v2, vcc
   4 // CHECK: [0x01,0x05,0x0a,0x00]
   5
   6 v_cndmask_b32 v255, v1, v2, vcc
   7 // CHECK: [0x01,0x05,0xfe,0x01]
   8
   9 v_cndmask_b32 v5, v255, v2, vcc
  10 // CHECK: [0xff,0x05,0x0a,0x00]
  11
  12 v_cndmask_b32 v5, 0, v2, vcc
  13 // CHECK: [0x80,0x04,0x0a,0x00]
  14
  15 v_cndmask_b32 v5, -1, v2, vcc
  16 // CHECK: [0xc1,0x04,0x0a,0x00]
  17
  18 v_cndmask_b32 v5, 0.5, v2, vcc
  19 // CHECK: [0xf0,0x04,0x0a,0x00]
  20
  21 v_cndmask_b32 v5, -4.0, v2, vcc
  22 // CHECK: [0xf7,0x04,0x0a,0x00]
  23
  24 v_cndmask_b32 v5, src_lds_direct, v2, vcc
  25 // CHECK: [0xfe,0x04,0x0a,0x00]
  26
  27 v_cndmask_b32 v5, v1, v255, vcc
  28 // CHECK: [0x01,0xff,0x0b,0x00]
  29
  30 v_add_f32 v5, v1, v2
  31 // CHECK: [0x01,0x05,0x0a,0x02]
  32
  33 v_add_f32 v255, v1, v2
  34 // CHECK: [0x01,0x05,0xfe,0x03]
  35
  36 v_add_f32 v5, v255, v2
  37 // CHECK: [0xff,0x05,0x0a,0x02]
  38
  39 v_add_f32 v5, s1, v2
  40 // CHECK: [0x01,0x04,0x0a,0x02]
  41
  42 v_add_f32 v5, s101, v2
  43 // CHECK: [0x65,0x04,0x0a,0x02]
  44
  45 v_add_f32 v5, flat_scratch_lo, v2
  46 // CHECK: [0x66,0x04,0x0a,0x02]
  47
  48 v_add_f32 v5, flat_scratch_hi, v2
  49 // CHECK: [0x67,0x04,0x0a,0x02]
  50
  51 v_add_f32 v5, vcc_lo, v2
  52 // CHECK: [0x6a,0x04,0x0a,0x02]
  53
  54 v_add_f32 v5, vcc_hi, v2
  55 // CHECK: [0x6b,0x04,0x0a,0x02]
  56
  57 v_add_f32 v5, tba_lo, v2
  58 // CHECK: [0x6c,0x04,0x0a,0x02]
  59
  60 v_add_f32 v5, tba_hi, v2
  61 // CHECK: [0x6d,0x04,0x0a,0x02]
  62
  63 v_add_f32 v5, tma_lo, v2
  64 // CHECK: [0x6e,0x04,0x0a,0x02]
  65
  66 v_add_f32 v5, tma_hi, v2
  67 // CHECK: [0x6f,0x04,0x0a,0x02]
  68
  69 v_add_f32 v5, ttmp11, v2
  70 // CHECK: [0x7b,0x04,0x0a,0x02]
  71
  72 v_add_f32 v5, m0, v2
  73 // CHECK: [0x7c,0x04,0x0a,0x02]
  74
  75 v_add_f32 v5, exec_lo, v2
  76 // CHECK: [0x7e,0x04,0x0a,0x02]
  77
  78 v_add_f32 v5, exec_hi, v2
  79 // CHECK: [0x7f,0x04,0x0a,0x02]
  80
  81 v_add_f32 v5, 0, v2
  82 // CHECK: [0x80,0x04,0x0a,0x02]
  83
  84 v_add_f32 v5, -1, v2
  85 // CHECK: [0xc1,0x04,0x0a,0x02]
  86
  87 v_add_f32 v5, 0.5, v2
  88 // CHECK: [0xf0,0x04,0x0a,0x02]
  89
  90 v_add_f32 v5, -4.0, v2
  91 // CHECK: [0xf7,0x04,0x0a,0x02]
  92
  93 v_add_f32 v5, src_vccz, v2
  94 // CHECK: [0xfb,0x04,0x0a,0x02]
  95
  96 v_add_f32 v5, src_execz, v2
  97 // CHECK: [0xfc,0x04,0x0a,0x02]
  98
  99 v_add_f32 v5, src_scc, v2
 100 // CHECK: [0xfd,0x04,0x0a,0x02]
 101
 102 v_add_f32 v5, src_lds_direct, v2
 103 // CHECK: [0xfe,0x04,0x0a,0x02]
 104
 105 v_add_f32 v5, 0xaf123456, v2
 106 // CHECK: [0xff,0x04,0x0a,0x02,0x56,0x34,0x12,0xaf]
 107
 108 v_add_f32 v5, 0x3f717273, v2
 109 // CHECK: [0xff,0x04,0x0a,0x02,0x73,0x72,0x71,0x3f]
 110
 111 v_add_f32 v5, v1, v255
 112 // CHECK: [0x01,0xff,0x0b,0x02]
 113
 114 v_sub_f32 v5, v1, v2
 115 // CHECK: [0x01,0x05,0x0a,0x04]
 116
 117 v_sub_f32 v255, v1, v2
 118 // CHECK: [0x01,0x05,0xfe,0x05]
 119
 120 v_sub_f32 v5, v255, v2
 121 // CHECK: [0xff,0x05,0x0a,0x04]
 122
 123 v_sub_f32 v5, s1, v2
 124 // CHECK: [0x01,0x04,0x0a,0x04]
 125
 126 v_sub_f32 v5, s101, v2
 127 // CHECK: [0x65,0x04,0x0a,0x04]
 128
 129 v_sub_f32 v5, flat_scratch_lo, v2
 130 // CHECK: [0x66,0x04,0x0a,0x04]
 131
 132 v_sub_f32 v5, flat_scratch_hi, v2
 133 // CHECK: [0x67,0x04,0x0a,0x04]
 134
 135 v_sub_f32 v5, vcc_lo, v2
 136 // CHECK: [0x6a,0x04,0x0a,0x04]
 137
 138 v_sub_f32 v5, vcc_hi, v2
 139 // CHECK: [0x6b,0x04,0x0a,0x04]
 140
 141 v_sub_f32 v5, tba_lo, v2
 142 // CHECK: [0x6c,0x04,0x0a,0x04]
 143
 144 v_sub_f32 v5, tba_hi, v2
 145 // CHECK: [0x6d,0x04,0x0a,0x04]
 146
 147 v_sub_f32 v5, tma_lo, v2
 148 // CHECK: [0x6e,0x04,0x0a,0x04]
 149
 150 v_sub_f32 v5, tma_hi, v2
 151 // CHECK: [0x6f,0x04,0x0a,0x04]
 152
 153 v_sub_f32 v5, ttmp11, v2
 154 // CHECK: [0x7b,0x04,0x0a,0x04]
 155
 156 v_sub_f32 v5, m0, v2
 157 // CHECK: [0x7c,0x04,0x0a,0x04]
 158
 159 v_sub_f32 v5, exec_lo, v2
 160 // CHECK: [0x7e,0x04,0x0a,0x04]
 161
 162 v_sub_f32 v5, exec_hi, v2
 163 // CHECK: [0x7f,0x04,0x0a,0x04]
 164
 165 v_sub_f32 v5, 0, v2
 166 // CHECK: [0x80,0x04,0x0a,0x04]
 167
 168 v_sub_f32 v5, -1, v2
 169 // CHECK: [0xc1,0x04,0x0a,0x04]
 170
 171 v_sub_f32 v5, 0.5, v2
 172 // CHECK: [0xf0,0x04,0x0a,0x04]
 173
 174 v_sub_f32 v5, -4.0, v2
 175 // CHECK: [0xf7,0x04,0x0a,0x04]
 176
 177 v_sub_f32 v5, src_vccz, v2
 178 // CHECK: [0xfb,0x04,0x0a,0x04]
 179
 180 v_sub_f32 v5, src_execz, v2
 181 // CHECK: [0xfc,0x04,0x0a,0x04]
 182
 183 v_sub_f32 v5, src_scc, v2
 184 // CHECK: [0xfd,0x04,0x0a,0x04]
 185
 186 v_sub_f32 v5, src_lds_direct, v2
 187 // CHECK: [0xfe,0x04,0x0a,0x04]
 188
 189 v_sub_f32 v5, 0xaf123456, v2
 190 // CHECK: [0xff,0x04,0x0a,0x04,0x56,0x34,0x12,0xaf]
 191
 192 v_sub_f32 v5, 0x3f717273, v2
 193 // CHECK: [0xff,0x04,0x0a,0x04,0x73,0x72,0x71,0x3f]
 194
 195 v_sub_f32 v5, v1, v255
 196 // CHECK: [0x01,0xff,0x0b,0x04]
 197
 198 v_subrev_f32 v5, v1, v2
 199 // CHECK: [0x01,0x05,0x0a,0x06]
 200
 201 v_subrev_f32 v255, v1, v2
 202 // CHECK: [0x01,0x05,0xfe,0x07]
 203
 204 v_subrev_f32 v5, v255, v2
 205 // CHECK: [0xff,0x05,0x0a,0x06]
 206
 207 v_subrev_f32 v5, s1, v2
 208 // CHECK: [0x01,0x04,0x0a,0x06]
 209
 210 v_subrev_f32 v5, s101, v2
 211 // CHECK: [0x65,0x04,0x0a,0x06]
 212
 213 v_subrev_f32 v5, flat_scratch_lo, v2
 214 // CHECK: [0x66,0x04,0x0a,0x06]
 215
 216 v_subrev_f32 v5, flat_scratch_hi, v2
 217 // CHECK: [0x67,0x04,0x0a,0x06]
 218
 219 v_subrev_f32 v5, vcc_lo, v2
 220 // CHECK: [0x6a,0x04,0x0a,0x06]
 221
 222 v_subrev_f32 v5, vcc_hi, v2
 223 // CHECK: [0x6b,0x04,0x0a,0x06]
 224
 225 v_subrev_f32 v5, tba_lo, v2
 226 // CHECK: [0x6c,0x04,0x0a,0x06]
 227
 228 v_subrev_f32 v5, tba_hi, v2
 229 // CHECK: [0x6d,0x04,0x0a,0x06]
 230
 231 v_subrev_f32 v5, tma_lo, v2
 232 // CHECK: [0x6e,0x04,0x0a,0x06]
 233
 234 v_subrev_f32 v5, tma_hi, v2
 235 // CHECK: [0x6f,0x04,0x0a,0x06]
 236
 237 v_subrev_f32 v5, ttmp11, v2
 238 // CHECK: [0x7b,0x04,0x0a,0x06]
 239
 240 v_subrev_f32 v5, m0, v2
 241 // CHECK: [0x7c,0x04,0x0a,0x06]
 242
 243 v_subrev_f32 v5, exec_lo, v2
 244 // CHECK: [0x7e,0x04,0x0a,0x06]
 245
 246 v_subrev_f32 v5, exec_hi, v2
 247 // CHECK: [0x7f,0x04,0x0a,0x06]
 248
 249 v_subrev_f32 v5, 0, v2
 250 // CHECK: [0x80,0x04,0x0a,0x06]
 251
 252 v_subrev_f32 v5, -1, v2
 253 // CHECK: [0xc1,0x04,0x0a,0x06]
 254
 255 v_subrev_f32 v5, 0.5, v2
 256 // CHECK: [0xf0,0x04,0x0a,0x06]
 257
 258 v_subrev_f32 v5, -4.0, v2
 259 // CHECK: [0xf7,0x04,0x0a,0x06]
 260
 261 v_subrev_f32 v5, src_vccz, v2
 262 // CHECK: [0xfb,0x04,0x0a,0x06]
 263
 264 v_subrev_f32 v5, src_execz, v2
 265 // CHECK: [0xfc,0x04,0x0a,0x06]
 266
 267 v_subrev_f32 v5, src_scc, v2
 268 // CHECK: [0xfd,0x04,0x0a,0x06]
 269
 270 v_subrev_f32 v5, 0xaf123456, v2
 271 // CHECK: [0xff,0x04,0x0a,0x06,0x56,0x34,0x12,0xaf]
 272
 273 v_subrev_f32 v5, 0x3f717273, v2
 274 // CHECK: [0xff,0x04,0x0a,0x06,0x73,0x72,0x71,0x3f]
 275
 276 v_subrev_f32 v5, v1, v255
 277 // CHECK: [0x01,0xff,0x0b,0x06]
 278
 279 v_mul_legacy_f32 v5, v1, v2
 280 // CHECK: [0x01,0x05,0x0a,0x08]
 281
 282 v_mul_legacy_f32 v255, v1, v2
 283 // CHECK: [0x01,0x05,0xfe,0x09]
 284
 285 v_mul_legacy_f32 v5, v255, v2
 286 // CHECK: [0xff,0x05,0x0a,0x08]
 287
 288 v_mul_legacy_f32 v5, s1, v2
 289 // CHECK: [0x01,0x04,0x0a,0x08]
 290
 291 v_mul_legacy_f32 v5, s101, v2
 292 // CHECK: [0x65,0x04,0x0a,0x08]
 293
 294 v_mul_legacy_f32 v5, flat_scratch_lo, v2
 295 // CHECK: [0x66,0x04,0x0a,0x08]
 296
 297 v_mul_legacy_f32 v5, flat_scratch_hi, v2
 298 // CHECK: [0x67,0x04,0x0a,0x08]
 299
 300 v_mul_legacy_f32 v5, vcc_lo, v2
 301 // CHECK: [0x6a,0x04,0x0a,0x08]
 302
 303 v_mul_legacy_f32 v5, vcc_hi, v2
 304 // CHECK: [0x6b,0x04,0x0a,0x08]
 305
 306 v_mul_legacy_f32 v5, tba_lo, v2
 307 // CHECK: [0x6c,0x04,0x0a,0x08]
 308
 309 v_mul_legacy_f32 v5, tba_hi, v2
 310 // CHECK: [0x6d,0x04,0x0a,0x08]
 311
 312 v_mul_legacy_f32 v5, tma_lo, v2
 313 // CHECK: [0x6e,0x04,0x0a,0x08]
 314
 315 v_mul_legacy_f32 v5, tma_hi, v2
 316 // CHECK: [0x6f,0x04,0x0a,0x08]
 317
 318 v_mul_legacy_f32 v5, ttmp11, v2
 319 // CHECK: [0x7b,0x04,0x0a,0x08]
 320
 321 v_mul_legacy_f32 v5, m0, v2
 322 // CHECK: [0x7c,0x04,0x0a,0x08]
 323
 324 v_mul_legacy_f32 v5, exec_lo, v2
 325 // CHECK: [0x7e,0x04,0x0a,0x08]
 326
 327 v_mul_legacy_f32 v5, exec_hi, v2
 328 // CHECK: [0x7f,0x04,0x0a,0x08]
 329
 330 v_mul_legacy_f32 v5, 0, v2
 331 // CHECK: [0x80,0x04,0x0a,0x08]
 332
 333 v_mul_legacy_f32 v5, -1, v2
 334 // CHECK: [0xc1,0x04,0x0a,0x08]
 335
 336 v_mul_legacy_f32 v5, 0.5, v2
 337 // CHECK: [0xf0,0x04,0x0a,0x08]
 338
 339 v_mul_legacy_f32 v5, -4.0, v2
 340 // CHECK: [0xf7,0x04,0x0a,0x08]
 341
 342 v_mul_legacy_f32 v5, src_vccz, v2
 343 // CHECK: [0xfb,0x04,0x0a,0x08]
 344
 345 v_mul_legacy_f32 v5, src_execz, v2
 346 // CHECK: [0xfc,0x04,0x0a,0x08]
 347
 348 v_mul_legacy_f32 v5, src_scc, v2
 349 // CHECK: [0xfd,0x04,0x0a,0x08]
 350
 351 v_mul_legacy_f32 v5, src_lds_direct, v2
 352 // CHECK: [0xfe,0x04,0x0a,0x08]
 353
 354 v_mul_legacy_f32 v5, 0xaf123456, v2
 355 // CHECK: [0xff,0x04,0x0a,0x08,0x56,0x34,0x12,0xaf]
 356
 357 v_mul_legacy_f32 v5, 0x3f717273, v2
 358 // CHECK: [0xff,0x04,0x0a,0x08,0x73,0x72,0x71,0x3f]
 359
 360 v_mul_legacy_f32 v5, v1, v255
 361 // CHECK: [0x01,0xff,0x0b,0x08]
 362
 363 v_mul_f32 v5, v1, v2
 364 // CHECK: [0x01,0x05,0x0a,0x0a]
 365
 366 v_mul_f32 v255, v1, v2
 367 // CHECK: [0x01,0x05,0xfe,0x0b]
 368
 369 v_mul_f32 v5, v255, v2
 370 // CHECK: [0xff,0x05,0x0a,0x0a]
 371
 372 v_mul_f32 v5, s1, v2
 373 // CHECK: [0x01,0x04,0x0a,0x0a]
 374
 375 v_mul_f32 v5, s101, v2
 376 // CHECK: [0x65,0x04,0x0a,0x0a]
 377
 378 v_mul_f32 v5, flat_scratch_lo, v2
 379 // CHECK: [0x66,0x04,0x0a,0x0a]
 380
 381 v_mul_f32 v5, flat_scratch_hi, v2
 382 // CHECK: [0x67,0x04,0x0a,0x0a]
 383
 384 v_mul_f32 v5, vcc_lo, v2
 385 // CHECK: [0x6a,0x04,0x0a,0x0a]
 386
 387 v_mul_f32 v5, vcc_hi, v2
 388 // CHECK: [0x6b,0x04,0x0a,0x0a]
 389
 390 v_mul_f32 v5, tba_lo, v2
 391 // CHECK: [0x6c,0x04,0x0a,0x0a]
 392
 393 v_mul_f32 v5, tba_hi, v2
 394 // CHECK: [0x6d,0x04,0x0a,0x0a]
 395
 396 v_mul_f32 v5, tma_lo, v2
 397 // CHECK: [0x6e,0x04,0x0a,0x0a]
 398
 399 v_mul_f32 v5, tma_hi, v2
 400 // CHECK: [0x6f,0x04,0x0a,0x0a]
 401
 402 v_mul_f32 v5, ttmp11, v2
 403 // CHECK: [0x7b,0x04,0x0a,0x0a]
 404
 405 v_mul_f32 v5, m0, v2
 406 // CHECK: [0x7c,0x04,0x0a,0x0a]
 407
 408 v_mul_f32 v5, exec_lo, v2
 409 // CHECK: [0x7e,0x04,0x0a,0x0a]
 410
 411 v_mul_f32 v5, exec_hi, v2
 412 // CHECK: [0x7f,0x04,0x0a,0x0a]
 413
 414 v_mul_f32 v5, 0, v2
 415 // CHECK: [0x80,0x04,0x0a,0x0a]
 416
 417 v_mul_f32 v5, -1, v2
 418 // CHECK: [0xc1,0x04,0x0a,0x0a]
 419
 420 v_mul_f32 v5, 0.5, v2
 421 // CHECK: [0xf0,0x04,0x0a,0x0a]
 422
 423 v_mul_f32 v5, -4.0, v2
 424 // CHECK: [0xf7,0x04,0x0a,0x0a]
 425
 426 v_mul_f32 v5, src_vccz, v2
 427 // CHECK: [0xfb,0x04,0x0a,0x0a]
 428
 429 v_mul_f32 v5, src_execz, v2
 430 // CHECK: [0xfc,0x04,0x0a,0x0a]
 431
 432 v_mul_f32 v5, src_scc, v2
 433 // CHECK: [0xfd,0x04,0x0a,0x0a]
 434
 435 v_mul_f32 v5, src_lds_direct, v2
 436 // CHECK: [0xfe,0x04,0x0a,0x0a]
 437
 438 v_mul_f32 v5, 0xaf123456, v2
 439 // CHECK: [0xff,0x04,0x0a,0x0a,0x56,0x34,0x12,0xaf]
 440
 441 v_mul_f32 v5, 0x3f717273, v2
 442 // CHECK: [0xff,0x04,0x0a,0x0a,0x73,0x72,0x71,0x3f]
 443
 444 v_mul_f32 v5, v1, v255
 445 // CHECK: [0x01,0xff,0x0b,0x0a]
 446
 447 v_mul_i32_i24 v5, v1, v2
 448 // CHECK: [0x01,0x05,0x0a,0x0c]
 449
 450 v_mul_i32_i24 v255, v1, v2
 451 // CHECK: [0x01,0x05,0xfe,0x0d]
 452
 453 v_mul_i32_i24 v5, v255, v2
 454 // CHECK: [0xff,0x05,0x0a,0x0c]
 455
 456 v_mul_i32_i24 v5, s1, v2
 457 // CHECK: [0x01,0x04,0x0a,0x0c]
 458
 459 v_mul_i32_i24 v5, s101, v2
 460 // CHECK: [0x65,0x04,0x0a,0x0c]
 461
 462 v_mul_i32_i24 v5, flat_scratch_lo, v2
 463 // CHECK: [0x66,0x04,0x0a,0x0c]
 464
 465 v_mul_i32_i24 v5, flat_scratch_hi, v2
 466 // CHECK: [0x67,0x04,0x0a,0x0c]
 467
 468 v_mul_i32_i24 v5, vcc_lo, v2
 469 // CHECK: [0x6a,0x04,0x0a,0x0c]
 470
 471 v_mul_i32_i24 v5, vcc_hi, v2
 472 // CHECK: [0x6b,0x04,0x0a,0x0c]
 473
 474 v_mul_i32_i24 v5, tba_lo, v2
 475 // CHECK: [0x6c,0x04,0x0a,0x0c]
 476
 477 v_mul_i32_i24 v5, tba_hi, v2
 478 // CHECK: [0x6d,0x04,0x0a,0x0c]
 479
 480 v_mul_i32_i24 v5, tma_lo, v2
 481 // CHECK: [0x6e,0x04,0x0a,0x0c]
 482
 483 v_mul_i32_i24 v5, tma_hi, v2
 484 // CHECK: [0x6f,0x04,0x0a,0x0c]
 485
 486 v_mul_i32_i24 v5, ttmp11, v2
 487 // CHECK: [0x7b,0x04,0x0a,0x0c]
 488
 489 v_mul_i32_i24 v5, m0, v2
 490 // CHECK: [0x7c,0x04,0x0a,0x0c]
 491
 492 v_mul_i32_i24 v5, exec_lo, v2
 493 // CHECK: [0x7e,0x04,0x0a,0x0c]
 494
 495 v_mul_i32_i24 v5, exec_hi, v2
 496 // CHECK: [0x7f,0x04,0x0a,0x0c]
 497
 498 v_mul_i32_i24 v5, 0, v2
 499 // CHECK: [0x80,0x04,0x0a,0x0c]
 500
 501 v_mul_i32_i24 v5, -1, v2
 502 // CHECK: [0xc1,0x04,0x0a,0x0c]
 503
 504 v_mul_i32_i24 v5, 0.5, v2
 505 // CHECK: [0xf0,0x04,0x0a,0x0c]
 506
 507 v_mul_i32_i24 v5, -4.0, v2
 508 // CHECK: [0xf7,0x04,0x0a,0x0c]
 509
 510 v_mul_i32_i24 v5, src_vccz, v2
 511 // CHECK: [0xfb,0x04,0x0a,0x0c]
 512
 513 v_mul_i32_i24 v5, src_execz, v2
 514 // CHECK: [0xfc,0x04,0x0a,0x0c]
 515
 516 v_mul_i32_i24 v5, src_scc, v2
 517 // CHECK: [0xfd,0x04,0x0a,0x0c]
 518
 519 v_mul_i32_i24 v5, src_lds_direct, v2
 520 // CHECK: [0xfe,0x04,0x0a,0x0c]
 521
 522 v_mul_i32_i24 v5, 0xaf123456, v2
 523 // CHECK: [0xff,0x04,0x0a,0x0c,0x56,0x34,0x12,0xaf]
 524
 525 v_mul_i32_i24 v5, 0x3f717273, v2
 526 // CHECK: [0xff,0x04,0x0a,0x0c,0x73,0x72,0x71,0x3f]
 527
 528 v_mul_i32_i24 v5, v1, v255
 529 // CHECK: [0x01,0xff,0x0b,0x0c]
 530
 531 v_mul_hi_i32_i24 v5, v1, v2
 532 // CHECK: [0x01,0x05,0x0a,0x0e]
 533
 534 v_mul_hi_i32_i24 v255, v1, v2
 535 // CHECK: [0x01,0x05,0xfe,0x0f]
 536
 537 v_mul_hi_i32_i24 v5, v255, v2
 538 // CHECK: [0xff,0x05,0x0a,0x0e]
 539
 540 v_mul_hi_i32_i24 v5, s1, v2
 541 // CHECK: [0x01,0x04,0x0a,0x0e]
 542
 543 v_mul_hi_i32_i24 v5, s101, v2
 544 // CHECK: [0x65,0x04,0x0a,0x0e]
 545
 546 v_mul_hi_i32_i24 v5, flat_scratch_lo, v2
 547 // CHECK: [0x66,0x04,0x0a,0x0e]
 548
 549 v_mul_hi_i32_i24 v5, flat_scratch_hi, v2
 550 // CHECK: [0x67,0x04,0x0a,0x0e]
 551
 552 v_mul_hi_i32_i24 v5, vcc_lo, v2
 553 // CHECK: [0x6a,0x04,0x0a,0x0e]
 554
 555 v_mul_hi_i32_i24 v5, vcc_hi, v2
 556 // CHECK: [0x6b,0x04,0x0a,0x0e]
 557
 558 v_mul_hi_i32_i24 v5, tba_lo, v2
 559 // CHECK: [0x6c,0x04,0x0a,0x0e]
 560
 561 v_mul_hi_i32_i24 v5, tba_hi, v2
 562 // CHECK: [0x6d,0x04,0x0a,0x0e]
 563
 564 v_mul_hi_i32_i24 v5, tma_lo, v2
 565 // CHECK: [0x6e,0x04,0x0a,0x0e]
 566
 567 v_mul_hi_i32_i24 v5, tma_hi, v2
 568 // CHECK: [0x6f,0x04,0x0a,0x0e]
 569
 570 v_mul_hi_i32_i24 v5, ttmp11, v2
 571 // CHECK: [0x7b,0x04,0x0a,0x0e]
 572
 573 v_mul_hi_i32_i24 v5, m0, v2
 574 // CHECK: [0x7c,0x04,0x0a,0x0e]
 575
 576 v_mul_hi_i32_i24 v5, exec_lo, v2
 577 // CHECK: [0x7e,0x04,0x0a,0x0e]
 578
 579 v_mul_hi_i32_i24 v5, exec_hi, v2
 580 // CHECK: [0x7f,0x04,0x0a,0x0e]
 581
 582 v_mul_hi_i32_i24 v5, 0, v2
 583 // CHECK: [0x80,0x04,0x0a,0x0e]
 584
 585 v_mul_hi_i32_i24 v5, -1, v2
 586 // CHECK: [0xc1,0x04,0x0a,0x0e]
 587
 588 v_mul_hi_i32_i24 v5, 0.5, v2
 589 // CHECK: [0xf0,0x04,0x0a,0x0e]
 590
 591 v_mul_hi_i32_i24 v5, -4.0, v2
 592 // CHECK: [0xf7,0x04,0x0a,0x0e]
 593
 594 v_mul_hi_i32_i24 v5, src_vccz, v2
 595 // CHECK: [0xfb,0x04,0x0a,0x0e]
 596
 597 v_mul_hi_i32_i24 v5, src_execz, v2
 598 // CHECK: [0xfc,0x04,0x0a,0x0e]
 599
 600 v_mul_hi_i32_i24 v5, src_scc, v2
 601 // CHECK: [0xfd,0x04,0x0a,0x0e]
 602
 603 v_mul_hi_i32_i24 v5, src_lds_direct, v2
 604 // CHECK: [0xfe,0x04,0x0a,0x0e]
 605
 606 v_mul_hi_i32_i24 v5, 0xaf123456, v2
 607 // CHECK: [0xff,0x04,0x0a,0x0e,0x56,0x34,0x12,0xaf]
 608
 609 v_mul_hi_i32_i24 v5, 0x3f717273, v2
 610 // CHECK: [0xff,0x04,0x0a,0x0e,0x73,0x72,0x71,0x3f]
 611
 612 v_mul_hi_i32_i24 v5, v1, v255
 613 // CHECK: [0x01,0xff,0x0b,0x0e]
 614
 615 v_mul_u32_u24 v5, v1, v2
 616 // CHECK: [0x01,0x05,0x0a,0x10]
 617
 618 v_mul_u32_u24 v255, v1, v2
 619 // CHECK: [0x01,0x05,0xfe,0x11]
 620
 621 v_mul_u32_u24 v5, v255, v2
 622 // CHECK: [0xff,0x05,0x0a,0x10]
 623
 624 v_mul_u32_u24 v5, s1, v2
 625 // CHECK: [0x01,0x04,0x0a,0x10]
 626
 627 v_mul_u32_u24 v5, s101, v2
 628 // CHECK: [0x65,0x04,0x0a,0x10]
 629
 630 v_mul_u32_u24 v5, flat_scratch_lo, v2
 631 // CHECK: [0x66,0x04,0x0a,0x10]
 632
 633 v_mul_u32_u24 v5, flat_scratch_hi, v2
 634 // CHECK: [0x67,0x04,0x0a,0x10]
 635
 636 v_mul_u32_u24 v5, vcc_lo, v2
 637 // CHECK: [0x6a,0x04,0x0a,0x10]
 638
 639 v_mul_u32_u24 v5, vcc_hi, v2
 640 // CHECK: [0x6b,0x04,0x0a,0x10]
 641
 642 v_mul_u32_u24 v5, tba_lo, v2
 643 // CHECK: [0x6c,0x04,0x0a,0x10]
 644
 645 v_mul_u32_u24 v5, tba_hi, v2
 646 // CHECK: [0x6d,0x04,0x0a,0x10]
 647
 648 v_mul_u32_u24 v5, tma_lo, v2
 649 // CHECK: [0x6e,0x04,0x0a,0x10]
 650
 651 v_mul_u32_u24 v5, tma_hi, v2
 652 // CHECK: [0x6f,0x04,0x0a,0x10]
 653
 654 v_mul_u32_u24 v5, ttmp11, v2
 655 // CHECK: [0x7b,0x04,0x0a,0x10]
 656
 657 v_mul_u32_u24 v5, m0, v2
 658 // CHECK: [0x7c,0x04,0x0a,0x10]
 659
 660 v_mul_u32_u24 v5, exec_lo, v2
 661 // CHECK: [0x7e,0x04,0x0a,0x10]
 662
 663 v_mul_u32_u24 v5, exec_hi, v2
 664 // CHECK: [0x7f,0x04,0x0a,0x10]
 665
 666 v_mul_u32_u24 v5, 0, v2
 667 // CHECK: [0x80,0x04,0x0a,0x10]
 668
 669 v_mul_u32_u24 v5, -1, v2
 670 // CHECK: [0xc1,0x04,0x0a,0x10]
 671
 672 v_mul_u32_u24 v5, 0.5, v2
 673 // CHECK: [0xf0,0x04,0x0a,0x10]
 674
 675 v_mul_u32_u24 v5, -4.0, v2
 676 // CHECK: [0xf7,0x04,0x0a,0x10]
 677
 678 v_mul_u32_u24 v5, src_vccz, v2
 679 // CHECK: [0xfb,0x04,0x0a,0x10]
 680
 681 v_mul_u32_u24 v5, src_execz, v2
 682 // CHECK: [0xfc,0x04,0x0a,0x10]
 683
 684 v_mul_u32_u24 v5, src_scc, v2
 685 // CHECK: [0xfd,0x04,0x0a,0x10]
 686
 687 v_mul_u32_u24 v5, src_lds_direct, v2
 688 // CHECK: [0xfe,0x04,0x0a,0x10]
 689
 690 v_mul_u32_u24 v5, 0xaf123456, v2
 691 // CHECK: [0xff,0x04,0x0a,0x10,0x56,0x34,0x12,0xaf]
 692
 693 v_mul_u32_u24 v5, 0x3f717273, v2
 694 // CHECK: [0xff,0x04,0x0a,0x10,0x73,0x72,0x71,0x3f]
 695
 696 v_mul_u32_u24 v5, v1, v255
 697 // CHECK: [0x01,0xff,0x0b,0x10]
 698
 699 v_mul_hi_u32_u24 v5, v1, v2
 700 // CHECK: [0x01,0x05,0x0a,0x12]
 701
 702 v_mul_hi_u32_u24 v255, v1, v2
 703 // CHECK: [0x01,0x05,0xfe,0x13]
 704
 705 v_mul_hi_u32_u24 v5, v255, v2
 706 // CHECK: [0xff,0x05,0x0a,0x12]
 707
 708 v_mul_hi_u32_u24 v5, s1, v2
 709 // CHECK: [0x01,0x04,0x0a,0x12]
 710
 711 v_mul_hi_u32_u24 v5, s101, v2
 712 // CHECK: [0x65,0x04,0x0a,0x12]
 713
 714 v_mul_hi_u32_u24 v5, flat_scratch_lo, v2
 715 // CHECK: [0x66,0x04,0x0a,0x12]
 716
 717 v_mul_hi_u32_u24 v5, flat_scratch_hi, v2
 718 // CHECK: [0x67,0x04,0x0a,0x12]
 719
 720 v_mul_hi_u32_u24 v5, vcc_lo, v2
 721 // CHECK: [0x6a,0x04,0x0a,0x12]
 722
 723 v_mul_hi_u32_u24 v5, vcc_hi, v2
 724 // CHECK: [0x6b,0x04,0x0a,0x12]
 725
 726 v_mul_hi_u32_u24 v5, tba_lo, v2
 727 // CHECK: [0x6c,0x04,0x0a,0x12]
 728
 729 v_mul_hi_u32_u24 v5, tba_hi, v2
 730 // CHECK: [0x6d,0x04,0x0a,0x12]
 731
 732 v_mul_hi_u32_u24 v5, tma_lo, v2
 733 // CHECK: [0x6e,0x04,0x0a,0x12]
 734
 735 v_mul_hi_u32_u24 v5, tma_hi, v2
 736 // CHECK: [0x6f,0x04,0x0a,0x12]
 737
 738 v_mul_hi_u32_u24 v5, ttmp11, v2
 739 // CHECK: [0x7b,0x04,0x0a,0x12]
 740
 741 v_mul_hi_u32_u24 v5, m0, v2
 742 // CHECK: [0x7c,0x04,0x0a,0x12]
 743
 744 v_mul_hi_u32_u24 v5, exec_lo, v2
 745 // CHECK: [0x7e,0x04,0x0a,0x12]
 746
 747 v_mul_hi_u32_u24 v5, exec_hi, v2
 748 // CHECK: [0x7f,0x04,0x0a,0x12]
 749
 750 v_mul_hi_u32_u24 v5, 0, v2
 751 // CHECK: [0x80,0x04,0x0a,0x12]
 752
 753 v_mul_hi_u32_u24 v5, -1, v2
 754 // CHECK: [0xc1,0x04,0x0a,0x12]
 755
 756 v_mul_hi_u32_u24 v5, 0.5, v2
 757 // CHECK: [0xf0,0x04,0x0a,0x12]
 758
 759 v_mul_hi_u32_u24 v5, -4.0, v2
 760 // CHECK: [0xf7,0x04,0x0a,0x12]
 761
 762 v_mul_hi_u32_u24 v5, src_vccz, v2
 763 // CHECK: [0xfb,0x04,0x0a,0x12]
 764
 765 v_mul_hi_u32_u24 v5, src_execz, v2
 766 // CHECK: [0xfc,0x04,0x0a,0x12]
 767
 768 v_mul_hi_u32_u24 v5, src_scc, v2
 769 // CHECK: [0xfd,0x04,0x0a,0x12]
 770
 771 v_mul_hi_u32_u24 v5, src_lds_direct, v2
 772 // CHECK: [0xfe,0x04,0x0a,0x12]
 773
 774 v_mul_hi_u32_u24 v5, 0xaf123456, v2
 775 // CHECK: [0xff,0x04,0x0a,0x12,0x56,0x34,0x12,0xaf]
 776
 777 v_mul_hi_u32_u24 v5, 0x3f717273, v2
 778 // CHECK: [0xff,0x04,0x0a,0x12,0x73,0x72,0x71,0x3f]
 779
 780 v_mul_hi_u32_u24 v5, v1, v255
 781 // CHECK: [0x01,0xff,0x0b,0x12]
 782
 783 v_min_f32 v5, v1, v2
 784 // CHECK: [0x01,0x05,0x0a,0x14]
 785
 786 v_min_f32 v255, v1, v2
 787 // CHECK: [0x01,0x05,0xfe,0x15]
 788
 789 v_min_f32 v5, v255, v2
 790 // CHECK: [0xff,0x05,0x0a,0x14]
 791
 792 v_min_f32 v5, s1, v2
 793 // CHECK: [0x01,0x04,0x0a,0x14]
 794
 795 v_min_f32 v5, s101, v2
 796 // CHECK: [0x65,0x04,0x0a,0x14]
 797
 798 v_min_f32 v5, flat_scratch_lo, v2
 799 // CHECK: [0x66,0x04,0x0a,0x14]
 800
 801 v_min_f32 v5, flat_scratch_hi, v2
 802 // CHECK: [0x67,0x04,0x0a,0x14]
 803
 804 v_min_f32 v5, vcc_lo, v2
 805 // CHECK: [0x6a,0x04,0x0a,0x14]
 806
 807 v_min_f32 v5, vcc_hi, v2
 808 // CHECK: [0x6b,0x04,0x0a,0x14]
 809
 810 v_min_f32 v5, tba_lo, v2
 811 // CHECK: [0x6c,0x04,0x0a,0x14]
 812
 813 v_min_f32 v5, tba_hi, v2
 814 // CHECK: [0x6d,0x04,0x0a,0x14]
 815
 816 v_min_f32 v5, tma_lo, v2
 817 // CHECK: [0x6e,0x04,0x0a,0x14]
 818
 819 v_min_f32 v5, tma_hi, v2
 820 // CHECK: [0x6f,0x04,0x0a,0x14]
 821
 822 v_min_f32 v5, ttmp11, v2
 823 // CHECK: [0x7b,0x04,0x0a,0x14]
 824
 825 v_min_f32 v5, m0, v2
 826 // CHECK: [0x7c,0x04,0x0a,0x14]
 827
 828 v_min_f32 v5, exec_lo, v2
 829 // CHECK: [0x7e,0x04,0x0a,0x14]
 830
 831 v_min_f32 v5, exec_hi, v2
 832 // CHECK: [0x7f,0x04,0x0a,0x14]
 833
 834 v_min_f32 v5, 0, v2
 835 // CHECK: [0x80,0x04,0x0a,0x14]
 836
 837 v_min_f32 v5, -1, v2
 838 // CHECK: [0xc1,0x04,0x0a,0x14]
 839
 840 v_min_f32 v5, 0.5, v2
 841 // CHECK: [0xf0,0x04,0x0a,0x14]
 842
 843 v_min_f32 v5, -4.0, v2
 844 // CHECK: [0xf7,0x04,0x0a,0x14]
 845
 846 v_min_f32 v5, src_vccz, v2
 847 // CHECK: [0xfb,0x04,0x0a,0x14]
 848
 849 v_min_f32 v5, src_execz, v2
 850 // CHECK: [0xfc,0x04,0x0a,0x14]
 851
 852 v_min_f32 v5, src_scc, v2
 853 // CHECK: [0xfd,0x04,0x0a,0x14]
 854
 855 v_min_f32 v5, src_lds_direct, v2
 856 // CHECK: [0xfe,0x04,0x0a,0x14]
 857
 858 v_min_f32 v5, 0xaf123456, v2
 859 // CHECK: [0xff,0x04,0x0a,0x14,0x56,0x34,0x12,0xaf]
 860
 861 v_min_f32 v5, 0x3f717273, v2
 862 // CHECK: [0xff,0x04,0x0a,0x14,0x73,0x72,0x71,0x3f]
 863
 864 v_min_f32 v5, v1, v255
 865 // CHECK: [0x01,0xff,0x0b,0x14]
 866
 867 v_max_f32 v5, v1, v2
 868 // CHECK: [0x01,0x05,0x0a,0x16]
 869
 870 v_max_f32 v255, v1, v2
 871 // CHECK: [0x01,0x05,0xfe,0x17]
 872
 873 v_max_f32 v5, v255, v2
 874 // CHECK: [0xff,0x05,0x0a,0x16]
 875
 876 v_max_f32 v5, s1, v2
 877 // CHECK: [0x01,0x04,0x0a,0x16]
 878
 879 v_max_f32 v5, s101, v2
 880 // CHECK: [0x65,0x04,0x0a,0x16]
 881
 882 v_max_f32 v5, flat_scratch_lo, v2
 883 // CHECK: [0x66,0x04,0x0a,0x16]
 884
 885 v_max_f32 v5, flat_scratch_hi, v2
 886 // CHECK: [0x67,0x04,0x0a,0x16]
 887
 888 v_max_f32 v5, vcc_lo, v2
 889 // CHECK: [0x6a,0x04,0x0a,0x16]
 890
 891 v_max_f32 v5, vcc_hi, v2
 892 // CHECK: [0x6b,0x04,0x0a,0x16]
 893
 894 v_max_f32 v5, tba_lo, v2
 895 // CHECK: [0x6c,0x04,0x0a,0x16]
 896
 897 v_max_f32 v5, tba_hi, v2
 898 // CHECK: [0x6d,0x04,0x0a,0x16]
 899
 900 v_max_f32 v5, tma_lo, v2
 901 // CHECK: [0x6e,0x04,0x0a,0x16]
 902
 903 v_max_f32 v5, tma_hi, v2
 904 // CHECK: [0x6f,0x04,0x0a,0x16]
 905
 906 v_max_f32 v5, ttmp11, v2
 907 // CHECK: [0x7b,0x04,0x0a,0x16]
 908
 909 v_max_f32 v5, m0, v2
 910 // CHECK: [0x7c,0x04,0x0a,0x16]
 911
 912 v_max_f32 v5, exec_lo, v2
 913 // CHECK: [0x7e,0x04,0x0a,0x16]
 914
 915 v_max_f32 v5, exec_hi, v2
 916 // CHECK: [0x7f,0x04,0x0a,0x16]
 917
 918 v_max_f32 v5, 0, v2
 919 // CHECK: [0x80,0x04,0x0a,0x16]
 920
 921 v_max_f32 v5, -1, v2
 922 // CHECK: [0xc1,0x04,0x0a,0x16]
 923
 924 v_max_f32 v5, 0.5, v2
 925 // CHECK: [0xf0,0x04,0x0a,0x16]
 926
 927 v_max_f32 v5, -4.0, v2
 928 // CHECK: [0xf7,0x04,0x0a,0x16]
 929
 930 v_max_f32 v5, src_vccz, v2
 931 // CHECK: [0xfb,0x04,0x0a,0x16]
 932
 933 v_max_f32 v5, src_execz, v2
 934 // CHECK: [0xfc,0x04,0x0a,0x16]
 935
 936 v_max_f32 v5, src_scc, v2
 937 // CHECK: [0xfd,0x04,0x0a,0x16]
 938
 939 v_max_f32 v5, src_lds_direct, v2
 940 // CHECK: [0xfe,0x04,0x0a,0x16]
 941
 942 v_max_f32 v5, 0xaf123456, v2
 943 // CHECK: [0xff,0x04,0x0a,0x16,0x56,0x34,0x12,0xaf]
 944
 945 v_max_f32 v5, 0x3f717273, v2
 946 // CHECK: [0xff,0x04,0x0a,0x16,0x73,0x72,0x71,0x3f]
 947
 948 v_max_f32 v5, v1, v255
 949 // CHECK: [0x01,0xff,0x0b,0x16]
 950
 951 v_min_i32 v5, v1, v2
 952 // CHECK: [0x01,0x05,0x0a,0x18]
 953
 954 v_min_i32 v255, v1, v2
 955 // CHECK: [0x01,0x05,0xfe,0x19]
 956
 957 v_min_i32 v5, v255, v2
 958 // CHECK: [0xff,0x05,0x0a,0x18]
 959
 960 v_min_i32 v5, s1, v2
 961 // CHECK: [0x01,0x04,0x0a,0x18]
 962
 963 v_min_i32 v5, s101, v2
 964 // CHECK: [0x65,0x04,0x0a,0x18]
 965
 966 v_min_i32 v5, flat_scratch_lo, v2
 967 // CHECK: [0x66,0x04,0x0a,0x18]
 968
 969 v_min_i32 v5, flat_scratch_hi, v2
 970 // CHECK: [0x67,0x04,0x0a,0x18]
 971
 972 v_min_i32 v5, vcc_lo, v2
 973 // CHECK: [0x6a,0x04,0x0a,0x18]
 974
 975 v_min_i32 v5, vcc_hi, v2
 976 // CHECK: [0x6b,0x04,0x0a,0x18]
 977
 978 v_min_i32 v5, tba_lo, v2
 979 // CHECK: [0x6c,0x04,0x0a,0x18]
 980
 981 v_min_i32 v5, tba_hi, v2
 982 // CHECK: [0x6d,0x04,0x0a,0x18]
 983
 984 v_min_i32 v5, tma_lo, v2
 985 // CHECK: [0x6e,0x04,0x0a,0x18]
 986
 987 v_min_i32 v5, tma_hi, v2
 988 // CHECK: [0x6f,0x04,0x0a,0x18]
 989
 990 v_min_i32 v5, ttmp11, v2
 991 // CHECK: [0x7b,0x04,0x0a,0x18]
 992
 993 v_min_i32 v5, m0, v2
 994 // CHECK: [0x7c,0x04,0x0a,0x18]
 995
 996 v_min_i32 v5, exec_lo, v2
 997 // CHECK: [0x7e,0x04,0x0a,0x18]
 998
 999 v_min_i32 v5, exec_hi, v2
1000 // CHECK: [0x7f,0x04,0x0a,0x18]
1001
1002 v_min_i32 v5, 0, v2
1003 // CHECK: [0x80,0x04,0x0a,0x18]
1004
1005 v_min_i32 v5, -1, v2
1006 // CHECK: [0xc1,0x04,0x0a,0x18]
1007
1008 v_min_i32 v5, 0.5, v2
1009 // CHECK: [0xf0,0x04,0x0a,0x18]
1010
1011 v_min_i32 v5, -4.0, v2
1012 // CHECK: [0xf7,0x04,0x0a,0x18]
1013
1014 v_min_i32 v5, src_vccz, v2
1015 // CHECK: [0xfb,0x04,0x0a,0x18]
1016
1017 v_min_i32 v5, src_execz, v2
1018 // CHECK: [0xfc,0x04,0x0a,0x18]
1019
1020 v_min_i32 v5, src_scc, v2
1021 // CHECK: [0xfd,0x04,0x0a,0x18]
1022
1023 v_min_i32 v5, src_lds_direct, v2
1024 // CHECK: [0xfe,0x04,0x0a,0x18]
1025
1026 v_min_i32 v5, 0xaf123456, v2
1027 // CHECK: [0xff,0x04,0x0a,0x18,0x56,0x34,0x12,0xaf]
1028
1029 v_min_i32 v5, 0x3f717273, v2
1030 // CHECK: [0xff,0x04,0x0a,0x18,0x73,0x72,0x71,0x3f]
1031
1032 v_min_i32 v5, v1, v255
1033 // CHECK: [0x01,0xff,0x0b,0x18]
1034
1035 v_max_i32 v5, v1, v2
1036 // CHECK: [0x01,0x05,0x0a,0x1a]
1037
1038 v_max_i32 v255, v1, v2
1039 // CHECK: [0x01,0x05,0xfe,0x1b]
1040
1041 v_max_i32 v5, v255, v2
1042 // CHECK: [0xff,0x05,0x0a,0x1a]
1043
1044 v_max_i32 v5, s1, v2
1045 // CHECK: [0x01,0x04,0x0a,0x1a]
1046
1047 v_max_i32 v5, s101, v2
1048 // CHECK: [0x65,0x04,0x0a,0x1a]
1049
1050 v_max_i32 v5, flat_scratch_lo, v2
1051 // CHECK: [0x66,0x04,0x0a,0x1a]
1052
1053 v_max_i32 v5, flat_scratch_hi, v2
1054 // CHECK: [0x67,0x04,0x0a,0x1a]
1055
1056 v_max_i32 v5, vcc_lo, v2
1057 // CHECK: [0x6a,0x04,0x0a,0x1a]
1058
1059 v_max_i32 v5, vcc_hi, v2
1060 // CHECK: [0x6b,0x04,0x0a,0x1a]
1061
1062 v_max_i32 v5, tba_lo, v2
1063 // CHECK: [0x6c,0x04,0x0a,0x1a]
1064
1065 v_max_i32 v5, tba_hi, v2
1066 // CHECK: [0x6d,0x04,0x0a,0x1a]
1067
1068 v_max_i32 v5, tma_lo, v2
1069 // CHECK: [0x6e,0x04,0x0a,0x1a]
1070
1071 v_max_i32 v5, tma_hi, v2
1072 // CHECK: [0x6f,0x04,0x0a,0x1a]
1073
1074 v_max_i32 v5, ttmp11, v2
1075 // CHECK: [0x7b,0x04,0x0a,0x1a]
1076
1077 v_max_i32 v5, m0, v2
1078 // CHECK: [0x7c,0x04,0x0a,0x1a]
1079
1080 v_max_i32 v5, exec_lo, v2
1081 // CHECK: [0x7e,0x04,0x0a,0x1a]
1082
1083 v_max_i32 v5, exec_hi, v2
1084 // CHECK: [0x7f,0x04,0x0a,0x1a]
1085
1086 v_max_i32 v5, 0, v2
1087 // CHECK: [0x80,0x04,0x0a,0x1a]
1088
1089 v_max_i32 v5, -1, v2
1090 // CHECK: [0xc1,0x04,0x0a,0x1a]
1091
1092 v_max_i32 v5, 0.5, v2
1093 // CHECK: [0xf0,0x04,0x0a,0x1a]
1094
1095 v_max_i32 v5, -4.0, v2
1096 // CHECK: [0xf7,0x04,0x0a,0x1a]
1097
1098 v_max_i32 v5, src_vccz, v2
1099 // CHECK: [0xfb,0x04,0x0a,0x1a]
1100
1101 v_max_i32 v5, src_execz, v2
1102 // CHECK: [0xfc,0x04,0x0a,0x1a]
1103
1104 v_max_i32 v5, src_scc, v2
1105 // CHECK: [0xfd,0x04,0x0a,0x1a]
1106
1107 v_max_i32 v5, src_lds_direct, v2
1108 // CHECK: [0xfe,0x04,0x0a,0x1a]
1109
1110 v_max_i32 v5, 0xaf123456, v2
1111 // CHECK: [0xff,0x04,0x0a,0x1a,0x56,0x34,0x12,0xaf]
1112
1113 v_max_i32 v5, 0x3f717273, v2
1114 // CHECK: [0xff,0x04,0x0a,0x1a,0x73,0x72,0x71,0x3f]
1115
1116 v_max_i32 v5, v1, v255
1117 // CHECK: [0x01,0xff,0x0b,0x1a]
1118
1119 v_min_u32 v5, v1, v2
1120 // CHECK: [0x01,0x05,0x0a,0x1c]
1121
1122 v_min_u32 v255, v1, v2
1123 // CHECK: [0x01,0x05,0xfe,0x1d]
1124
1125 v_min_u32 v5, v255, v2
1126 // CHECK: [0xff,0x05,0x0a,0x1c]
1127
1128 v_min_u32 v5, s1, v2
1129 // CHECK: [0x01,0x04,0x0a,0x1c]
1130
1131 v_min_u32 v5, s101, v2
1132 // CHECK: [0x65,0x04,0x0a,0x1c]
1133
1134 v_min_u32 v5, flat_scratch_lo, v2
1135 // CHECK: [0x66,0x04,0x0a,0x1c]
1136
1137 v_min_u32 v5, flat_scratch_hi, v2
1138 // CHECK: [0x67,0x04,0x0a,0x1c]
1139
1140 v_min_u32 v5, vcc_lo, v2
1141 // CHECK: [0x6a,0x04,0x0a,0x1c]
1142
1143 v_min_u32 v5, vcc_hi, v2
1144 // CHECK: [0x6b,0x04,0x0a,0x1c]
1145
1146 v_min_u32 v5, tba_lo, v2
1147 // CHECK: [0x6c,0x04,0x0a,0x1c]
1148
1149 v_min_u32 v5, tba_hi, v2
1150 // CHECK: [0x6d,0x04,0x0a,0x1c]
1151
1152 v_min_u32 v5, tma_lo, v2
1153 // CHECK: [0x6e,0x04,0x0a,0x1c]
1154
1155 v_min_u32 v5, tma_hi, v2
1156 // CHECK: [0x6f,0x04,0x0a,0x1c]
1157
1158 v_min_u32 v5, ttmp11, v2
1159 // CHECK: [0x7b,0x04,0x0a,0x1c]
1160
1161 v_min_u32 v5, m0, v2
1162 // CHECK: [0x7c,0x04,0x0a,0x1c]
1163
1164 v_min_u32 v5, exec_lo, v2
1165 // CHECK: [0x7e,0x04,0x0a,0x1c]
1166
1167 v_min_u32 v5, exec_hi, v2
1168 // CHECK: [0x7f,0x04,0x0a,0x1c]
1169
1170 v_min_u32 v5, 0, v2
1171 // CHECK: [0x80,0x04,0x0a,0x1c]
1172
1173 v_min_u32 v5, -1, v2
1174 // CHECK: [0xc1,0x04,0x0a,0x1c]
1175
1176 v_min_u32 v5, 0.5, v2
1177 // CHECK: [0xf0,0x04,0x0a,0x1c]
1178
1179 v_min_u32 v5, -4.0, v2
1180 // CHECK: [0xf7,0x04,0x0a,0x1c]
1181
1182 v_min_u32 v5, src_vccz, v2
1183 // CHECK: [0xfb,0x04,0x0a,0x1c]
1184
1185 v_min_u32 v5, src_execz, v2
1186 // CHECK: [0xfc,0x04,0x0a,0x1c]
1187
1188 v_min_u32 v5, src_scc, v2
1189 // CHECK: [0xfd,0x04,0x0a,0x1c]
1190
1191 v_min_u32 v5, src_lds_direct, v2
1192 // CHECK: [0xfe,0x04,0x0a,0x1c]
1193
1194 v_min_u32 v5, 0xaf123456, v2
1195 // CHECK: [0xff,0x04,0x0a,0x1c,0x56,0x34,0x12,0xaf]
1196
1197 v_min_u32 v5, 0x3f717273, v2
1198 // CHECK: [0xff,0x04,0x0a,0x1c,0x73,0x72,0x71,0x3f]
1199
1200 v_min_u32 v5, v1, v255
1201 // CHECK: [0x01,0xff,0x0b,0x1c]
1202
1203 v_max_u32 v5, v1, v2
1204 // CHECK: [0x01,0x05,0x0a,0x1e]
1205
1206 v_max_u32 v255, v1, v2
1207 // CHECK: [0x01,0x05,0xfe,0x1f]
1208
1209 v_max_u32 v5, v255, v2
1210 // CHECK: [0xff,0x05,0x0a,0x1e]
1211
1212 v_max_u32 v5, s1, v2
1213 // CHECK: [0x01,0x04,0x0a,0x1e]
1214
1215 v_max_u32 v5, s101, v2
1216 // CHECK: [0x65,0x04,0x0a,0x1e]
1217
1218 v_max_u32 v5, flat_scratch_lo, v2
1219 // CHECK: [0x66,0x04,0x0a,0x1e]
1220
1221 v_max_u32 v5, flat_scratch_hi, v2
1222 // CHECK: [0x67,0x04,0x0a,0x1e]
1223
1224 v_max_u32 v5, vcc_lo, v2
1225 // CHECK: [0x6a,0x04,0x0a,0x1e]
1226
1227 v_max_u32 v5, vcc_hi, v2
1228 // CHECK: [0x6b,0x04,0x0a,0x1e]
1229
1230 v_max_u32 v5, tba_lo, v2
1231 // CHECK: [0x6c,0x04,0x0a,0x1e]
1232
1233 v_max_u32 v5, tba_hi, v2
1234 // CHECK: [0x6d,0x04,0x0a,0x1e]
1235
1236 v_max_u32 v5, tma_lo, v2
1237 // CHECK: [0x6e,0x04,0x0a,0x1e]
1238
1239 v_max_u32 v5, tma_hi, v2
1240 // CHECK: [0x6f,0x04,0x0a,0x1e]
1241
1242 v_max_u32 v5, ttmp11, v2
1243 // CHECK: [0x7b,0x04,0x0a,0x1e]
1244
1245 v_max_u32 v5, m0, v2
1246 // CHECK: [0x7c,0x04,0x0a,0x1e]
1247
1248 v_max_u32 v5, exec_lo, v2
1249 // CHECK: [0x7e,0x04,0x0a,0x1e]
1250
1251 v_max_u32 v5, exec_hi, v2
1252 // CHECK: [0x7f,0x04,0x0a,0x1e]
1253
1254 v_max_u32 v5, 0, v2
1255 // CHECK: [0x80,0x04,0x0a,0x1e]
1256
1257 v_max_u32 v5, -1, v2
1258 // CHECK: [0xc1,0x04,0x0a,0x1e]
1259
1260 v_max_u32 v5, 0.5, v2
1261 // CHECK: [0xf0,0x04,0x0a,0x1e]
1262
1263 v_max_u32 v5, -4.0, v2
1264 // CHECK: [0xf7,0x04,0x0a,0x1e]
1265
1266 v_max_u32 v5, src_vccz, v2
1267 // CHECK: [0xfb,0x04,0x0a,0x1e]
1268
1269 v_max_u32 v5, src_execz, v2
1270 // CHECK: [0xfc,0x04,0x0a,0x1e]
1271
1272 v_max_u32 v5, src_scc, v2
1273 // CHECK: [0xfd,0x04,0x0a,0x1e]
1274
1275 v_max_u32 v5, src_lds_direct, v2
1276 // CHECK: [0xfe,0x04,0x0a,0x1e]
1277
1278 v_max_u32 v5, 0xaf123456, v2
1279 // CHECK: [0xff,0x04,0x0a,0x1e,0x56,0x34,0x12,0xaf]
1280
1281 v_max_u32 v5, 0x3f717273, v2
1282 // CHECK: [0xff,0x04,0x0a,0x1e,0x73,0x72,0x71,0x3f]
1283
1284 v_max_u32 v5, v1, v255
1285 // CHECK: [0x01,0xff,0x0b,0x1e]
1286
1287 v_lshrrev_b32 v5, v1, v2
1288 // CHECK: [0x01,0x05,0x0a,0x20]
1289
1290 v_lshrrev_b32 v255, v1, v2
1291 // CHECK: [0x01,0x05,0xfe,0x21]
1292
1293 v_lshrrev_b32 v5, v255, v2
1294 // CHECK: [0xff,0x05,0x0a,0x20]
1295
1296 v_lshrrev_b32 v5, s1, v2
1297 // CHECK: [0x01,0x04,0x0a,0x20]
1298
1299 v_lshrrev_b32 v5, s101, v2
1300 // CHECK: [0x65,0x04,0x0a,0x20]
1301
1302 v_lshrrev_b32 v5, flat_scratch_lo, v2
1303 // CHECK: [0x66,0x04,0x0a,0x20]
1304
1305 v_lshrrev_b32 v5, flat_scratch_hi, v2
1306 // CHECK: [0x67,0x04,0x0a,0x20]
1307
1308 v_lshrrev_b32 v5, vcc_lo, v2
1309 // CHECK: [0x6a,0x04,0x0a,0x20]
1310
1311 v_lshrrev_b32 v5, vcc_hi, v2
1312 // CHECK: [0x6b,0x04,0x0a,0x20]
1313
1314 v_lshrrev_b32 v5, tba_lo, v2
1315 // CHECK: [0x6c,0x04,0x0a,0x20]
1316
1317 v_lshrrev_b32 v5, tba_hi, v2
1318 // CHECK: [0x6d,0x04,0x0a,0x20]
1319
1320 v_lshrrev_b32 v5, tma_lo, v2
1321 // CHECK: [0x6e,0x04,0x0a,0x20]
1322
1323 v_lshrrev_b32 v5, tma_hi, v2
1324 // CHECK: [0x6f,0x04,0x0a,0x20]
1325
1326 v_lshrrev_b32 v5, ttmp11, v2
1327 // CHECK: [0x7b,0x04,0x0a,0x20]
1328
1329 v_lshrrev_b32 v5, m0, v2
1330 // CHECK: [0x7c,0x04,0x0a,0x20]
1331
1332 v_lshrrev_b32 v5, exec_lo, v2
1333 // CHECK: [0x7e,0x04,0x0a,0x20]
1334
1335 v_lshrrev_b32 v5, exec_hi, v2
1336 // CHECK: [0x7f,0x04,0x0a,0x20]
1337
1338 v_lshrrev_b32 v5, 0, v2
1339 // CHECK: [0x80,0x04,0x0a,0x20]
1340
1341 v_lshrrev_b32 v5, -1, v2
1342 // CHECK: [0xc1,0x04,0x0a,0x20]
1343
1344 v_lshrrev_b32 v5, 0.5, v2
1345 // CHECK: [0xf0,0x04,0x0a,0x20]
1346
1347 v_lshrrev_b32 v5, -4.0, v2
1348 // CHECK: [0xf7,0x04,0x0a,0x20]
1349
1350 v_lshrrev_b32 v5, src_vccz, v2
1351 // CHECK: [0xfb,0x04,0x0a,0x20]
1352
1353 v_lshrrev_b32 v5, src_execz, v2
1354 // CHECK: [0xfc,0x04,0x0a,0x20]
1355
1356 v_lshrrev_b32 v5, src_scc, v2
1357 // CHECK: [0xfd,0x04,0x0a,0x20]
1358
1359 v_lshrrev_b32 v5, 0xaf123456, v2
1360 // CHECK: [0xff,0x04,0x0a,0x20,0x56,0x34,0x12,0xaf]
1361
1362 v_lshrrev_b32 v5, 0x3f717273, v2
1363 // CHECK: [0xff,0x04,0x0a,0x20,0x73,0x72,0x71,0x3f]
1364
1365 v_lshrrev_b32 v5, v1, v255
1366 // CHECK: [0x01,0xff,0x0b,0x20]
1367
1368 v_ashrrev_i32 v5, v1, v2
1369 // CHECK: [0x01,0x05,0x0a,0x22]
1370
1371 v_ashrrev_i32 v255, v1, v2
1372 // CHECK: [0x01,0x05,0xfe,0x23]
1373
1374 v_ashrrev_i32 v5, v255, v2
1375 // CHECK: [0xff,0x05,0x0a,0x22]
1376
1377 v_ashrrev_i32 v5, s1, v2
1378 // CHECK: [0x01,0x04,0x0a,0x22]
1379
1380 v_ashrrev_i32 v5, s101, v2
1381 // CHECK: [0x65,0x04,0x0a,0x22]
1382
1383 v_ashrrev_i32 v5, flat_scratch_lo, v2
1384 // CHECK: [0x66,0x04,0x0a,0x22]
1385
1386 v_ashrrev_i32 v5, flat_scratch_hi, v2
1387 // CHECK: [0x67,0x04,0x0a,0x22]
1388
1389 v_ashrrev_i32 v5, vcc_lo, v2
1390 // CHECK: [0x6a,0x04,0x0a,0x22]
1391
1392 v_ashrrev_i32 v5, vcc_hi, v2
1393 // CHECK: [0x6b,0x04,0x0a,0x22]
1394
1395 v_ashrrev_i32 v5, tba_lo, v2
1396 // CHECK: [0x6c,0x04,0x0a,0x22]
1397
1398 v_ashrrev_i32 v5, tba_hi, v2
1399 // CHECK: [0x6d,0x04,0x0a,0x22]
1400
1401 v_ashrrev_i32 v5, tma_lo, v2
1402 // CHECK: [0x6e,0x04,0x0a,0x22]
1403
1404 v_ashrrev_i32 v5, tma_hi, v2
1405 // CHECK: [0x6f,0x04,0x0a,0x22]
1406
1407 v_ashrrev_i32 v5, ttmp11, v2
1408 // CHECK: [0x7b,0x04,0x0a,0x22]
1409
1410 v_ashrrev_i32 v5, m0, v2
1411 // CHECK: [0x7c,0x04,0x0a,0x22]
1412
1413 v_ashrrev_i32 v5, exec_lo, v2
1414 // CHECK: [0x7e,0x04,0x0a,0x22]
1415
1416 v_ashrrev_i32 v5, exec_hi, v2
1417 // CHECK: [0x7f,0x04,0x0a,0x22]
1418
1419 v_ashrrev_i32 v5, 0, v2
1420 // CHECK: [0x80,0x04,0x0a,0x22]
1421
1422 v_ashrrev_i32 v5, -1, v2
1423 // CHECK: [0xc1,0x04,0x0a,0x22]
1424
1425 v_ashrrev_i32 v5, 0.5, v2
1426 // CHECK: [0xf0,0x04,0x0a,0x22]
1427
1428 v_ashrrev_i32 v5, -4.0, v2
1429 // CHECK: [0xf7,0x04,0x0a,0x22]
1430
1431 v_ashrrev_i32 v5, src_vccz, v2
1432 // CHECK: [0xfb,0x04,0x0a,0x22]
1433
1434 v_ashrrev_i32 v5, src_execz, v2
1435 // CHECK: [0xfc,0x04,0x0a,0x22]
1436
1437 v_ashrrev_i32 v5, src_scc, v2
1438 // CHECK: [0xfd,0x04,0x0a,0x22]
1439
1440 v_ashrrev_i32 v5, 0xaf123456, v2
1441 // CHECK: [0xff,0x04,0x0a,0x22,0x56,0x34,0x12,0xaf]
1442
1443 v_ashrrev_i32 v5, 0x3f717273, v2
1444 // CHECK: [0xff,0x04,0x0a,0x22,0x73,0x72,0x71,0x3f]
1445
1446 v_ashrrev_i32 v5, v1, v255
1447 // CHECK: [0x01,0xff,0x0b,0x22]
1448
1449 v_lshlrev_b32 v5, v1, v2
1450 // CHECK: [0x01,0x05,0x0a,0x24]
1451
1452 v_lshlrev_b32 v255, v1, v2
1453 // CHECK: [0x01,0x05,0xfe,0x25]
1454
1455 v_lshlrev_b32 v5, v255, v2
1456 // CHECK: [0xff,0x05,0x0a,0x24]
1457
1458 v_lshlrev_b32 v5, s1, v2
1459 // CHECK: [0x01,0x04,0x0a,0x24]
1460
1461 v_lshlrev_b32 v5, s101, v2
1462 // CHECK: [0x65,0x04,0x0a,0x24]
1463
1464 v_lshlrev_b32 v5, flat_scratch_lo, v2
1465 // CHECK: [0x66,0x04,0x0a,0x24]
1466
1467 v_lshlrev_b32 v5, flat_scratch_hi, v2
1468 // CHECK: [0x67,0x04,0x0a,0x24]
1469
1470 v_lshlrev_b32 v5, vcc_lo, v2
1471 // CHECK: [0x6a,0x04,0x0a,0x24]
1472
1473 v_lshlrev_b32 v5, vcc_hi, v2
1474 // CHECK: [0x6b,0x04,0x0a,0x24]
1475
1476 v_lshlrev_b32 v5, tba_lo, v2
1477 // CHECK: [0x6c,0x04,0x0a,0x24]
1478
1479 v_lshlrev_b32 v5, tba_hi, v2
1480 // CHECK: [0x6d,0x04,0x0a,0x24]
1481
1482 v_lshlrev_b32 v5, tma_lo, v2
1483 // CHECK: [0x6e,0x04,0x0a,0x24]
1484
1485 v_lshlrev_b32 v5, tma_hi, v2
1486 // CHECK: [0x6f,0x04,0x0a,0x24]
1487
1488 v_lshlrev_b32 v5, ttmp11, v2
1489 // CHECK: [0x7b,0x04,0x0a,0x24]
1490
1491 v_lshlrev_b32 v5, m0, v2
1492 // CHECK: [0x7c,0x04,0x0a,0x24]
1493
1494 v_lshlrev_b32 v5, exec_lo, v2
1495 // CHECK: [0x7e,0x04,0x0a,0x24]
1496
1497 v_lshlrev_b32 v5, exec_hi, v2
1498 // CHECK: [0x7f,0x04,0x0a,0x24]
1499
1500 v_lshlrev_b32 v5, 0, v2
1501 // CHECK: [0x80,0x04,0x0a,0x24]
1502
1503 v_lshlrev_b32 v5, -1, v2
1504 // CHECK: [0xc1,0x04,0x0a,0x24]
1505
1506 v_lshlrev_b32 v5, 0.5, v2
1507 // CHECK: [0xf0,0x04,0x0a,0x24]
1508
1509 v_lshlrev_b32 v5, -4.0, v2
1510 // CHECK: [0xf7,0x04,0x0a,0x24]
1511
1512 v_lshlrev_b32 v5, src_vccz, v2
1513 // CHECK: [0xfb,0x04,0x0a,0x24]
1514
1515 v_lshlrev_b32 v5, src_execz, v2
1516 // CHECK: [0xfc,0x04,0x0a,0x24]
1517
1518 v_lshlrev_b32 v5, src_scc, v2
1519 // CHECK: [0xfd,0x04,0x0a,0x24]
1520
1521 v_lshlrev_b32 v5, 0xaf123456, v2
1522 // CHECK: [0xff,0x04,0x0a,0x24,0x56,0x34,0x12,0xaf]
1523
1524 v_lshlrev_b32 v5, 0x3f717273, v2
1525 // CHECK: [0xff,0x04,0x0a,0x24,0x73,0x72,0x71,0x3f]
1526
1527 v_lshlrev_b32 v5, v1, v255
1528 // CHECK: [0x01,0xff,0x0b,0x24]
1529
1530 v_and_b32 v5, v1, v2
1531 // CHECK: [0x01,0x05,0x0a,0x26]
1532
1533 v_and_b32 v255, v1, v2
1534 // CHECK: [0x01,0x05,0xfe,0x27]
1535
1536 v_and_b32 v5, v255, v2
1537 // CHECK: [0xff,0x05,0x0a,0x26]
1538
1539 v_and_b32 v5, s1, v2
1540 // CHECK: [0x01,0x04,0x0a,0x26]
1541
1542 v_and_b32 v5, s101, v2
1543 // CHECK: [0x65,0x04,0x0a,0x26]
1544
1545 v_and_b32 v5, flat_scratch_lo, v2
1546 // CHECK: [0x66,0x04,0x0a,0x26]
1547
1548 v_and_b32 v5, flat_scratch_hi, v2
1549 // CHECK: [0x67,0x04,0x0a,0x26]
1550
1551 v_and_b32 v5, vcc_lo, v2
1552 // CHECK: [0x6a,0x04,0x0a,0x26]
1553
1554 v_and_b32 v5, vcc_hi, v2
1555 // CHECK: [0x6b,0x04,0x0a,0x26]
1556
1557 v_and_b32 v5, tba_lo, v2
1558 // CHECK: [0x6c,0x04,0x0a,0x26]
1559
1560 v_and_b32 v5, tba_hi, v2
1561 // CHECK: [0x6d,0x04,0x0a,0x26]
1562
1563 v_and_b32 v5, tma_lo, v2
1564 // CHECK: [0x6e,0x04,0x0a,0x26]
1565
1566 v_and_b32 v5, tma_hi, v2
1567 // CHECK: [0x6f,0x04,0x0a,0x26]
1568
1569 v_and_b32 v5, ttmp11, v2
1570 // CHECK: [0x7b,0x04,0x0a,0x26]
1571
1572 v_and_b32 v5, m0, v2
1573 // CHECK: [0x7c,0x04,0x0a,0x26]
1574
1575 v_and_b32 v5, exec_lo, v2
1576 // CHECK: [0x7e,0x04,0x0a,0x26]
1577
1578 v_and_b32 v5, exec_hi, v2
1579 // CHECK: [0x7f,0x04,0x0a,0x26]
1580
1581 v_and_b32 v5, 0, v2
1582 // CHECK: [0x80,0x04,0x0a,0x26]
1583
1584 v_and_b32 v5, -1, v2
1585 // CHECK: [0xc1,0x04,0x0a,0x26]
1586
1587 v_and_b32 v5, 0.5, v2
1588 // CHECK: [0xf0,0x04,0x0a,0x26]
1589
1590 v_and_b32 v5, -4.0, v2
1591 // CHECK: [0xf7,0x04,0x0a,0x26]
1592
1593 v_and_b32 v5, src_vccz, v2
1594 // CHECK: [0xfb,0x04,0x0a,0x26]
1595
1596 v_and_b32 v5, src_execz, v2
1597 // CHECK: [0xfc,0x04,0x0a,0x26]
1598
1599 v_and_b32 v5, src_scc, v2
1600 // CHECK: [0xfd,0x04,0x0a,0x26]
1601
1602 v_and_b32 v5, src_lds_direct, v2
1603 // CHECK: [0xfe,0x04,0x0a,0x26]
1604
1605 v_and_b32 v5, 0xaf123456, v2
1606 // CHECK: [0xff,0x04,0x0a,0x26,0x56,0x34,0x12,0xaf]
1607
1608 v_and_b32 v5, 0x3f717273, v2
1609 // CHECK: [0xff,0x04,0x0a,0x26,0x73,0x72,0x71,0x3f]
1610
1611 v_and_b32 v5, v1, v255
1612 // CHECK: [0x01,0xff,0x0b,0x26]
1613
1614 v_or_b32 v5, v1, v2
1615 // CHECK: [0x01,0x05,0x0a,0x28]
1616
1617 v_or_b32 v255, v1, v2
1618 // CHECK: [0x01,0x05,0xfe,0x29]
1619
1620 v_or_b32 v5, v255, v2
1621 // CHECK: [0xff,0x05,0x0a,0x28]
1622
1623 v_or_b32 v5, s1, v2
1624 // CHECK: [0x01,0x04,0x0a,0x28]
1625
1626 v_or_b32 v5, s101, v2
1627 // CHECK: [0x65,0x04,0x0a,0x28]
1628
1629 v_or_b32 v5, flat_scratch_lo, v2
1630 // CHECK: [0x66,0x04,0x0a,0x28]
1631
1632 v_or_b32 v5, flat_scratch_hi, v2
1633 // CHECK: [0x67,0x04,0x0a,0x28]
1634
1635 v_or_b32 v5, vcc_lo, v2
1636 // CHECK: [0x6a,0x04,0x0a,0x28]
1637
1638 v_or_b32 v5, vcc_hi, v2
1639 // CHECK: [0x6b,0x04,0x0a,0x28]
1640
1641 v_or_b32 v5, tba_lo, v2
1642 // CHECK: [0x6c,0x04,0x0a,0x28]
1643
1644 v_or_b32 v5, tba_hi, v2
1645 // CHECK: [0x6d,0x04,0x0a,0x28]
1646
1647 v_or_b32 v5, tma_lo, v2
1648 // CHECK: [0x6e,0x04,0x0a,0x28]
1649
1650 v_or_b32 v5, tma_hi, v2
1651 // CHECK: [0x6f,0x04,0x0a,0x28]
1652
1653 v_or_b32 v5, ttmp11, v2
1654 // CHECK: [0x7b,0x04,0x0a,0x28]
1655
1656 v_or_b32 v5, m0, v2
1657 // CHECK: [0x7c,0x04,0x0a,0x28]
1658
1659 v_or_b32 v5, exec_lo, v2
1660 // CHECK: [0x7e,0x04,0x0a,0x28]
1661
1662 v_or_b32 v5, exec_hi, v2
1663 // CHECK: [0x7f,0x04,0x0a,0x28]
1664
1665 v_or_b32 v5, 0, v2
1666 // CHECK: [0x80,0x04,0x0a,0x28]
1667
1668 v_or_b32 v5, -1, v2
1669 // CHECK: [0xc1,0x04,0x0a,0x28]
1670
1671 v_or_b32 v5, 0.5, v2
1672 // CHECK: [0xf0,0x04,0x0a,0x28]
1673
1674 v_or_b32 v5, -4.0, v2
1675 // CHECK: [0xf7,0x04,0x0a,0x28]
1676
1677 v_or_b32 v5, src_vccz, v2
1678 // CHECK: [0xfb,0x04,0x0a,0x28]
1679
1680 v_or_b32 v5, src_execz, v2
1681 // CHECK: [0xfc,0x04,0x0a,0x28]
1682
1683 v_or_b32 v5, src_scc, v2
1684 // CHECK: [0xfd,0x04,0x0a,0x28]
1685
1686 v_or_b32 v5, src_lds_direct, v2
1687 // CHECK: [0xfe,0x04,0x0a,0x28]
1688
1689 v_or_b32 v5, 0xaf123456, v2
1690 // CHECK: [0xff,0x04,0x0a,0x28,0x56,0x34,0x12,0xaf]
1691
1692 v_or_b32 v5, 0x3f717273, v2
1693 // CHECK: [0xff,0x04,0x0a,0x28,0x73,0x72,0x71,0x3f]
1694
1695 v_or_b32 v5, v1, v255
1696 // CHECK: [0x01,0xff,0x0b,0x28]
1697
1698 v_xor_b32 v5, v1, v2
1699 // CHECK: [0x01,0x05,0x0a,0x2a]
1700
1701 v_xor_b32 v255, v1, v2
1702 // CHECK: [0x01,0x05,0xfe,0x2b]
1703
1704 v_xor_b32 v5, v255, v2
1705 // CHECK: [0xff,0x05,0x0a,0x2a]
1706
1707 v_xor_b32 v5, s1, v2
1708 // CHECK: [0x01,0x04,0x0a,0x2a]
1709
1710 v_xor_b32 v5, s101, v2
1711 // CHECK: [0x65,0x04,0x0a,0x2a]
1712
1713 v_xor_b32 v5, flat_scratch_lo, v2
1714 // CHECK: [0x66,0x04,0x0a,0x2a]
1715
1716 v_xor_b32 v5, flat_scratch_hi, v2
1717 // CHECK: [0x67,0x04,0x0a,0x2a]
1718
1719 v_xor_b32 v5, vcc_lo, v2
1720 // CHECK: [0x6a,0x04,0x0a,0x2a]
1721
1722 v_xor_b32 v5, vcc_hi, v2
1723 // CHECK: [0x6b,0x04,0x0a,0x2a]
1724
1725 v_xor_b32 v5, tba_lo, v2
1726 // CHECK: [0x6c,0x04,0x0a,0x2a]
1727
1728 v_xor_b32 v5, tba_hi, v2
1729 // CHECK: [0x6d,0x04,0x0a,0x2a]
1730
1731 v_xor_b32 v5, tma_lo, v2
1732 // CHECK: [0x6e,0x04,0x0a,0x2a]
1733
1734 v_xor_b32 v5, tma_hi, v2
1735 // CHECK: [0x6f,0x04,0x0a,0x2a]
1736
1737 v_xor_b32 v5, ttmp11, v2
1738 // CHECK: [0x7b,0x04,0x0a,0x2a]
1739
1740 v_xor_b32 v5, m0, v2
1741 // CHECK: [0x7c,0x04,0x0a,0x2a]
1742
1743 v_xor_b32 v5, exec_lo, v2
1744 // CHECK: [0x7e,0x04,0x0a,0x2a]
1745
1746 v_xor_b32 v5, exec_hi, v2
1747 // CHECK: [0x7f,0x04,0x0a,0x2a]
1748
1749 v_xor_b32 v5, 0, v2
1750 // CHECK: [0x80,0x04,0x0a,0x2a]
1751
1752 v_xor_b32 v5, -1, v2
1753 // CHECK: [0xc1,0x04,0x0a,0x2a]
1754
1755 v_xor_b32 v5, 0.5, v2
1756 // CHECK: [0xf0,0x04,0x0a,0x2a]
1757
1758 v_xor_b32 v5, -4.0, v2
1759 // CHECK: [0xf7,0x04,0x0a,0x2a]
1760
1761 v_xor_b32 v5, src_vccz, v2
1762 // CHECK: [0xfb,0x04,0x0a,0x2a]
1763
1764 v_xor_b32 v5, src_execz, v2
1765 // CHECK: [0xfc,0x04,0x0a,0x2a]
1766
1767 v_xor_b32 v5, src_scc, v2
1768 // CHECK: [0xfd,0x04,0x0a,0x2a]
1769
1770 v_xor_b32 v5, src_lds_direct, v2
1771 // CHECK: [0xfe,0x04,0x0a,0x2a]
1772
1773 v_xor_b32 v5, 0xaf123456, v2
1774 // CHECK: [0xff,0x04,0x0a,0x2a,0x56,0x34,0x12,0xaf]
1775
1776 v_xor_b32 v5, 0x3f717273, v2
1777 // CHECK: [0xff,0x04,0x0a,0x2a,0x73,0x72,0x71,0x3f]
1778
1779 v_xor_b32 v5, v1, v255
1780 // CHECK: [0x01,0xff,0x0b,0x2a]
1781
1782 v_mac_f32 v5, v1, v2
1783 // CHECK: [0x01,0x05,0x0a,0x2c]
1784
1785 v_mac_f32 v255, v1, v2
1786 // CHECK: [0x01,0x05,0xfe,0x2d]
1787
1788 v_mac_f32 v5, v255, v2
1789 // CHECK: [0xff,0x05,0x0a,0x2c]
1790
1791 v_mac_f32 v5, s1, v2
1792 // CHECK: [0x01,0x04,0x0a,0x2c]
1793
1794 v_mac_f32 v5, s101, v2
1795 // CHECK: [0x65,0x04,0x0a,0x2c]
1796
1797 v_mac_f32 v5, flat_scratch_lo, v2
1798 // CHECK: [0x66,0x04,0x0a,0x2c]
1799
1800 v_mac_f32 v5, flat_scratch_hi, v2
1801 // CHECK: [0x67,0x04,0x0a,0x2c]
1802
1803 v_mac_f32 v5, vcc_lo, v2
1804 // CHECK: [0x6a,0x04,0x0a,0x2c]
1805
1806 v_mac_f32 v5, vcc_hi, v2
1807 // CHECK: [0x6b,0x04,0x0a,0x2c]
1808
1809 v_mac_f32 v5, tba_lo, v2
1810 // CHECK: [0x6c,0x04,0x0a,0x2c]
1811
1812 v_mac_f32 v5, tba_hi, v2
1813 // CHECK: [0x6d,0x04,0x0a,0x2c]
1814
1815 v_mac_f32 v5, tma_lo, v2
1816 // CHECK: [0x6e,0x04,0x0a,0x2c]
1817
1818 v_mac_f32 v5, tma_hi, v2
1819 // CHECK: [0x6f,0x04,0x0a,0x2c]
1820
1821 v_mac_f32 v5, ttmp11, v2
1822 // CHECK: [0x7b,0x04,0x0a,0x2c]
1823
1824 v_mac_f32 v5, m0, v2
1825 // CHECK: [0x7c,0x04,0x0a,0x2c]
1826
1827 v_mac_f32 v5, exec_lo, v2
1828 // CHECK: [0x7e,0x04,0x0a,0x2c]
1829
1830 v_mac_f32 v5, exec_hi, v2
1831 // CHECK: [0x7f,0x04,0x0a,0x2c]
1832
1833 v_mac_f32 v5, 0, v2
1834 // CHECK: [0x80,0x04,0x0a,0x2c]
1835
1836 v_mac_f32 v5, -1, v2
1837 // CHECK: [0xc1,0x04,0x0a,0x2c]
1838
1839 v_mac_f32 v5, 0.5, v2
1840 // CHECK: [0xf0,0x04,0x0a,0x2c]
1841
1842 v_mac_f32 v5, -4.0, v2
1843 // CHECK: [0xf7,0x04,0x0a,0x2c]
1844
1845 v_mac_f32 v5, src_vccz, v2
1846 // CHECK: [0xfb,0x04,0x0a,0x2c]
1847
1848 v_mac_f32 v5, src_execz, v2
1849 // CHECK: [0xfc,0x04,0x0a,0x2c]
1850
1851 v_mac_f32 v5, src_scc, v2
1852 // CHECK: [0xfd,0x04,0x0a,0x2c]
1853
1854 v_mac_f32 v5, src_lds_direct, v2
1855 // CHECK: [0xfe,0x04,0x0a,0x2c]
1856
1857 v_mac_f32 v5, 0xaf123456, v2
1858 // CHECK: [0xff,0x04,0x0a,0x2c,0x56,0x34,0x12,0xaf]
1859
1860 v_mac_f32 v5, 0x3f717273, v2
1861 // CHECK: [0xff,0x04,0x0a,0x2c,0x73,0x72,0x71,0x3f]
1862
1863 v_mac_f32 v5, v1, v255
1864 // CHECK: [0x01,0xff,0x0b,0x2c]
1865
1866 v_madmk_f32 v5, v1, 0x11213141, v3
1867 // CHECK: [0x01,0x07,0x0a,0x2e,0x41,0x31,0x21,0x11]
1868
1869 v_madmk_f32 v255, v1, 0x11213141, v3
1870 // CHECK: [0x01,0x07,0xfe,0x2f,0x41,0x31,0x21,0x11]
1871
1872 v_madmk_f32 v5, v255, 0x11213141, v3
1873 // CHECK: [0xff,0x07,0x0a,0x2e,0x41,0x31,0x21,0x11]
1874
1875 v_madmk_f32 v5, 0, 0x11213141, v3
1876 // CHECK: [0x80,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
1877
1878 v_madmk_f32 v5, -1, 0x11213141, v3
1879 // CHECK: [0xc1,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
1880
1881 v_madmk_f32 v5, 0.5, 0x11213141, v3
1882 // CHECK: [0xf0,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
1883
1884 v_madmk_f32 v5, -4.0, 0x11213141, v3
1885 // CHECK: [0xf7,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
1886
1887 v_madmk_f32 v5, src_lds_direct, 0x11213141, v3
1888 // CHECK: [0xfe,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
1889
1890 v_madmk_f32 v5, v1, 0xa1b1c1d1, v3
1891 // CHECK: [0x01,0x07,0x0a,0x2e,0xd1,0xc1,0xb1,0xa1]
1892
1893 v_madmk_f32 v5, v1, 0x11213141, v255
1894 // CHECK: [0x01,0xff,0x0b,0x2e,0x41,0x31,0x21,0x11]
1895
1896 v_madak_f32 v5, v1, v2, 0x11213141
1897 // CHECK: [0x01,0x05,0x0a,0x30,0x41,0x31,0x21,0x11]
1898
1899 v_madak_f32 v255, v1, v2, 0x11213141
1900 // CHECK: [0x01,0x05,0xfe,0x31,0x41,0x31,0x21,0x11]
1901
1902 v_madak_f32 v5, v255, v2, 0x11213141
1903 // CHECK: [0xff,0x05,0x0a,0x30,0x41,0x31,0x21,0x11]
1904
1905 v_madak_f32 v5, 0, v2, 0x11213141
1906 // CHECK: [0x80,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
1907
1908 v_madak_f32 v5, -1, v2, 0x11213141
1909 // CHECK: [0xc1,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
1910
1911 v_madak_f32 v5, 0.5, v2, 0x11213141
1912 // CHECK: [0xf0,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
1913
1914 v_madak_f32 v5, -4.0, v2, 0x11213141
1915 // CHECK: [0xf7,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
1916
1917 v_madak_f32 v5, src_lds_direct, v2, 0x11213141
1918 // CHECK: [0xfe,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
1919
1920 v_madak_f32 v5, v1, v255, 0x11213141
1921 // CHECK: [0x01,0xff,0x0b,0x30,0x41,0x31,0x21,0x11]
1922
1923 v_madak_f32 v5, v1, v2, 0xa1b1c1d1
1924 // CHECK: [0x01,0x05,0x0a,0x30,0xd1,0xc1,0xb1,0xa1]
1925
1926 v_add_u32 v5, vcc, v1, v2
1927 // CHECK: [0x01,0x05,0x0a,0x32]
1928
1929 v_add_u32 v255, vcc, v1, v2
1930 // CHECK: [0x01,0x05,0xfe,0x33]
1931
1932 v_add_u32 v5, vcc, v255, v2
1933 // CHECK: [0xff,0x05,0x0a,0x32]
1934
1935 v_add_u32 v5, vcc, s1, v2
1936 // CHECK: [0x01,0x04,0x0a,0x32]
1937
1938 v_add_u32 v5, vcc, s101, v2
1939 // CHECK: [0x65,0x04,0x0a,0x32]
1940
1941 v_add_u32 v5, vcc, flat_scratch_lo, v2
1942 // CHECK: [0x66,0x04,0x0a,0x32]
1943
1944 v_add_u32 v5, vcc, flat_scratch_hi, v2
1945 // CHECK: [0x67,0x04,0x0a,0x32]
1946
1947 v_add_u32 v5, vcc, vcc_lo, v2
1948 // CHECK: [0x6a,0x04,0x0a,0x32]
1949
1950 v_add_u32 v5, vcc, vcc_hi, v2
1951 // CHECK: [0x6b,0x04,0x0a,0x32]
1952
1953 v_add_u32 v5, vcc, tba_lo, v2
1954 // CHECK: [0x6c,0x04,0x0a,0x32]
1955
1956 v_add_u32 v5, vcc, tba_hi, v2
1957 // CHECK: [0x6d,0x04,0x0a,0x32]
1958
1959 v_add_u32 v5, vcc, tma_lo, v2
1960 // CHECK: [0x6e,0x04,0x0a,0x32]
1961
1962 v_add_u32 v5, vcc, tma_hi, v2
1963 // CHECK: [0x6f,0x04,0x0a,0x32]
1964
1965 v_add_u32 v5, vcc, ttmp11, v2
1966 // CHECK: [0x7b,0x04,0x0a,0x32]
1967
1968 v_add_u32 v5, vcc, m0, v2
1969 // CHECK: [0x7c,0x04,0x0a,0x32]
1970
1971 v_add_u32 v5, vcc, exec_lo, v2
1972 // CHECK: [0x7e,0x04,0x0a,0x32]
1973
1974 v_add_u32 v5, vcc, exec_hi, v2
1975 // CHECK: [0x7f,0x04,0x0a,0x32]
1976
1977 v_add_u32 v5, vcc, 0, v2
1978 // CHECK: [0x80,0x04,0x0a,0x32]
1979
1980 v_add_u32 v5, vcc, -1, v2
1981 // CHECK: [0xc1,0x04,0x0a,0x32]
1982
1983 v_add_u32 v5, vcc, 0.5, v2
1984 // CHECK: [0xf0,0x04,0x0a,0x32]
1985
1986 v_add_u32 v5, vcc, -4.0, v2
1987 // CHECK: [0xf7,0x04,0x0a,0x32]
1988
1989 v_add_u32 v5, vcc, src_vccz, v2
1990 // CHECK: [0xfb,0x04,0x0a,0x32]
1991
1992 v_add_u32 v5, vcc, src_execz, v2
1993 // CHECK: [0xfc,0x04,0x0a,0x32]
1994
1995 v_add_u32 v5, vcc, src_scc, v2
1996 // CHECK: [0xfd,0x04,0x0a,0x32]
1997
1998 v_add_u32 v5, vcc, src_lds_direct, v2
1999 // CHECK: [0xfe,0x04,0x0a,0x32]
2000
2001 v_add_u32 v5, vcc, 0xaf123456, v2
2002 // CHECK: [0xff,0x04,0x0a,0x32,0x56,0x34,0x12,0xaf]
2003
2004 v_add_u32 v5, vcc, 0x3f717273, v2
2005 // CHECK: [0xff,0x04,0x0a,0x32,0x73,0x72,0x71,0x3f]
2006
2007 v_add_u32 v5, vcc, v1, v255
2008 // CHECK: [0x01,0xff,0x0b,0x32]
2009
2010 v_sub_u32 v5, vcc, v1, v2
2011 // CHECK: [0x01,0x05,0x0a,0x34]
2012
2013 v_sub_u32 v255, vcc, v1, v2
2014 // CHECK: [0x01,0x05,0xfe,0x35]
2015
2016 v_sub_u32 v5, vcc, v255, v2
2017 // CHECK: [0xff,0x05,0x0a,0x34]
2018
2019 v_sub_u32 v5, vcc, s1, v2
2020 // CHECK: [0x01,0x04,0x0a,0x34]
2021
2022 v_sub_u32 v5, vcc, s101, v2
2023 // CHECK: [0x65,0x04,0x0a,0x34]
2024
2025 v_sub_u32 v5, vcc, flat_scratch_lo, v2
2026 // CHECK: [0x66,0x04,0x0a,0x34]
2027
2028 v_sub_u32 v5, vcc, flat_scratch_hi, v2
2029 // CHECK: [0x67,0x04,0x0a,0x34]
2030
2031 v_sub_u32 v5, vcc, vcc_lo, v2
2032 // CHECK: [0x6a,0x04,0x0a,0x34]
2033
2034 v_sub_u32 v5, vcc, vcc_hi, v2
2035 // CHECK: [0x6b,0x04,0x0a,0x34]
2036
2037 v_sub_u32 v5, vcc, tba_lo, v2
2038 // CHECK: [0x6c,0x04,0x0a,0x34]
2039
2040 v_sub_u32 v5, vcc, tba_hi, v2
2041 // CHECK: [0x6d,0x04,0x0a,0x34]
2042
2043 v_sub_u32 v5, vcc, tma_lo, v2
2044 // CHECK: [0x6e,0x04,0x0a,0x34]
2045
2046 v_sub_u32 v5, vcc, tma_hi, v2
2047 // CHECK: [0x6f,0x04,0x0a,0x34]
2048
2049 v_sub_u32 v5, vcc, ttmp11, v2
2050 // CHECK: [0x7b,0x04,0x0a,0x34]
2051
2052 v_sub_u32 v5, vcc, m0, v2
2053 // CHECK: [0x7c,0x04,0x0a,0x34]
2054
2055 v_sub_u32 v5, vcc, exec_lo, v2
2056 // CHECK: [0x7e,0x04,0x0a,0x34]
2057
2058 v_sub_u32 v5, vcc, exec_hi, v2
2059 // CHECK: [0x7f,0x04,0x0a,0x34]
2060
2061 v_sub_u32 v5, vcc, 0, v2
2062 // CHECK: [0x80,0x04,0x0a,0x34]
2063
2064 v_sub_u32 v5, vcc, -1, v2
2065 // CHECK: [0xc1,0x04,0x0a,0x34]
2066
2067 v_sub_u32 v5, vcc, 0.5, v2
2068 // CHECK: [0xf0,0x04,0x0a,0x34]
2069
2070 v_sub_u32 v5, vcc, -4.0, v2
2071 // CHECK: [0xf7,0x04,0x0a,0x34]
2072
2073 v_sub_u32 v5, vcc, src_vccz, v2
2074 // CHECK: [0xfb,0x04,0x0a,0x34]
2075
2076 v_sub_u32 v5, vcc, src_execz, v2
2077 // CHECK: [0xfc,0x04,0x0a,0x34]
2078
2079 v_sub_u32 v5, vcc, src_scc, v2
2080 // CHECK: [0xfd,0x04,0x0a,0x34]
2081
2082 v_sub_u32 v5, vcc, src_lds_direct, v2
2083 // CHECK: [0xfe,0x04,0x0a,0x34]
2084
2085 v_sub_u32 v5, vcc, 0xaf123456, v2
2086 // CHECK: [0xff,0x04,0x0a,0x34,0x56,0x34,0x12,0xaf]
2087
2088 v_sub_u32 v5, vcc, 0x3f717273, v2
2089 // CHECK: [0xff,0x04,0x0a,0x34,0x73,0x72,0x71,0x3f]
2090
2091 v_sub_u32 v5, vcc, v1, v255
2092 // CHECK: [0x01,0xff,0x0b,0x34]
2093
2094 v_subrev_u32 v5, vcc, v1, v2
2095 // CHECK: [0x01,0x05,0x0a,0x36]
2096
2097 v_subrev_u32 v255, vcc, v1, v2
2098 // CHECK: [0x01,0x05,0xfe,0x37]
2099
2100 v_subrev_u32 v5, vcc, v255, v2
2101 // CHECK: [0xff,0x05,0x0a,0x36]
2102
2103 v_subrev_u32 v5, vcc, s1, v2
2104 // CHECK: [0x01,0x04,0x0a,0x36]
2105
2106 v_subrev_u32 v5, vcc, s101, v2
2107 // CHECK: [0x65,0x04,0x0a,0x36]
2108
2109 v_subrev_u32 v5, vcc, flat_scratch_lo, v2
2110 // CHECK: [0x66,0x04,0x0a,0x36]
2111
2112 v_subrev_u32 v5, vcc, flat_scratch_hi, v2
2113 // CHECK: [0x67,0x04,0x0a,0x36]
2114
2115 v_subrev_u32 v5, vcc, vcc_lo, v2
2116 // CHECK: [0x6a,0x04,0x0a,0x36]
2117
2118 v_subrev_u32 v5, vcc, vcc_hi, v2
2119 // CHECK: [0x6b,0x04,0x0a,0x36]
2120
2121 v_subrev_u32 v5, vcc, tba_lo, v2
2122 // CHECK: [0x6c,0x04,0x0a,0x36]
2123
2124 v_subrev_u32 v5, vcc, tba_hi, v2
2125 // CHECK: [0x6d,0x04,0x0a,0x36]
2126
2127 v_subrev_u32 v5, vcc, tma_lo, v2
2128 // CHECK: [0x6e,0x04,0x0a,0x36]
2129
2130 v_subrev_u32 v5, vcc, tma_hi, v2
2131 // CHECK: [0x6f,0x04,0x0a,0x36]
2132
2133 v_subrev_u32 v5, vcc, ttmp11, v2
2134 // CHECK: [0x7b,0x04,0x0a,0x36]
2135
2136 v_subrev_u32 v5, vcc, m0, v2
2137 // CHECK: [0x7c,0x04,0x0a,0x36]
2138
2139 v_subrev_u32 v5, vcc, exec_lo, v2
2140 // CHECK: [0x7e,0x04,0x0a,0x36]
2141
2142 v_subrev_u32 v5, vcc, exec_hi, v2
2143 // CHECK: [0x7f,0x04,0x0a,0x36]
2144
2145 v_subrev_u32 v5, vcc, 0, v2
2146 // CHECK: [0x80,0x04,0x0a,0x36]
2147
2148 v_subrev_u32 v5, vcc, -1, v2
2149 // CHECK: [0xc1,0x04,0x0a,0x36]
2150
2151 v_subrev_u32 v5, vcc, 0.5, v2
2152 // CHECK: [0xf0,0x04,0x0a,0x36]
2153
2154 v_subrev_u32 v5, vcc, -4.0, v2
2155 // CHECK: [0xf7,0x04,0x0a,0x36]
2156
2157 v_subrev_u32 v5, vcc, src_vccz, v2
2158 // CHECK: [0xfb,0x04,0x0a,0x36]
2159
2160 v_subrev_u32 v5, vcc, src_execz, v2
2161 // CHECK: [0xfc,0x04,0x0a,0x36]
2162
2163 v_subrev_u32 v5, vcc, src_scc, v2
2164 // CHECK: [0xfd,0x04,0x0a,0x36]
2165
2166 v_subrev_u32 v5, vcc, 0xaf123456, v2
2167 // CHECK: [0xff,0x04,0x0a,0x36,0x56,0x34,0x12,0xaf]
2168
2169 v_subrev_u32 v5, vcc, 0x3f717273, v2
2170 // CHECK: [0xff,0x04,0x0a,0x36,0x73,0x72,0x71,0x3f]
2171
2172 v_subrev_u32 v5, vcc, v1, v255
2173 // CHECK: [0x01,0xff,0x0b,0x36]
2174
2175 v_addc_u32 v5, vcc, v1, v2, vcc
2176 // CHECK: [0x01,0x05,0x0a,0x38]
2177
2178 v_addc_u32 v255, vcc, v1, v2, vcc
2179 // CHECK: [0x01,0x05,0xfe,0x39]
2180
2181 v_addc_u32 v5, vcc, v255, v2, vcc
2182 // CHECK: [0xff,0x05,0x0a,0x38]
2183
2184 v_addc_u32 v5, vcc, 0, v2, vcc
2185 // CHECK: [0x80,0x04,0x0a,0x38]
2186
2187 v_addc_u32 v5, vcc, -1, v2, vcc
2188 // CHECK: [0xc1,0x04,0x0a,0x38]
2189
2190 v_addc_u32 v5, vcc, 0.5, v2, vcc
2191 // CHECK: [0xf0,0x04,0x0a,0x38]
2192
2193 v_addc_u32 v5, vcc, -4.0, v2, vcc
2194 // CHECK: [0xf7,0x04,0x0a,0x38]
2195
2196 v_addc_u32 v5, vcc, src_lds_direct, v2, vcc
2197 // CHECK: [0xfe,0x04,0x0a,0x38]
2198
2199 v_addc_u32 v5, vcc, v1, v255, vcc
2200 // CHECK: [0x01,0xff,0x0b,0x38]
2201
2202 v_subb_u32 v5, vcc, v1, v2, vcc
2203 // CHECK: [0x01,0x05,0x0a,0x3a]
2204
2205 v_subb_u32 v255, vcc, v1, v2, vcc
2206 // CHECK: [0x01,0x05,0xfe,0x3b]
2207
2208 v_subb_u32 v5, vcc, v255, v2, vcc
2209 // CHECK: [0xff,0x05,0x0a,0x3a]
2210
2211 v_subb_u32 v5, vcc, 0, v2, vcc
2212 // CHECK: [0x80,0x04,0x0a,0x3a]
2213
2214 v_subb_u32 v5, vcc, -1, v2, vcc
2215 // CHECK: [0xc1,0x04,0x0a,0x3a]
2216
2217 v_subb_u32 v5, vcc, 0.5, v2, vcc
2218 // CHECK: [0xf0,0x04,0x0a,0x3a]
2219
2220 v_subb_u32 v5, vcc, -4.0, v2, vcc
2221 // CHECK: [0xf7,0x04,0x0a,0x3a]
2222
2223 v_subb_u32 v5, vcc, src_lds_direct, v2, vcc
2224 // CHECK: [0xfe,0x04,0x0a,0x3a]
2225
2226 v_subb_u32 v5, vcc, v1, v255, vcc
2227 // CHECK: [0x01,0xff,0x0b,0x3a]
2228
2229 v_subbrev_u32 v5, vcc, v1, v2, vcc
2230 // CHECK: [0x01,0x05,0x0a,0x3c]
2231
2232 v_subbrev_u32 v255, vcc, v1, v2, vcc
2233 // CHECK: [0x01,0x05,0xfe,0x3d]
2234
2235 v_subbrev_u32 v5, vcc, v255, v2, vcc
2236 // CHECK: [0xff,0x05,0x0a,0x3c]
2237
2238 v_subbrev_u32 v5, vcc, 0, v2, vcc
2239 // CHECK: [0x80,0x04,0x0a,0x3c]
2240
2241 v_subbrev_u32 v5, vcc, -1, v2, vcc
2242 // CHECK: [0xc1,0x04,0x0a,0x3c]
2243
2244 v_subbrev_u32 v5, vcc, 0.5, v2, vcc
2245 // CHECK: [0xf0,0x04,0x0a,0x3c]
2246
2247 v_subbrev_u32 v5, vcc, -4.0, v2, vcc
2248 // CHECK: [0xf7,0x04,0x0a,0x3c]
2249
2250 v_subbrev_u32 v5, vcc, v1, v255, vcc
2251 // CHECK: [0x01,0xff,0x0b,0x3c]
2252
2253 v_add_f16 v5, v1, v2
2254 // CHECK: [0x01,0x05,0x0a,0x3e]
2255
2256 v_add_f16 v255, v1, v2
2257 // CHECK: [0x01,0x05,0xfe,0x3f]
2258
2259 v_add_f16 v5, v255, v2
2260 // CHECK: [0xff,0x05,0x0a,0x3e]
2261
2262 v_add_f16 v5, s1, v2
2263 // CHECK: [0x01,0x04,0x0a,0x3e]
2264
2265 v_add_f16 v5, s101, v2
2266 // CHECK: [0x65,0x04,0x0a,0x3e]
2267
2268 v_add_f16 v5, flat_scratch_lo, v2
2269 // CHECK: [0x66,0x04,0x0a,0x3e]
2270
2271 v_add_f16 v5, flat_scratch_hi, v2
2272 // CHECK: [0x67,0x04,0x0a,0x3e]
2273
2274 v_add_f16 v5, vcc_lo, v2
2275 // CHECK: [0x6a,0x04,0x0a,0x3e]
2276
2277 v_add_f16 v5, vcc_hi, v2
2278 // CHECK: [0x6b,0x04,0x0a,0x3e]
2279
2280 v_add_f16 v5, tba_lo, v2
2281 // CHECK: [0x6c,0x04,0x0a,0x3e]
2282
2283 v_add_f16 v5, tba_hi, v2
2284 // CHECK: [0x6d,0x04,0x0a,0x3e]
2285
2286 v_add_f16 v5, tma_lo, v2
2287 // CHECK: [0x6e,0x04,0x0a,0x3e]
2288
2289 v_add_f16 v5, tma_hi, v2
2290 // CHECK: [0x6f,0x04,0x0a,0x3e]
2291
2292 v_add_f16 v5, ttmp11, v2
2293 // CHECK: [0x7b,0x04,0x0a,0x3e]
2294
2295 v_add_f16 v5, m0, v2
2296 // CHECK: [0x7c,0x04,0x0a,0x3e]
2297
2298 v_add_f16 v5, exec_lo, v2
2299 // CHECK: [0x7e,0x04,0x0a,0x3e]
2300
2301 v_add_f16 v5, exec_hi, v2
2302 // CHECK: [0x7f,0x04,0x0a,0x3e]
2303
2304 v_add_f16 v5, 0, v2
2305 // CHECK: [0x80,0x04,0x0a,0x3e]
2306
2307 v_add_f16 v5, -1, v2
2308 // CHECK: [0xc1,0x04,0x0a,0x3e]
2309
2310 v_add_f16 v5, 0.5, v2
2311 // CHECK: [0xf0,0x04,0x0a,0x3e]
2312
2313 v_add_f16 v5, -4.0, v2
2314 // CHECK: [0xf7,0x04,0x0a,0x3e]
2315
2316 v_add_f16 v5, src_vccz, v2
2317 // CHECK: [0xfb,0x04,0x0a,0x3e]
2318
2319 v_add_f16 v5, src_execz, v2
2320 // CHECK: [0xfc,0x04,0x0a,0x3e]
2321
2322 v_add_f16 v5, src_scc, v2
2323 // CHECK: [0xfd,0x04,0x0a,0x3e]
2324
2325 v_add_f16 v5, src_lds_direct, v2
2326 // CHECK: [0xfe,0x04,0x0a,0x3e]
2327
2328 v_add_f16 v5, 0xfe0b, v2
2329 // CHECK: [0xff,0x04,0x0a,0x3e,0x0b,0xfe,0x00,0x00]
2330
2331 v_add_f16 v5, 0x3456, v2
2332 // CHECK: [0xff,0x04,0x0a,0x3e,0x56,0x34,0x00,0x00]
2333
2334 v_add_f16 v5, v1, v255
2335 // CHECK: [0x01,0xff,0x0b,0x3e]
2336
2337 v_sub_f16 v5, v1, v2
2338 // CHECK: [0x01,0x05,0x0a,0x40]
2339
2340 v_sub_f16 v255, v1, v2
2341 // CHECK: [0x01,0x05,0xfe,0x41]
2342
2343 v_sub_f16 v5, v255, v2
2344 // CHECK: [0xff,0x05,0x0a,0x40]
2345
2346 v_sub_f16 v5, s1, v2
2347 // CHECK: [0x01,0x04,0x0a,0x40]
2348
2349 v_sub_f16 v5, s101, v2
2350 // CHECK: [0x65,0x04,0x0a,0x40]
2351
2352 v_sub_f16 v5, flat_scratch_lo, v2
2353 // CHECK: [0x66,0x04,0x0a,0x40]
2354
2355 v_sub_f16 v5, flat_scratch_hi, v2
2356 // CHECK: [0x67,0x04,0x0a,0x40]
2357
2358 v_sub_f16 v5, vcc_lo, v2
2359 // CHECK: [0x6a,0x04,0x0a,0x40]
2360
2361 v_sub_f16 v5, vcc_hi, v2
2362 // CHECK: [0x6b,0x04,0x0a,0x40]
2363
2364 v_sub_f16 v5, tba_lo, v2
2365 // CHECK: [0x6c,0x04,0x0a,0x40]
2366
2367 v_sub_f16 v5, tba_hi, v2
2368 // CHECK: [0x6d,0x04,0x0a,0x40]
2369
2370 v_sub_f16 v5, tma_lo, v2
2371 // CHECK: [0x6e,0x04,0x0a,0x40]
2372
2373 v_sub_f16 v5, tma_hi, v2
2374 // CHECK: [0x6f,0x04,0x0a,0x40]
2375
2376 v_sub_f16 v5, ttmp11, v2
2377 // CHECK: [0x7b,0x04,0x0a,0x40]
2378
2379 v_sub_f16 v5, m0, v2
2380 // CHECK: [0x7c,0x04,0x0a,0x40]
2381
2382 v_sub_f16 v5, exec_lo, v2
2383 // CHECK: [0x7e,0x04,0x0a,0x40]
2384
2385 v_sub_f16 v5, exec_hi, v2
2386 // CHECK: [0x7f,0x04,0x0a,0x40]
2387
2388 v_sub_f16 v5, 0, v2
2389 // CHECK: [0x80,0x04,0x0a,0x40]
2390
2391 v_sub_f16 v5, -1, v2
2392 // CHECK: [0xc1,0x04,0x0a,0x40]
2393
2394 v_sub_f16 v5, 0.5, v2
2395 // CHECK: [0xf0,0x04,0x0a,0x40]
2396
2397 v_sub_f16 v5, -4.0, v2
2398 // CHECK: [0xf7,0x04,0x0a,0x40]
2399
2400 v_sub_f16 v5, src_vccz, v2
2401 // CHECK: [0xfb,0x04,0x0a,0x40]
2402
2403 v_sub_f16 v5, src_execz, v2
2404 // CHECK: [0xfc,0x04,0x0a,0x40]
2405
2406 v_sub_f16 v5, src_scc, v2
2407 // CHECK: [0xfd,0x04,0x0a,0x40]
2408
2409 v_sub_f16 v5, src_lds_direct, v2
2410 // CHECK: [0xfe,0x04,0x0a,0x40]
2411
2412 v_sub_f16 v5, 0xfe0b, v2
2413 // CHECK: [0xff,0x04,0x0a,0x40,0x0b,0xfe,0x00,0x00]
2414
2415 v_sub_f16 v5, 0x3456, v2
2416 // CHECK: [0xff,0x04,0x0a,0x40,0x56,0x34,0x00,0x00]
2417
2418 v_sub_f16 v5, v1, v255
2419 // CHECK: [0x01,0xff,0x0b,0x40]
2420
2421 v_subrev_f16 v5, v1, v2
2422 // CHECK: [0x01,0x05,0x0a,0x42]
2423
2424 v_subrev_f16 v255, v1, v2
2425 // CHECK: [0x01,0x05,0xfe,0x43]
2426
2427 v_subrev_f16 v5, v255, v2
2428 // CHECK: [0xff,0x05,0x0a,0x42]
2429
2430 v_subrev_f16 v5, s1, v2
2431 // CHECK: [0x01,0x04,0x0a,0x42]
2432
2433 v_subrev_f16 v5, s101, v2
2434 // CHECK: [0x65,0x04,0x0a,0x42]
2435
2436 v_subrev_f16 v5, flat_scratch_lo, v2
2437 // CHECK: [0x66,0x04,0x0a,0x42]
2438
2439 v_subrev_f16 v5, flat_scratch_hi, v2
2440 // CHECK: [0x67,0x04,0x0a,0x42]
2441
2442 v_subrev_f16 v5, vcc_lo, v2
2443 // CHECK: [0x6a,0x04,0x0a,0x42]
2444
2445 v_subrev_f16 v5, vcc_hi, v2
2446 // CHECK: [0x6b,0x04,0x0a,0x42]
2447
2448 v_subrev_f16 v5, tba_lo, v2
2449 // CHECK: [0x6c,0x04,0x0a,0x42]
2450
2451 v_subrev_f16 v5, tba_hi, v2
2452 // CHECK: [0x6d,0x04,0x0a,0x42]
2453
2454 v_subrev_f16 v5, tma_lo, v2
2455 // CHECK: [0x6e,0x04,0x0a,0x42]
2456
2457 v_subrev_f16 v5, tma_hi, v2
2458 // CHECK: [0x6f,0x04,0x0a,0x42]
2459
2460 v_subrev_f16 v5, ttmp11, v2
2461 // CHECK: [0x7b,0x04,0x0a,0x42]
2462
2463 v_subrev_f16 v5, m0, v2
2464 // CHECK: [0x7c,0x04,0x0a,0x42]
2465
2466 v_subrev_f16 v5, exec_lo, v2
2467 // CHECK: [0x7e,0x04,0x0a,0x42]
2468
2469 v_subrev_f16 v5, exec_hi, v2
2470 // CHECK: [0x7f,0x04,0x0a,0x42]
2471
2472 v_subrev_f16 v5, 0, v2
2473 // CHECK: [0x80,0x04,0x0a,0x42]
2474
2475 v_subrev_f16 v5, -1, v2
2476 // CHECK: [0xc1,0x04,0x0a,0x42]
2477
2478 v_subrev_f16 v5, 0.5, v2
2479 // CHECK: [0xf0,0x04,0x0a,0x42]
2480
2481 v_subrev_f16 v5, -4.0, v2
2482 // CHECK: [0xf7,0x04,0x0a,0x42]
2483
2484 v_subrev_f16 v5, src_vccz, v2
2485 // CHECK: [0xfb,0x04,0x0a,0x42]
2486
2487 v_subrev_f16 v5, src_execz, v2
2488 // CHECK: [0xfc,0x04,0x0a,0x42]
2489
2490 v_subrev_f16 v5, src_scc, v2
2491 // CHECK: [0xfd,0x04,0x0a,0x42]
2492
2493 v_subrev_f16 v5, 0xfe0b, v2
2494 // CHECK: [0xff,0x04,0x0a,0x42,0x0b,0xfe,0x00,0x00]
2495
2496 v_subrev_f16 v5, 0x3456, v2
2497 // CHECK: [0xff,0x04,0x0a,0x42,0x56,0x34,0x00,0x00]
2498
2499 v_subrev_f16 v5, v1, v255
2500 // CHECK: [0x01,0xff,0x0b,0x42]
2501
2502 v_mul_f16 v5, v1, v2
2503 // CHECK: [0x01,0x05,0x0a,0x44]
2504
2505 v_mul_f16 v255, v1, v2
2506 // CHECK: [0x01,0x05,0xfe,0x45]
2507
2508 v_mul_f16 v5, v255, v2
2509 // CHECK: [0xff,0x05,0x0a,0x44]
2510
2511 v_mul_f16 v5, s1, v2
2512 // CHECK: [0x01,0x04,0x0a,0x44]
2513
2514 v_mul_f16 v5, s101, v2
2515 // CHECK: [0x65,0x04,0x0a,0x44]
2516
2517 v_mul_f16 v5, flat_scratch_lo, v2
2518 // CHECK: [0x66,0x04,0x0a,0x44]
2519
2520 v_mul_f16 v5, flat_scratch_hi, v2
2521 // CHECK: [0x67,0x04,0x0a,0x44]
2522
2523 v_mul_f16 v5, vcc_lo, v2
2524 // CHECK: [0x6a,0x04,0x0a,0x44]
2525
2526 v_mul_f16 v5, vcc_hi, v2
2527 // CHECK: [0x6b,0x04,0x0a,0x44]
2528
2529 v_mul_f16 v5, tba_lo, v2
2530 // CHECK: [0x6c,0x04,0x0a,0x44]
2531
2532 v_mul_f16 v5, tba_hi, v2
2533 // CHECK: [0x6d,0x04,0x0a,0x44]
2534
2535 v_mul_f16 v5, tma_lo, v2
2536 // CHECK: [0x6e,0x04,0x0a,0x44]
2537
2538 v_mul_f16 v5, tma_hi, v2
2539 // CHECK: [0x6f,0x04,0x0a,0x44]
2540
2541 v_mul_f16 v5, ttmp11, v2
2542 // CHECK: [0x7b,0x04,0x0a,0x44]
2543
2544 v_mul_f16 v5, m0, v2
2545 // CHECK: [0x7c,0x04,0x0a,0x44]
2546
2547 v_mul_f16 v5, exec_lo, v2
2548 // CHECK: [0x7e,0x04,0x0a,0x44]
2549
2550 v_mul_f16 v5, exec_hi, v2
2551 // CHECK: [0x7f,0x04,0x0a,0x44]
2552
2553 v_mul_f16 v5, 0, v2
2554 // CHECK: [0x80,0x04,0x0a,0x44]
2555
2556 v_mul_f16 v5, -1, v2
2557 // CHECK: [0xc1,0x04,0x0a,0x44]
2558
2559 v_mul_f16 v5, 0.5, v2
2560 // CHECK: [0xf0,0x04,0x0a,0x44]
2561
2562 v_mul_f16 v5, -4.0, v2
2563 // CHECK: [0xf7,0x04,0x0a,0x44]
2564
2565 v_mul_f16 v5, src_vccz, v2
2566 // CHECK: [0xfb,0x04,0x0a,0x44]
2567
2568 v_mul_f16 v5, src_execz, v2
2569 // CHECK: [0xfc,0x04,0x0a,0x44]
2570
2571 v_mul_f16 v5, src_scc, v2
2572 // CHECK: [0xfd,0x04,0x0a,0x44]
2573
2574 v_mul_f16 v5, src_lds_direct, v2
2575 // CHECK: [0xfe,0x04,0x0a,0x44]
2576
2577 v_mul_f16 v5, 0xfe0b, v2
2578 // CHECK: [0xff,0x04,0x0a,0x44,0x0b,0xfe,0x00,0x00]
2579
2580 v_mul_f16 v5, 0x3456, v2
2581 // CHECK: [0xff,0x04,0x0a,0x44,0x56,0x34,0x00,0x00]
2582
2583 v_mul_f16 v5, v1, v255
2584 // CHECK: [0x01,0xff,0x0b,0x44]
2585
2586 v_mac_f16 v5, v1, v2
2587 // CHECK: [0x01,0x05,0x0a,0x46]
2588
2589 v_mac_f16 v255, v1, v2
2590 // CHECK: [0x01,0x05,0xfe,0x47]
2591
2592 v_mac_f16 v5, v255, v2
2593 // CHECK: [0xff,0x05,0x0a,0x46]
2594
2595 v_mac_f16 v5, s1, v2
2596 // CHECK: [0x01,0x04,0x0a,0x46]
2597
2598 v_mac_f16 v5, s101, v2
2599 // CHECK: [0x65,0x04,0x0a,0x46]
2600
2601 v_mac_f16 v5, flat_scratch_lo, v2
2602 // CHECK: [0x66,0x04,0x0a,0x46]
2603
2604 v_mac_f16 v5, flat_scratch_hi, v2
2605 // CHECK: [0x67,0x04,0x0a,0x46]
2606
2607 v_mac_f16 v5, vcc_lo, v2
2608 // CHECK: [0x6a,0x04,0x0a,0x46]
2609
2610 v_mac_f16 v5, vcc_hi, v2
2611 // CHECK: [0x6b,0x04,0x0a,0x46]
2612
2613 v_mac_f16 v5, tba_lo, v2
2614 // CHECK: [0x6c,0x04,0x0a,0x46]
2615
2616 v_mac_f16 v5, tba_hi, v2
2617 // CHECK: [0x6d,0x04,0x0a,0x46]
2618
2619 v_mac_f16 v5, tma_lo, v2
2620 // CHECK: [0x6e,0x04,0x0a,0x46]
2621
2622 v_mac_f16 v5, tma_hi, v2
2623 // CHECK: [0x6f,0x04,0x0a,0x46]
2624
2625 v_mac_f16 v5, ttmp11, v2
2626 // CHECK: [0x7b,0x04,0x0a,0x46]
2627
2628 v_mac_f16 v5, m0, v2
2629 // CHECK: [0x7c,0x04,0x0a,0x46]
2630
2631 v_mac_f16 v5, exec_lo, v2
2632 // CHECK: [0x7e,0x04,0x0a,0x46]
2633
2634 v_mac_f16 v5, exec_hi, v2
2635 // CHECK: [0x7f,0x04,0x0a,0x46]
2636
2637 v_mac_f16 v5, 0, v2
2638 // CHECK: [0x80,0x04,0x0a,0x46]
2639
2640 v_mac_f16 v5, -1, v2
2641 // CHECK: [0xc1,0x04,0x0a,0x46]
2642
2643 v_mac_f16 v5, 0.5, v2
2644 // CHECK: [0xf0,0x04,0x0a,0x46]
2645
2646 v_mac_f16 v5, -4.0, v2
2647 // CHECK: [0xf7,0x04,0x0a,0x46]
2648
2649 v_mac_f16 v5, src_vccz, v2
2650 // CHECK: [0xfb,0x04,0x0a,0x46]
2651
2652 v_mac_f16 v5, src_execz, v2
2653 // CHECK: [0xfc,0x04,0x0a,0x46]
2654
2655 v_mac_f16 v5, src_scc, v2
2656 // CHECK: [0xfd,0x04,0x0a,0x46]
2657
2658 v_mac_f16 v5, src_lds_direct, v2
2659 // CHECK: [0xfe,0x04,0x0a,0x46]
2660
2661 v_mac_f16 v5, 0xfe0b, v2
2662 // CHECK: [0xff,0x04,0x0a,0x46,0x0b,0xfe,0x00,0x00]
2663
2664 v_mac_f16 v5, 0x3456, v2
2665 // CHECK: [0xff,0x04,0x0a,0x46,0x56,0x34,0x00,0x00]
2666
2667 v_mac_f16 v5, v1, v255
2668 // CHECK: [0x01,0xff,0x0b,0x46]
2669
2670 v_madmk_f16 v5, v1, 0x1121, v3
2671 // CHECK: [0x01,0x07,0x0a,0x48,0x21,0x11,0x00,0x00]
2672
2673 v_madmk_f16 v255, v1, 0x1121, v3
2674 // CHECK: [0x01,0x07,0xfe,0x49,0x21,0x11,0x00,0x00]
2675
2676 v_madmk_f16 v5, v255, 0x1121, v3
2677 // CHECK: [0xff,0x07,0x0a,0x48,0x21,0x11,0x00,0x00]
2678
2679 v_madmk_f16 v5, 0, 0x1121, v3
2680 // CHECK: [0x80,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
2681
2682 v_madmk_f16 v5, -1, 0x1121, v3
2683 // CHECK: [0xc1,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
2684
2685 v_madmk_f16 v5, 0.5, 0x1121, v3
2686 // CHECK: [0xf0,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
2687
2688 v_madmk_f16 v5, -4.0, 0x1121, v3
2689 // CHECK: [0xf7,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
2690
2691 v_madmk_f16 v5, src_lds_direct, 0x1121, v3
2692 // CHECK: [0xfe,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
2693
2694 v_madmk_f16 v5, v1, 0xa1b1, v3
2695 // CHECK: [0x01,0x07,0x0a,0x48,0xb1,0xa1,0x00,0x00]
2696
2697 v_madmk_f16 v5, v1, 0x1121, v255
2698 // CHECK: [0x01,0xff,0x0b,0x48,0x21,0x11,0x00,0x00]
2699
2700 v_madak_f16 v5, v1, v2, 0x1121
2701 // CHECK: [0x01,0x05,0x0a,0x4a,0x21,0x11,0x00,0x00]
2702
2703 v_madak_f16 v255, v1, v2, 0x1121
2704 // CHECK: [0x01,0x05,0xfe,0x4b,0x21,0x11,0x00,0x00]
2705
2706 v_madak_f16 v5, v255, v2, 0x1121
2707 // CHECK: [0xff,0x05,0x0a,0x4a,0x21,0x11,0x00,0x00]
2708
2709 v_madak_f16 v5, 0, v2, 0x1121
2710 // CHECK: [0x80,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
2711
2712 v_madak_f16 v5, -1, v2, 0x1121
2713 // CHECK: [0xc1,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
2714
2715 v_madak_f16 v5, 0.5, v2, 0x1121
2716 // CHECK: [0xf0,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
2717
2718 v_madak_f16 v5, -4.0, v2, 0x1121
2719 // CHECK: [0xf7,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
2720
2721 v_madak_f16 v5, src_lds_direct, v2, 0x1121
2722 // CHECK: [0xfe,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
2723
2724 v_madak_f16 v5, v1, v255, 0x1121
2725 // CHECK: [0x01,0xff,0x0b,0x4a,0x21,0x11,0x00,0x00]
2726
2727 v_madak_f16 v5, v1, v2, 0xa1b1
2728 // CHECK: [0x01,0x05,0x0a,0x4a,0xb1,0xa1,0x00,0x00]
2729
2730 v_add_u16 v5, v1, v2
2731 // CHECK: [0x01,0x05,0x0a,0x4c]
2732
2733 v_add_u16 v255, v1, v2
2734 // CHECK: [0x01,0x05,0xfe,0x4d]
2735
2736 v_add_u16 v5, v255, v2
2737 // CHECK: [0xff,0x05,0x0a,0x4c]
2738
2739 v_add_u16 v5, s1, v2
2740 // CHECK: [0x01,0x04,0x0a,0x4c]
2741
2742 v_add_u16 v5, s101, v2
2743 // CHECK: [0x65,0x04,0x0a,0x4c]
2744
2745 v_add_u16 v5, flat_scratch_lo, v2
2746 // CHECK: [0x66,0x04,0x0a,0x4c]
2747
2748 v_add_u16 v5, flat_scratch_hi, v2
2749 // CHECK: [0x67,0x04,0x0a,0x4c]
2750
2751 v_add_u16 v5, vcc_lo, v2
2752 // CHECK: [0x6a,0x04,0x0a,0x4c]
2753
2754 v_add_u16 v5, vcc_hi, v2
2755 // CHECK: [0x6b,0x04,0x0a,0x4c]
2756
2757 v_add_u16 v5, tba_lo, v2
2758 // CHECK: [0x6c,0x04,0x0a,0x4c]
2759
2760 v_add_u16 v5, tba_hi, v2
2761 // CHECK: [0x6d,0x04,0x0a,0x4c]
2762
2763 v_add_u16 v5, tma_lo, v2
2764 // CHECK: [0x6e,0x04,0x0a,0x4c]
2765
2766 v_add_u16 v5, tma_hi, v2
2767 // CHECK: [0x6f,0x04,0x0a,0x4c]
2768
2769 v_add_u16 v5, ttmp11, v2
2770 // CHECK: [0x7b,0x04,0x0a,0x4c]
2771
2772 v_add_u16 v5, m0, v2
2773 // CHECK: [0x7c,0x04,0x0a,0x4c]
2774
2775 v_add_u16 v5, exec_lo, v2
2776 // CHECK: [0x7e,0x04,0x0a,0x4c]
2777
2778 v_add_u16 v5, exec_hi, v2
2779 // CHECK: [0x7f,0x04,0x0a,0x4c]
2780
2781 v_add_u16 v5, 0, v2
2782 // CHECK: [0x80,0x04,0x0a,0x4c]
2783
2784 v_add_u16 v5, -1, v2
2785 // CHECK: [0xc1,0x04,0x0a,0x4c]
2786
2787 v_add_u16 v5, 0.5, v2
2788 // CHECK: [0xf0,0x04,0x0a,0x4c]
2789
2790 v_add_u16 v5, -4.0, v2
2791 // CHECK: [0xf7,0x04,0x0a,0x4c]
2792
2793 v_add_u16 v5, src_vccz, v2
2794 // CHECK: [0xfb,0x04,0x0a,0x4c]
2795
2796 v_add_u16 v5, src_execz, v2
2797 // CHECK: [0xfc,0x04,0x0a,0x4c]
2798
2799 v_add_u16 v5, src_scc, v2
2800 // CHECK: [0xfd,0x04,0x0a,0x4c]
2801
2802 v_add_u16 v5, src_lds_direct, v2
2803 // CHECK: [0xfe,0x04,0x0a,0x4c]
2804
2805 v_add_u16 v5, 0xfe0b, v2
2806 // CHECK: [0xff,0x04,0x0a,0x4c,0x0b,0xfe,0x00,0x00]
2807
2808 v_add_u16 v5, 0x3456, v2
2809 // CHECK: [0xff,0x04,0x0a,0x4c,0x56,0x34,0x00,0x00]
2810
2811 v_add_u16 v5, v1, v255
2812 // CHECK: [0x01,0xff,0x0b,0x4c]
2813
2814 v_sub_u16 v5, v1, v2
2815 // CHECK: [0x01,0x05,0x0a,0x4e]
2816
2817 v_sub_u16 v255, v1, v2
2818 // CHECK: [0x01,0x05,0xfe,0x4f]
2819
2820 v_sub_u16 v5, v255, v2
2821 // CHECK: [0xff,0x05,0x0a,0x4e]
2822
2823 v_sub_u16 v5, s1, v2
2824 // CHECK: [0x01,0x04,0x0a,0x4e]
2825
2826 v_sub_u16 v5, s101, v2
2827 // CHECK: [0x65,0x04,0x0a,0x4e]
2828
2829 v_sub_u16 v5, flat_scratch_lo, v2
2830 // CHECK: [0x66,0x04,0x0a,0x4e]
2831
2832 v_sub_u16 v5, flat_scratch_hi, v2
2833 // CHECK: [0x67,0x04,0x0a,0x4e]
2834
2835 v_sub_u16 v5, vcc_lo, v2
2836 // CHECK: [0x6a,0x04,0x0a,0x4e]
2837
2838 v_sub_u16 v5, vcc_hi, v2
2839 // CHECK: [0x6b,0x04,0x0a,0x4e]
2840
2841 v_sub_u16 v5, tba_lo, v2
2842 // CHECK: [0x6c,0x04,0x0a,0x4e]
2843
2844 v_sub_u16 v5, tba_hi, v2
2845 // CHECK: [0x6d,0x04,0x0a,0x4e]
2846
2847 v_sub_u16 v5, tma_lo, v2
2848 // CHECK: [0x6e,0x04,0x0a,0x4e]
2849
2850 v_sub_u16 v5, tma_hi, v2
2851 // CHECK: [0x6f,0x04,0x0a,0x4e]
2852
2853 v_sub_u16 v5, ttmp11, v2
2854 // CHECK: [0x7b,0x04,0x0a,0x4e]
2855
2856 v_sub_u16 v5, m0, v2
2857 // CHECK: [0x7c,0x04,0x0a,0x4e]
2858
2859 v_sub_u16 v5, exec_lo, v2
2860 // CHECK: [0x7e,0x04,0x0a,0x4e]
2861
2862 v_sub_u16 v5, exec_hi, v2
2863 // CHECK: [0x7f,0x04,0x0a,0x4e]
2864
2865 v_sub_u16 v5, 0, v2
2866 // CHECK: [0x80,0x04,0x0a,0x4e]
2867
2868 v_sub_u16 v5, -1, v2
2869 // CHECK: [0xc1,0x04,0x0a,0x4e]
2870
2871 v_sub_u16 v5, 0.5, v2
2872 // CHECK: [0xf0,0x04,0x0a,0x4e]
2873
2874 v_sub_u16 v5, -4.0, v2
2875 // CHECK: [0xf7,0x04,0x0a,0x4e]
2876
2877 v_sub_u16 v5, src_vccz, v2
2878 // CHECK: [0xfb,0x04,0x0a,0x4e]
2879
2880 v_sub_u16 v5, src_execz, v2
2881 // CHECK: [0xfc,0x04,0x0a,0x4e]
2882
2883 v_sub_u16 v5, src_scc, v2
2884 // CHECK: [0xfd,0x04,0x0a,0x4e]
2885
2886 v_sub_u16 v5, src_lds_direct, v2
2887 // CHECK: [0xfe,0x04,0x0a,0x4e]
2888
2889 v_sub_u16 v5, 0xfe0b, v2
2890 // CHECK: [0xff,0x04,0x0a,0x4e,0x0b,0xfe,0x00,0x00]
2891
2892 v_sub_u16 v5, 0x3456, v2
2893 // CHECK: [0xff,0x04,0x0a,0x4e,0x56,0x34,0x00,0x00]
2894
2895 v_sub_u16 v5, v1, v255
2896 // CHECK: [0x01,0xff,0x0b,0x4e]
2897
2898 v_subrev_u16 v5, v1, v2
2899 // CHECK: [0x01,0x05,0x0a,0x50]
2900
2901 v_subrev_u16 v255, v1, v2
2902 // CHECK: [0x01,0x05,0xfe,0x51]
2903
2904 v_subrev_u16 v5, v255, v2
2905 // CHECK: [0xff,0x05,0x0a,0x50]
2906
2907 v_subrev_u16 v5, s1, v2
2908 // CHECK: [0x01,0x04,0x0a,0x50]
2909
2910 v_subrev_u16 v5, s101, v2
2911 // CHECK: [0x65,0x04,0x0a,0x50]
2912
2913 v_subrev_u16 v5, flat_scratch_lo, v2
2914 // CHECK: [0x66,0x04,0x0a,0x50]
2915
2916 v_subrev_u16 v5, flat_scratch_hi, v2
2917 // CHECK: [0x67,0x04,0x0a,0x50]
2918
2919 v_subrev_u16 v5, vcc_lo, v2
2920 // CHECK: [0x6a,0x04,0x0a,0x50]
2921
2922 v_subrev_u16 v5, vcc_hi, v2
2923 // CHECK: [0x6b,0x04,0x0a,0x50]
2924
2925 v_subrev_u16 v5, tba_lo, v2
2926 // CHECK: [0x6c,0x04,0x0a,0x50]
2927
2928 v_subrev_u16 v5, tba_hi, v2
2929 // CHECK: [0x6d,0x04,0x0a,0x50]
2930
2931 v_subrev_u16 v5, tma_lo, v2
2932 // CHECK: [0x6e,0x04,0x0a,0x50]
2933
2934 v_subrev_u16 v5, tma_hi, v2
2935 // CHECK: [0x6f,0x04,0x0a,0x50]
2936
2937 v_subrev_u16 v5, ttmp11, v2
2938 // CHECK: [0x7b,0x04,0x0a,0x50]
2939
2940 v_subrev_u16 v5, m0, v2
2941 // CHECK: [0x7c,0x04,0x0a,0x50]
2942
2943 v_subrev_u16 v5, exec_lo, v2
2944 // CHECK: [0x7e,0x04,0x0a,0x50]
2945
2946 v_subrev_u16 v5, exec_hi, v2
2947 // CHECK: [0x7f,0x04,0x0a,0x50]
2948
2949 v_subrev_u16 v5, 0, v2
2950 // CHECK: [0x80,0x04,0x0a,0x50]
2951
2952 v_subrev_u16 v5, -1, v2
2953 // CHECK: [0xc1,0x04,0x0a,0x50]
2954
2955 v_subrev_u16 v5, 0.5, v2
2956 // CHECK: [0xf0,0x04,0x0a,0x50]
2957
2958 v_subrev_u16 v5, -4.0, v2
2959 // CHECK: [0xf7,0x04,0x0a,0x50]
2960
2961 v_subrev_u16 v5, src_vccz, v2
2962 // CHECK: [0xfb,0x04,0x0a,0x50]
2963
2964 v_subrev_u16 v5, src_execz, v2
2965 // CHECK: [0xfc,0x04,0x0a,0x50]
2966
2967 v_subrev_u16 v5, src_scc, v2
2968 // CHECK: [0xfd,0x04,0x0a,0x50]
2969
2970 v_subrev_u16 v5, 0xfe0b, v2
2971 // CHECK: [0xff,0x04,0x0a,0x50,0x0b,0xfe,0x00,0x00]
2972
2973 v_subrev_u16 v5, 0x3456, v2
2974 // CHECK: [0xff,0x04,0x0a,0x50,0x56,0x34,0x00,0x00]
2975
2976 v_subrev_u16 v5, v1, v255
2977 // CHECK: [0x01,0xff,0x0b,0x50]
2978
2979 v_mul_lo_u16 v5, v1, v2
2980 // CHECK: [0x01,0x05,0x0a,0x52]
2981
2982 v_mul_lo_u16 v255, v1, v2
2983 // CHECK: [0x01,0x05,0xfe,0x53]
2984
2985 v_mul_lo_u16 v5, v255, v2
2986 // CHECK: [0xff,0x05,0x0a,0x52]
2987
2988 v_mul_lo_u16 v5, s1, v2
2989 // CHECK: [0x01,0x04,0x0a,0x52]
2990
2991 v_mul_lo_u16 v5, s101, v2
2992 // CHECK: [0x65,0x04,0x0a,0x52]
2993
2994 v_mul_lo_u16 v5, flat_scratch_lo, v2
2995 // CHECK: [0x66,0x04,0x0a,0x52]
2996
2997 v_mul_lo_u16 v5, flat_scratch_hi, v2
2998 // CHECK: [0x67,0x04,0x0a,0x52]
2999
3000 v_mul_lo_u16 v5, vcc_lo, v2
3001 // CHECK: [0x6a,0x04,0x0a,0x52]
3002
3003 v_mul_lo_u16 v5, vcc_hi, v2
3004 // CHECK: [0x6b,0x04,0x0a,0x52]
3005
3006 v_mul_lo_u16 v5, tba_lo, v2
3007 // CHECK: [0x6c,0x04,0x0a,0x52]
3008
3009 v_mul_lo_u16 v5, tba_hi, v2
3010 // CHECK: [0x6d,0x04,0x0a,0x52]
3011
3012 v_mul_lo_u16 v5, tma_lo, v2
3013 // CHECK: [0x6e,0x04,0x0a,0x52]
3014
3015 v_mul_lo_u16 v5, tma_hi, v2
3016 // CHECK: [0x6f,0x04,0x0a,0x52]
3017
3018 v_mul_lo_u16 v5, ttmp11, v2
3019 // CHECK: [0x7b,0x04,0x0a,0x52]
3020
3021 v_mul_lo_u16 v5, m0, v2
3022 // CHECK: [0x7c,0x04,0x0a,0x52]
3023
3024 v_mul_lo_u16 v5, exec_lo, v2
3025 // CHECK: [0x7e,0x04,0x0a,0x52]
3026
3027 v_mul_lo_u16 v5, exec_hi, v2
3028 // CHECK: [0x7f,0x04,0x0a,0x52]
3029
3030 v_mul_lo_u16 v5, 0, v2
3031 // CHECK: [0x80,0x04,0x0a,0x52]
3032
3033 v_mul_lo_u16 v5, -1, v2
3034 // CHECK: [0xc1,0x04,0x0a,0x52]
3035
3036 v_mul_lo_u16 v5, 0.5, v2
3037 // CHECK: [0xf0,0x04,0x0a,0x52]
3038
3039 v_mul_lo_u16 v5, -4.0, v2
3040 // CHECK: [0xf7,0x04,0x0a,0x52]
3041
3042 v_mul_lo_u16 v5, src_vccz, v2
3043 // CHECK: [0xfb,0x04,0x0a,0x52]
3044
3045 v_mul_lo_u16 v5, src_execz, v2
3046 // CHECK: [0xfc,0x04,0x0a,0x52]
3047
3048 v_mul_lo_u16 v5, src_scc, v2
3049 // CHECK: [0xfd,0x04,0x0a,0x52]
3050
3051 v_mul_lo_u16 v5, src_lds_direct, v2
3052 // CHECK: [0xfe,0x04,0x0a,0x52]
3053
3054 v_mul_lo_u16 v5, 0xfe0b, v2
3055 // CHECK: [0xff,0x04,0x0a,0x52,0x0b,0xfe,0x00,0x00]
3056
3057 v_mul_lo_u16 v5, 0x3456, v2
3058 // CHECK: [0xff,0x04,0x0a,0x52,0x56,0x34,0x00,0x00]
3059
3060 v_mul_lo_u16 v5, v1, v255
3061 // CHECK: [0x01,0xff,0x0b,0x52]
3062
3063 v_lshlrev_b16 v5, v1, v2
3064 // CHECK: [0x01,0x05,0x0a,0x54]
3065
3066 v_lshlrev_b16 v255, v1, v2
3067 // CHECK: [0x01,0x05,0xfe,0x55]
3068
3069 v_lshlrev_b16 v5, v255, v2
3070 // CHECK: [0xff,0x05,0x0a,0x54]
3071
3072 v_lshlrev_b16 v5, s1, v2
3073 // CHECK: [0x01,0x04,0x0a,0x54]
3074
3075 v_lshlrev_b16 v5, s101, v2
3076 // CHECK: [0x65,0x04,0x0a,0x54]
3077
3078 v_lshlrev_b16 v5, flat_scratch_lo, v2
3079 // CHECK: [0x66,0x04,0x0a,0x54]
3080
3081 v_lshlrev_b16 v5, flat_scratch_hi, v2
3082 // CHECK: [0x67,0x04,0x0a,0x54]
3083
3084 v_lshlrev_b16 v5, vcc_lo, v2
3085 // CHECK: [0x6a,0x04,0x0a,0x54]
3086
3087 v_lshlrev_b16 v5, vcc_hi, v2
3088 // CHECK: [0x6b,0x04,0x0a,0x54]
3089
3090 v_lshlrev_b16 v5, tba_lo, v2
3091 // CHECK: [0x6c,0x04,0x0a,0x54]
3092
3093 v_lshlrev_b16 v5, tba_hi, v2
3094 // CHECK: [0x6d,0x04,0x0a,0x54]
3095
3096 v_lshlrev_b16 v5, tma_lo, v2
3097 // CHECK: [0x6e,0x04,0x0a,0x54]
3098
3099 v_lshlrev_b16 v5, tma_hi, v2
3100 // CHECK: [0x6f,0x04,0x0a,0x54]
3101
3102 v_lshlrev_b16 v5, ttmp11, v2
3103 // CHECK: [0x7b,0x04,0x0a,0x54]
3104
3105 v_lshlrev_b16 v5, m0, v2
3106 // CHECK: [0x7c,0x04,0x0a,0x54]
3107
3108 v_lshlrev_b16 v5, exec_lo, v2
3109 // CHECK: [0x7e,0x04,0x0a,0x54]
3110
3111 v_lshlrev_b16 v5, exec_hi, v2
3112 // CHECK: [0x7f,0x04,0x0a,0x54]
3113
3114 v_lshlrev_b16 v5, 0, v2
3115 // CHECK: [0x80,0x04,0x0a,0x54]
3116
3117 v_lshlrev_b16 v5, -1, v2
3118 // CHECK: [0xc1,0x04,0x0a,0x54]
3119
3120 v_lshlrev_b16 v5, 0.5, v2
3121 // CHECK: [0xf0,0x04,0x0a,0x54]
3122
3123 v_lshlrev_b16 v5, -4.0, v2
3124 // CHECK: [0xf7,0x04,0x0a,0x54]
3125
3126 v_lshlrev_b16 v5, src_vccz, v2
3127 // CHECK: [0xfb,0x04,0x0a,0x54]
3128
3129 v_lshlrev_b16 v5, src_execz, v2
3130 // CHECK: [0xfc,0x04,0x0a,0x54]
3131
3132 v_lshlrev_b16 v5, src_scc, v2
3133 // CHECK: [0xfd,0x04,0x0a,0x54]
3134
3135 v_lshlrev_b16 v5, 0xfe0b, v2
3136 // CHECK: [0xff,0x04,0x0a,0x54,0x0b,0xfe,0x00,0x00]
3137
3138 v_lshlrev_b16 v5, 0x3456, v2
3139 // CHECK: [0xff,0x04,0x0a,0x54,0x56,0x34,0x00,0x00]
3140
3141 v_lshlrev_b16 v5, v1, v255
3142 // CHECK: [0x01,0xff,0x0b,0x54]
3143
3144 v_lshrrev_b16 v5, v1, v2
3145 // CHECK: [0x01,0x05,0x0a,0x56]
3146
3147 v_lshrrev_b16 v255, v1, v2
3148 // CHECK: [0x01,0x05,0xfe,0x57]
3149
3150 v_lshrrev_b16 v5, v255, v2
3151 // CHECK: [0xff,0x05,0x0a,0x56]
3152
3153 v_lshrrev_b16 v5, s1, v2
3154 // CHECK: [0x01,0x04,0x0a,0x56]
3155
3156 v_lshrrev_b16 v5, s101, v2
3157 // CHECK: [0x65,0x04,0x0a,0x56]
3158
3159 v_lshrrev_b16 v5, flat_scratch_lo, v2
3160 // CHECK: [0x66,0x04,0x0a,0x56]
3161
3162 v_lshrrev_b16 v5, flat_scratch_hi, v2
3163 // CHECK: [0x67,0x04,0x0a,0x56]
3164
3165 v_lshrrev_b16 v5, vcc_lo, v2
3166 // CHECK: [0x6a,0x04,0x0a,0x56]
3167
3168 v_lshrrev_b16 v5, vcc_hi, v2
3169 // CHECK: [0x6b,0x04,0x0a,0x56]
3170
3171 v_lshrrev_b16 v5, tba_lo, v2
3172 // CHECK: [0x6c,0x04,0x0a,0x56]
3173
3174 v_lshrrev_b16 v5, tba_hi, v2
3175 // CHECK: [0x6d,0x04,0x0a,0x56]
3176
3177 v_lshrrev_b16 v5, tma_lo, v2
3178 // CHECK: [0x6e,0x04,0x0a,0x56]
3179
3180 v_lshrrev_b16 v5, tma_hi, v2
3181 // CHECK: [0x6f,0x04,0x0a,0x56]
3182
3183 v_lshrrev_b16 v5, ttmp11, v2
3184 // CHECK: [0x7b,0x04,0x0a,0x56]
3185
3186 v_lshrrev_b16 v5, m0, v2
3187 // CHECK: [0x7c,0x04,0x0a,0x56]
3188
3189 v_lshrrev_b16 v5, exec_lo, v2
3190 // CHECK: [0x7e,0x04,0x0a,0x56]
3191
3192 v_lshrrev_b16 v5, exec_hi, v2
3193 // CHECK: [0x7f,0x04,0x0a,0x56]
3194
3195 v_lshrrev_b16 v5, 0, v2
3196 // CHECK: [0x80,0x04,0x0a,0x56]
3197
3198 v_lshrrev_b16 v5, -1, v2
3199 // CHECK: [0xc1,0x04,0x0a,0x56]
3200
3201 v_lshrrev_b16 v5, 0.5, v2
3202 // CHECK: [0xf0,0x04,0x0a,0x56]
3203
3204 v_lshrrev_b16 v5, -4.0, v2
3205 // CHECK: [0xf7,0x04,0x0a,0x56]
3206
3207 v_lshrrev_b16 v5, src_vccz, v2
3208 // CHECK: [0xfb,0x04,0x0a,0x56]
3209
3210 v_lshrrev_b16 v5, src_execz, v2
3211 // CHECK: [0xfc,0x04,0x0a,0x56]
3212
3213 v_lshrrev_b16 v5, src_scc, v2
3214 // CHECK: [0xfd,0x04,0x0a,0x56]
3215
3216 v_lshrrev_b16 v5, 0xfe0b, v2
3217 // CHECK: [0xff,0x04,0x0a,0x56,0x0b,0xfe,0x00,0x00]
3218
3219 v_lshrrev_b16 v5, 0x3456, v2
3220 // CHECK: [0xff,0x04,0x0a,0x56,0x56,0x34,0x00,0x00]
3221
3222 v_lshrrev_b16 v5, v1, v255
3223 // CHECK: [0x01,0xff,0x0b,0x56]
3224
3225 v_ashrrev_i16 v5, v1, v2
3226 // CHECK: [0x01,0x05,0x0a,0x58]
3227
3228 v_ashrrev_i16 v255, v1, v2
3229 // CHECK: [0x01,0x05,0xfe,0x59]
3230
3231 v_ashrrev_i16 v5, v255, v2
3232 // CHECK: [0xff,0x05,0x0a,0x58]
3233
3234 v_ashrrev_i16 v5, s1, v2
3235 // CHECK: [0x01,0x04,0x0a,0x58]
3236
3237 v_ashrrev_i16 v5, s101, v2
3238 // CHECK: [0x65,0x04,0x0a,0x58]
3239
3240 v_ashrrev_i16 v5, flat_scratch_lo, v2
3241 // CHECK: [0x66,0x04,0x0a,0x58]
3242
3243 v_ashrrev_i16 v5, flat_scratch_hi, v2
3244 // CHECK: [0x67,0x04,0x0a,0x58]
3245
3246 v_ashrrev_i16 v5, vcc_lo, v2
3247 // CHECK: [0x6a,0x04,0x0a,0x58]
3248
3249 v_ashrrev_i16 v5, vcc_hi, v2
3250 // CHECK: [0x6b,0x04,0x0a,0x58]
3251
3252 v_ashrrev_i16 v5, tba_lo, v2
3253 // CHECK: [0x6c,0x04,0x0a,0x58]
3254
3255 v_ashrrev_i16 v5, tba_hi, v2
3256 // CHECK: [0x6d,0x04,0x0a,0x58]
3257
3258 v_ashrrev_i16 v5, tma_lo, v2
3259 // CHECK: [0x6e,0x04,0x0a,0x58]
3260
3261 v_ashrrev_i16 v5, tma_hi, v2
3262 // CHECK: [0x6f,0x04,0x0a,0x58]
3263
3264 v_ashrrev_i16 v5, ttmp11, v2
3265 // CHECK: [0x7b,0x04,0x0a,0x58]
3266
3267 v_ashrrev_i16 v5, m0, v2
3268 // CHECK: [0x7c,0x04,0x0a,0x58]
3269
3270 v_ashrrev_i16 v5, exec_lo, v2
3271 // CHECK: [0x7e,0x04,0x0a,0x58]
3272
3273 v_ashrrev_i16 v5, exec_hi, v2
3274 // CHECK: [0x7f,0x04,0x0a,0x58]
3275
3276 v_ashrrev_i16 v5, 0, v2
3277 // CHECK: [0x80,0x04,0x0a,0x58]
3278
3279 v_ashrrev_i16 v5, -1, v2
3280 // CHECK: [0xc1,0x04,0x0a,0x58]
3281
3282 v_ashrrev_i16 v5, 0.5, v2
3283 // CHECK: [0xf0,0x04,0x0a,0x58]
3284
3285 v_ashrrev_i16 v5, -4.0, v2
3286 // CHECK: [0xf7,0x04,0x0a,0x58]
3287
3288 v_ashrrev_i16 v5, src_vccz, v2
3289 // CHECK: [0xfb,0x04,0x0a,0x58]
3290
3291 v_ashrrev_i16 v5, src_execz, v2
3292 // CHECK: [0xfc,0x04,0x0a,0x58]
3293
3294 v_ashrrev_i16 v5, src_scc, v2
3295 // CHECK: [0xfd,0x04,0x0a,0x58]
3296
3297 v_ashrrev_i16 v5, 0xfe0b, v2
3298 // CHECK: [0xff,0x04,0x0a,0x58,0x0b,0xfe,0x00,0x00]
3299
3300 v_ashrrev_i16 v5, 0x3456, v2
3301 // CHECK: [0xff,0x04,0x0a,0x58,0x56,0x34,0x00,0x00]
3302
3303 v_ashrrev_i16 v5, v1, v255
3304 // CHECK: [0x01,0xff,0x0b,0x58]
3305
3306 v_max_f16 v5, v1, v2
3307 // CHECK: [0x01,0x05,0x0a,0x5a]
3308
3309 v_max_f16 v255, v1, v2
3310 // CHECK: [0x01,0x05,0xfe,0x5b]
3311
3312 v_max_f16 v5, v255, v2
3313 // CHECK: [0xff,0x05,0x0a,0x5a]
3314
3315 v_max_f16 v5, s1, v2
3316 // CHECK: [0x01,0x04,0x0a,0x5a]
3317
3318 v_max_f16 v5, s101, v2
3319 // CHECK: [0x65,0x04,0x0a,0x5a]
3320
3321 v_max_f16 v5, flat_scratch_lo, v2
3322 // CHECK: [0x66,0x04,0x0a,0x5a]
3323
3324 v_max_f16 v5, flat_scratch_hi, v2
3325 // CHECK: [0x67,0x04,0x0a,0x5a]
3326
3327 v_max_f16 v5, vcc_lo, v2
3328 // CHECK: [0x6a,0x04,0x0a,0x5a]
3329
3330 v_max_f16 v5, vcc_hi, v2
3331 // CHECK: [0x6b,0x04,0x0a,0x5a]
3332
3333 v_max_f16 v5, tba_lo, v2
3334 // CHECK: [0x6c,0x04,0x0a,0x5a]
3335
3336 v_max_f16 v5, tba_hi, v2
3337 // CHECK: [0x6d,0x04,0x0a,0x5a]
3338
3339 v_max_f16 v5, tma_lo, v2
3340 // CHECK: [0x6e,0x04,0x0a,0x5a]
3341
3342 v_max_f16 v5, tma_hi, v2
3343 // CHECK: [0x6f,0x04,0x0a,0x5a]
3344
3345 v_max_f16 v5, ttmp11, v2
3346 // CHECK: [0x7b,0x04,0x0a,0x5a]
3347
3348 v_max_f16 v5, m0, v2
3349 // CHECK: [0x7c,0x04,0x0a,0x5a]
3350
3351 v_max_f16 v5, exec_lo, v2
3352 // CHECK: [0x7e,0x04,0x0a,0x5a]
3353
3354 v_max_f16 v5, exec_hi, v2
3355 // CHECK: [0x7f,0x04,0x0a,0x5a]
3356
3357 v_max_f16 v5, 0, v2
3358 // CHECK: [0x80,0x04,0x0a,0x5a]
3359
3360 v_max_f16 v5, -1, v2
3361 // CHECK: [0xc1,0x04,0x0a,0x5a]
3362
3363 v_max_f16 v5, 0.5, v2
3364 // CHECK: [0xf0,0x04,0x0a,0x5a]
3365
3366 v_max_f16 v5, -4.0, v2
3367 // CHECK: [0xf7,0x04,0x0a,0x5a]
3368
3369 v_max_f16 v5, src_vccz, v2
3370 // CHECK: [0xfb,0x04,0x0a,0x5a]
3371
3372 v_max_f16 v5, src_execz, v2
3373 // CHECK: [0xfc,0x04,0x0a,0x5a]
3374
3375 v_max_f16 v5, src_scc, v2
3376 // CHECK: [0xfd,0x04,0x0a,0x5a]
3377
3378 v_max_f16 v5, src_lds_direct, v2
3379 // CHECK: [0xfe,0x04,0x0a,0x5a]
3380
3381 v_max_f16 v5, 0xfe0b, v2
3382 // CHECK: [0xff,0x04,0x0a,0x5a,0x0b,0xfe,0x00,0x00]
3383
3384 v_max_f16 v5, 0x3456, v2
3385 // CHECK: [0xff,0x04,0x0a,0x5a,0x56,0x34,0x00,0x00]
3386
3387 v_max_f16 v5, v1, v255
3388 // CHECK: [0x01,0xff,0x0b,0x5a]
3389
3390 v_min_f16 v5, v1, v2
3391 // CHECK: [0x01,0x05,0x0a,0x5c]
3392
3393 v_min_f16 v255, v1, v2
3394 // CHECK: [0x01,0x05,0xfe,0x5d]
3395
3396 v_min_f16 v5, v255, v2
3397 // CHECK: [0xff,0x05,0x0a,0x5c]
3398
3399 v_min_f16 v5, s1, v2
3400 // CHECK: [0x01,0x04,0x0a,0x5c]
3401
3402 v_min_f16 v5, s101, v2
3403 // CHECK: [0x65,0x04,0x0a,0x5c]
3404
3405 v_min_f16 v5, flat_scratch_lo, v2
3406 // CHECK: [0x66,0x04,0x0a,0x5c]
3407
3408 v_min_f16 v5, flat_scratch_hi, v2
3409 // CHECK: [0x67,0x04,0x0a,0x5c]
3410
3411 v_min_f16 v5, vcc_lo, v2
3412 // CHECK: [0x6a,0x04,0x0a,0x5c]
3413
3414 v_min_f16 v5, vcc_hi, v2
3415 // CHECK: [0x6b,0x04,0x0a,0x5c]
3416
3417 v_min_f16 v5, tba_lo, v2
3418 // CHECK: [0x6c,0x04,0x0a,0x5c]
3419
3420 v_min_f16 v5, tba_hi, v2
3421 // CHECK: [0x6d,0x04,0x0a,0x5c]
3422
3423 v_min_f16 v5, tma_lo, v2
3424 // CHECK: [0x6e,0x04,0x0a,0x5c]
3425
3426 v_min_f16 v5, tma_hi, v2
3427 // CHECK: [0x6f,0x04,0x0a,0x5c]
3428
3429 v_min_f16 v5, ttmp11, v2
3430 // CHECK: [0x7b,0x04,0x0a,0x5c]
3431
3432 v_min_f16 v5, m0, v2
3433 // CHECK: [0x7c,0x04,0x0a,0x5c]
3434
3435 v_min_f16 v5, exec_lo, v2
3436 // CHECK: [0x7e,0x04,0x0a,0x5c]
3437
3438 v_min_f16 v5, exec_hi, v2
3439 // CHECK: [0x7f,0x04,0x0a,0x5c]
3440
3441 v_min_f16 v5, 0, v2
3442 // CHECK: [0x80,0x04,0x0a,0x5c]
3443
3444 v_min_f16 v5, -1, v2
3445 // CHECK: [0xc1,0x04,0x0a,0x5c]
3446
3447 v_min_f16 v5, 0.5, v2
3448 // CHECK: [0xf0,0x04,0x0a,0x5c]
3449
3450 v_min_f16 v5, -4.0, v2
3451 // CHECK: [0xf7,0x04,0x0a,0x5c]
3452
3453 v_min_f16 v5, src_vccz, v2
3454 // CHECK: [0xfb,0x04,0x0a,0x5c]
3455
3456 v_min_f16 v5, src_execz, v2
3457 // CHECK: [0xfc,0x04,0x0a,0x5c]
3458
3459 v_min_f16 v5, src_scc, v2
3460 // CHECK: [0xfd,0x04,0x0a,0x5c]
3461
3462 v_min_f16 v5, src_lds_direct, v2
3463 // CHECK: [0xfe,0x04,0x0a,0x5c]
3464
3465 v_min_f16 v5, 0xfe0b, v2
3466 // CHECK: [0xff,0x04,0x0a,0x5c,0x0b,0xfe,0x00,0x00]
3467
3468 v_min_f16 v5, 0x3456, v2
3469 // CHECK: [0xff,0x04,0x0a,0x5c,0x56,0x34,0x00,0x00]
3470
3471 v_min_f16 v5, v1, v255
3472 // CHECK: [0x01,0xff,0x0b,0x5c]
3473
3474 v_max_u16 v5, v1, v2
3475 // CHECK: [0x01,0x05,0x0a,0x5e]
3476
3477 v_max_u16 v255, v1, v2
3478 // CHECK: [0x01,0x05,0xfe,0x5f]
3479
3480 v_max_u16 v5, v255, v2
3481 // CHECK: [0xff,0x05,0x0a,0x5e]
3482
3483 v_max_u16 v5, s1, v2
3484 // CHECK: [0x01,0x04,0x0a,0x5e]
3485
3486 v_max_u16 v5, s101, v2
3487 // CHECK: [0x65,0x04,0x0a,0x5e]
3488
3489 v_max_u16 v5, flat_scratch_lo, v2
3490 // CHECK: [0x66,0x04,0x0a,0x5e]
3491
3492 v_max_u16 v5, flat_scratch_hi, v2
3493 // CHECK: [0x67,0x04,0x0a,0x5e]
3494
3495 v_max_u16 v5, vcc_lo, v2
3496 // CHECK: [0x6a,0x04,0x0a,0x5e]
3497
3498 v_max_u16 v5, vcc_hi, v2
3499 // CHECK: [0x6b,0x04,0x0a,0x5e]
3500
3501 v_max_u16 v5, tba_lo, v2
3502 // CHECK: [0x6c,0x04,0x0a,0x5e]
3503
3504 v_max_u16 v5, tba_hi, v2
3505 // CHECK: [0x6d,0x04,0x0a,0x5e]
3506
3507 v_max_u16 v5, tma_lo, v2
3508 // CHECK: [0x6e,0x04,0x0a,0x5e]
3509
3510 v_max_u16 v5, tma_hi, v2
3511 // CHECK: [0x6f,0x04,0x0a,0x5e]
3512
3513 v_max_u16 v5, ttmp11, v2
3514 // CHECK: [0x7b,0x04,0x0a,0x5e]
3515
3516 v_max_u16 v5, m0, v2
3517 // CHECK: [0x7c,0x04,0x0a,0x5e]
3518
3519 v_max_u16 v5, exec_lo, v2
3520 // CHECK: [0x7e,0x04,0x0a,0x5e]
3521
3522 v_max_u16 v5, exec_hi, v2
3523 // CHECK: [0x7f,0x04,0x0a,0x5e]
3524
3525 v_max_u16 v5, 0, v2
3526 // CHECK: [0x80,0x04,0x0a,0x5e]
3527
3528 v_max_u16 v5, -1, v2
3529 // CHECK: [0xc1,0x04,0x0a,0x5e]
3530
3531 v_max_u16 v5, 0.5, v2
3532 // CHECK: [0xf0,0x04,0x0a,0x5e]
3533
3534 v_max_u16 v5, -4.0, v2
3535 // CHECK: [0xf7,0x04,0x0a,0x5e]
3536
3537 v_max_u16 v5, src_vccz, v2
3538 // CHECK: [0xfb,0x04,0x0a,0x5e]
3539
3540 v_max_u16 v5, src_execz, v2
3541 // CHECK: [0xfc,0x04,0x0a,0x5e]
3542
3543 v_max_u16 v5, src_scc, v2
3544 // CHECK: [0xfd,0x04,0x0a,0x5e]
3545
3546 v_max_u16 v5, src_lds_direct, v2
3547 // CHECK: [0xfe,0x04,0x0a,0x5e]
3548
3549 v_max_u16 v5, 0xfe0b, v2
3550 // CHECK: [0xff,0x04,0x0a,0x5e,0x0b,0xfe,0x00,0x00]
3551
3552 v_max_u16 v5, 0x3456, v2
3553 // CHECK: [0xff,0x04,0x0a,0x5e,0x56,0x34,0x00,0x00]
3554
3555 v_max_u16 v5, v1, v255
3556 // CHECK: [0x01,0xff,0x0b,0x5e]
3557
3558 v_max_i16 v5, v1, v2
3559 // CHECK: [0x01,0x05,0x0a,0x60]
3560
3561 v_max_i16 v255, v1, v2
3562 // CHECK: [0x01,0x05,0xfe,0x61]
3563
3564 v_max_i16 v5, v255, v2
3565 // CHECK: [0xff,0x05,0x0a,0x60]
3566
3567 v_max_i16 v5, s1, v2
3568 // CHECK: [0x01,0x04,0x0a,0x60]
3569
3570 v_max_i16 v5, s101, v2
3571 // CHECK: [0x65,0x04,0x0a,0x60]
3572
3573 v_max_i16 v5, flat_scratch_lo, v2
3574 // CHECK: [0x66,0x04,0x0a,0x60]
3575
3576 v_max_i16 v5, flat_scratch_hi, v2
3577 // CHECK: [0x67,0x04,0x0a,0x60]
3578
3579 v_max_i16 v5, vcc_lo, v2
3580 // CHECK: [0x6a,0x04,0x0a,0x60]
3581
3582 v_max_i16 v5, vcc_hi, v2
3583 // CHECK: [0x6b,0x04,0x0a,0x60]
3584
3585 v_max_i16 v5, tba_lo, v2
3586 // CHECK: [0x6c,0x04,0x0a,0x60]
3587
3588 v_max_i16 v5, tba_hi, v2
3589 // CHECK: [0x6d,0x04,0x0a,0x60]
3590
3591 v_max_i16 v5, tma_lo, v2
3592 // CHECK: [0x6e,0x04,0x0a,0x60]
3593
3594 v_max_i16 v5, tma_hi, v2
3595 // CHECK: [0x6f,0x04,0x0a,0x60]
3596
3597 v_max_i16 v5, ttmp11, v2
3598 // CHECK: [0x7b,0x04,0x0a,0x60]
3599
3600 v_max_i16 v5, m0, v2
3601 // CHECK: [0x7c,0x04,0x0a,0x60]
3602
3603 v_max_i16 v5, exec_lo, v2
3604 // CHECK: [0x7e,0x04,0x0a,0x60]
3605
3606 v_max_i16 v5, exec_hi, v2
3607 // CHECK: [0x7f,0x04,0x0a,0x60]
3608
3609 v_max_i16 v5, 0, v2
3610 // CHECK: [0x80,0x04,0x0a,0x60]
3611
3612 v_max_i16 v5, -1, v2
3613 // CHECK: [0xc1,0x04,0x0a,0x60]
3614
3615 v_max_i16 v5, 0.5, v2
3616 // CHECK: [0xf0,0x04,0x0a,0x60]
3617
3618 v_max_i16 v5, -4.0, v2
3619 // CHECK: [0xf7,0x04,0x0a,0x60]
3620
3621 v_max_i16 v5, src_vccz, v2
3622 // CHECK: [0xfb,0x04,0x0a,0x60]
3623
3624 v_max_i16 v5, src_execz, v2
3625 // CHECK: [0xfc,0x04,0x0a,0x60]
3626
3627 v_max_i16 v5, src_scc, v2
3628 // CHECK: [0xfd,0x04,0x0a,0x60]
3629
3630 v_max_i16 v5, src_lds_direct, v2
3631 // CHECK: [0xfe,0x04,0x0a,0x60]
3632
3633 v_max_i16 v5, 0xfe0b, v2
3634 // CHECK: [0xff,0x04,0x0a,0x60,0x0b,0xfe,0x00,0x00]
3635
3636 v_max_i16 v5, 0x3456, v2
3637 // CHECK: [0xff,0x04,0x0a,0x60,0x56,0x34,0x00,0x00]
3638
3639 v_max_i16 v5, v1, v255
3640 // CHECK: [0x01,0xff,0x0b,0x60]
3641
3642 v_min_u16 v5, v1, v2
3643 // CHECK: [0x01,0x05,0x0a,0x62]
3644
3645 v_min_u16 v255, v1, v2
3646 // CHECK: [0x01,0x05,0xfe,0x63]
3647
3648 v_min_u16 v5, v255, v2
3649 // CHECK: [0xff,0x05,0x0a,0x62]
3650
3651 v_min_u16 v5, s1, v2
3652 // CHECK: [0x01,0x04,0x0a,0x62]
3653
3654 v_min_u16 v5, s101, v2
3655 // CHECK: [0x65,0x04,0x0a,0x62]
3656
3657 v_min_u16 v5, flat_scratch_lo, v2
3658 // CHECK: [0x66,0x04,0x0a,0x62]
3659
3660 v_min_u16 v5, flat_scratch_hi, v2
3661 // CHECK: [0x67,0x04,0x0a,0x62]
3662
3663 v_min_u16 v5, vcc_lo, v2
3664 // CHECK: [0x6a,0x04,0x0a,0x62]
3665
3666 v_min_u16 v5, vcc_hi, v2
3667 // CHECK: [0x6b,0x04,0x0a,0x62]
3668
3669 v_min_u16 v5, tba_lo, v2
3670 // CHECK: [0x6c,0x04,0x0a,0x62]
3671
3672 v_min_u16 v5, tba_hi, v2
3673 // CHECK: [0x6d,0x04,0x0a,0x62]
3674
3675 v_min_u16 v5, tma_lo, v2
3676 // CHECK: [0x6e,0x04,0x0a,0x62]
3677
3678 v_min_u16 v5, tma_hi, v2
3679 // CHECK: [0x6f,0x04,0x0a,0x62]
3680
3681 v_min_u16 v5, ttmp11, v2
3682 // CHECK: [0x7b,0x04,0x0a,0x62]
3683
3684 v_min_u16 v5, m0, v2
3685 // CHECK: [0x7c,0x04,0x0a,0x62]
3686
3687 v_min_u16 v5, exec_lo, v2
3688 // CHECK: [0x7e,0x04,0x0a,0x62]
3689
3690 v_min_u16 v5, exec_hi, v2
3691 // CHECK: [0x7f,0x04,0x0a,0x62]
3692
3693 v_min_u16 v5, 0, v2
3694 // CHECK: [0x80,0x04,0x0a,0x62]
3695
3696 v_min_u16 v5, -1, v2
3697 // CHECK: [0xc1,0x04,0x0a,0x62]
3698
3699 v_min_u16 v5, 0.5, v2
3700 // CHECK: [0xf0,0x04,0x0a,0x62]
3701
3702 v_min_u16 v5, -4.0, v2
3703 // CHECK: [0xf7,0x04,0x0a,0x62]
3704
3705 v_min_u16 v5, src_vccz, v2
3706 // CHECK: [0xfb,0x04,0x0a,0x62]
3707
3708 v_min_u16 v5, src_execz, v2
3709 // CHECK: [0xfc,0x04,0x0a,0x62]
3710
3711 v_min_u16 v5, src_scc, v2
3712 // CHECK: [0xfd,0x04,0x0a,0x62]
3713
3714 v_min_u16 v5, src_lds_direct, v2
3715 // CHECK: [0xfe,0x04,0x0a,0x62]
3716
3717 v_min_u16 v5, 0xfe0b, v2
3718 // CHECK: [0xff,0x04,0x0a,0x62,0x0b,0xfe,0x00,0x00]
3719
3720 v_min_u16 v5, 0x3456, v2
3721 // CHECK: [0xff,0x04,0x0a,0x62,0x56,0x34,0x00,0x00]
3722
3723 v_min_u16 v5, v1, v255
3724 // CHECK: [0x01,0xff,0x0b,0x62]
3725
3726 v_min_i16 v5, v1, v2
3727 // CHECK: [0x01,0x05,0x0a,0x64]
3728
3729 v_min_i16 v255, v1, v2
3730 // CHECK: [0x01,0x05,0xfe,0x65]
3731
3732 v_min_i16 v5, v255, v2
3733 // CHECK: [0xff,0x05,0x0a,0x64]
3734
3735 v_min_i16 v5, s1, v2
3736 // CHECK: [0x01,0x04,0x0a,0x64]
3737
3738 v_min_i16 v5, s101, v2
3739 // CHECK: [0x65,0x04,0x0a,0x64]
3740
3741 v_min_i16 v5, flat_scratch_lo, v2
3742 // CHECK: [0x66,0x04,0x0a,0x64]
3743
3744 v_min_i16 v5, flat_scratch_hi, v2
3745 // CHECK: [0x67,0x04,0x0a,0x64]
3746
3747 v_min_i16 v5, vcc_lo, v2
3748 // CHECK: [0x6a,0x04,0x0a,0x64]
3749
3750 v_min_i16 v5, vcc_hi, v2
3751 // CHECK: [0x6b,0x04,0x0a,0x64]
3752
3753 v_min_i16 v5, tba_lo, v2
3754 // CHECK: [0x6c,0x04,0x0a,0x64]
3755
3756 v_min_i16 v5, tba_hi, v2
3757 // CHECK: [0x6d,0x04,0x0a,0x64]
3758
3759 v_min_i16 v5, tma_lo, v2
3760 // CHECK: [0x6e,0x04,0x0a,0x64]
3761
3762 v_min_i16 v5, tma_hi, v2
3763 // CHECK: [0x6f,0x04,0x0a,0x64]
3764
3765 v_min_i16 v5, ttmp11, v2
3766 // CHECK: [0x7b,0x04,0x0a,0x64]
3767
3768 v_min_i16 v5, m0, v2
3769 // CHECK: [0x7c,0x04,0x0a,0x64]
3770
3771 v_min_i16 v5, exec_lo, v2
3772 // CHECK: [0x7e,0x04,0x0a,0x64]
3773
3774 v_min_i16 v5, exec_hi, v2
3775 // CHECK: [0x7f,0x04,0x0a,0x64]
3776
3777 v_min_i16 v5, 0, v2
3778 // CHECK: [0x80,0x04,0x0a,0x64]
3779
3780 v_min_i16 v5, -1, v2
3781 // CHECK: [0xc1,0x04,0x0a,0x64]
3782
3783 v_min_i16 v5, 0.5, v2
3784 // CHECK: [0xf0,0x04,0x0a,0x64]
3785
3786 v_min_i16 v5, -4.0, v2
3787 // CHECK: [0xf7,0x04,0x0a,0x64]
3788
3789 v_min_i16 v5, src_vccz, v2
3790 // CHECK: [0xfb,0x04,0x0a,0x64]
3791
3792 v_min_i16 v5, src_execz, v2
3793 // CHECK: [0xfc,0x04,0x0a,0x64]
3794
3795 v_min_i16 v5, src_scc, v2
3796 // CHECK: [0xfd,0x04,0x0a,0x64]
3797
3798 v_min_i16 v5, src_lds_direct, v2
3799 // CHECK: [0xfe,0x04,0x0a,0x64]
3800
3801 v_min_i16 v5, 0xfe0b, v2
3802 // CHECK: [0xff,0x04,0x0a,0x64,0x0b,0xfe,0x00,0x00]
3803
3804 v_min_i16 v5, 0x3456, v2
3805 // CHECK: [0xff,0x04,0x0a,0x64,0x56,0x34,0x00,0x00]
3806
3807 v_min_i16 v5, v1, v255
3808 // CHECK: [0x01,0xff,0x0b,0x64]
3809
3810 v_ldexp_f16 v5, v1, v2
3811 // CHECK: [0x01,0x05,0x0a,0x66]
3812
3813 v_ldexp_f16 v255, v1, v2
3814 // CHECK: [0x01,0x05,0xfe,0x67]
3815
3816 v_ldexp_f16 v5, v255, v2
3817 // CHECK: [0xff,0x05,0x0a,0x66]
3818
3819 v_ldexp_f16 v5, s1, v2
3820 // CHECK: [0x01,0x04,0x0a,0x66]
3821
3822 v_ldexp_f16 v5, s101, v2
3823 // CHECK: [0x65,0x04,0x0a,0x66]
3824
3825 v_ldexp_f16 v5, flat_scratch_lo, v2
3826 // CHECK: [0x66,0x04,0x0a,0x66]
3827
3828 v_ldexp_f16 v5, flat_scratch_hi, v2
3829 // CHECK: [0x67,0x04,0x0a,0x66]
3830
3831 v_ldexp_f16 v5, vcc_lo, v2
3832 // CHECK: [0x6a,0x04,0x0a,0x66]
3833
3834 v_ldexp_f16 v5, vcc_hi, v2
3835 // CHECK: [0x6b,0x04,0x0a,0x66]
3836
3837 v_ldexp_f16 v5, tba_lo, v2
3838 // CHECK: [0x6c,0x04,0x0a,0x66]
3839
3840 v_ldexp_f16 v5, tba_hi, v2
3841 // CHECK: [0x6d,0x04,0x0a,0x66]
3842
3843 v_ldexp_f16 v5, tma_lo, v2
3844 // CHECK: [0x6e,0x04,0x0a,0x66]
3845
3846 v_ldexp_f16 v5, tma_hi, v2
3847 // CHECK: [0x6f,0x04,0x0a,0x66]
3848
3849 v_ldexp_f16 v5, ttmp11, v2
3850 // CHECK: [0x7b,0x04,0x0a,0x66]
3851
3852 v_ldexp_f16 v5, m0, v2
3853 // CHECK: [0x7c,0x04,0x0a,0x66]
3854
3855 v_ldexp_f16 v5, exec_lo, v2
3856 // CHECK: [0x7e,0x04,0x0a,0x66]
3857
3858 v_ldexp_f16 v5, exec_hi, v2
3859 // CHECK: [0x7f,0x04,0x0a,0x66]
3860
3861 v_ldexp_f16 v5, 0, v2
3862 // CHECK: [0x80,0x04,0x0a,0x66]
3863
3864 v_ldexp_f16 v5, -1, v2
3865 // CHECK: [0xc1,0x04,0x0a,0x66]
3866
3867 v_ldexp_f16 v5, 0.5, v2
3868 // CHECK: [0xf0,0x04,0x0a,0x66]
3869
3870 v_ldexp_f16 v5, -4.0, v2
3871 // CHECK: [0xf7,0x04,0x0a,0x66]
3872
3873 v_ldexp_f16 v5, src_vccz, v2
3874 // CHECK: [0xfb,0x04,0x0a,0x66]
3875
3876 v_ldexp_f16 v5, src_execz, v2
3877 // CHECK: [0xfc,0x04,0x0a,0x66]
3878
3879 v_ldexp_f16 v5, src_scc, v2
3880 // CHECK: [0xfd,0x04,0x0a,0x66]
3881
3882 v_ldexp_f16 v5, src_lds_direct, v2
3883 // CHECK: [0xfe,0x04,0x0a,0x66]
3884
3885 v_ldexp_f16 v5, 0xfe0b, v2
3886 // CHECK: [0xff,0x04,0x0a,0x66,0x0b,0xfe,0x00,0x00]
3887
3888 v_ldexp_f16 v5, 0x3456, v2
3889 // CHECK: [0xff,0x04,0x0a,0x66,0x56,0x34,0x00,0x00]
3890
3891 v_ldexp_f16 v5, v1, v255
3892 // CHECK: [0x01,0xff,0x0b,0x66]
3893
3894 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3895 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
3896
3897 v_cndmask_b32_sdwa v255, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3898 // CHECK: [0xf9,0x04,0xfe,0x01,0x01,0x06,0x06,0x06]
3899
3900 v_cndmask_b32_sdwa v5, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3901 // CHECK: [0xf9,0x04,0x0a,0x00,0xff,0x06,0x06,0x06]
3902
3903 v_cndmask_b32_sdwa v5, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3904 // CHECK: [0xf9,0xfe,0x0b,0x00,0x01,0x06,0x06,0x06]
3905
3906 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3907 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
3908
3909 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3910 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x00,0x06,0x06]
3911
3912 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3913 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x01,0x06,0x06]
3914
3915 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3916 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x02,0x06,0x06]
3917
3918 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3919 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x03,0x06,0x06]
3920
3921 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3922 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x04,0x06,0x06]
3923
3924 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3925 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x05,0x06,0x06]
3926
3927 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
3928 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x0e,0x06,0x06]
3929
3930 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
3931 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x16,0x06,0x06]
3932
3933 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
3934 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x16,0x06,0x06]
3935
3936 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
3937 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
3938
3939 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
3940 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x00,0x06]
3941
3942 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
3943 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x01,0x06]
3944
3945 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
3946 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x02,0x06]
3947
3948 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
3949 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x03,0x06]
3950
3951 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
3952 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x04,0x06]
3953
3954 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
3955 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x05,0x06]
3956
3957 v_cndmask_b32_sdwa v5, |v1|, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3958 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x26,0x06]
3959
3960 v_cndmask_b32_sdwa v5, -v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3961 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x16,0x06]
3962
3963 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
3964 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
3965
3966 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
3967 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x00]
3968
3969 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
3970 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x01]
3971
3972 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
3973 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x02]
3974
3975 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
3976 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x03]
3977
3978 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
3979 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x04]
3980
3981 v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
3982 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x05]
3983
3984 v_cndmask_b32_sdwa v5, v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3985 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x26]
3986
3987 v_cndmask_b32_sdwa v5, v1, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
3988 // CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x16]
3989
3990 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
3991 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00]
3992
3993 v_cndmask_b32_dpp v255, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
3994 // CHECK: [0xfa,0x04,0xfe,0x01,0x01,0xe4,0x00,0x00]
3995
3996 v_cndmask_b32_dpp v5, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
3997 // CHECK: [0xfa,0x04,0x0a,0x00,0xff,0xe4,0x00,0x00]
3998
3999 v_cndmask_b32_dpp v5, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4000 // CHECK: [0xfa,0xfe,0x0b,0x00,0x01,0xe4,0x00,0x00]
4001
4002 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
4003 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x1b,0x00,0x00]
4004
4005 v_cndmask_b32_dpp v5, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
4006 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x40,0x01,0x00]
4007
4008 v_cndmask_b32_dpp v5, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
4009 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x41,0x01,0x00]
4010
4011 v_cndmask_b32_dpp v5, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
4012 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x42,0x01,0x00]
4013
4014 v_cndmask_b32_dpp v5, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
4015 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x43,0x01,0x00]
4016
4017 v_cndmask_b32_dpp v5, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
4018 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x30,0x01,0x00]
4019
4020 v_cndmask_b32_dpp v5, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
4021 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x34,0x01,0x00]
4022
4023 v_cndmask_b32_dpp v5, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
4024 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x38,0x01,0x00]
4025
4026 v_cndmask_b32_dpp v5, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
4027 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x3c,0x01,0x00]
4028
4029 v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
4030 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x01,0x01,0x00]
4031
4032 v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
4033 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x0f,0x01,0x00]
4034
4035 v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
4036 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x11,0x01,0x00]
4037
4038 v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
4039 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x1f,0x01,0x00]
4040
4041 v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
4042 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x21,0x01,0x00]
4043
4044 v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
4045 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x2f,0x01,0x00]
4046
4047 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
4048 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x10]
4049
4050 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
4051 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x30]
4052
4053 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
4054 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0xf0]
4055
4056 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
4057 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0xf0]
4058
4059 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
4060 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x01]
4061
4062 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
4063 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x03]
4064
4065 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
4066 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x0f]
4067
4068 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
4069 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x0f]
4070
4071 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
4072 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x08,0x00]
4073
4074 v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
4075 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x98,0x00]
4076
4077 v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
4078 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x68,0x00]
4079
4080 v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
4081 // CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0xf8,0x00]
4082
4083 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4084 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
4085
4086 v_add_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4087 // CHECK: [0xf9,0x04,0xfe,0x03,0x01,0x06,0x06,0x06]
4088
4089 v_add_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4090 // CHECK: [0xf9,0x04,0x0a,0x02,0xff,0x06,0x06,0x06]
4091
4092 v_add_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4093 // CHECK: [0xf9,0xfe,0x0b,0x02,0x01,0x06,0x06,0x06]
4094
4095 v_add_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4096 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x26,0x06,0x06]
4097
4098 v_add_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4099 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
4100
4101 v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4102 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x00,0x06,0x06]
4103
4104 v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4105 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x01,0x06,0x06]
4106
4107 v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4108 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x02,0x06,0x06]
4109
4110 v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4111 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x03,0x06,0x06]
4112
4113 v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4114 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x04,0x06,0x06]
4115
4116 v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4117 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x05,0x06,0x06]
4118
4119 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
4120 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x0e,0x06,0x06]
4121
4122 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
4123 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
4124
4125 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
4126 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
4127
4128 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
4129 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
4130
4131 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
4132 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x00,0x06]
4133
4134 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
4135 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x01,0x06]
4136
4137 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
4138 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x02,0x06]
4139
4140 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
4141 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x03,0x06]
4142
4143 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
4144 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x04,0x06]
4145
4146 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
4147 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x05,0x06]
4148
4149 v_add_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4150 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x16,0x06]
4151
4152 v_add_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4153 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x26,0x06]
4154
4155 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
4156 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
4157
4158 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
4159 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x00]
4160
4161 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
4162 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x01]
4163
4164 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
4165 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x02]
4166
4167 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
4168 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x03]
4169
4170 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
4171 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x04]
4172
4173 v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4174 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x05]
4175
4176 v_add_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4177 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x16]
4178
4179 v_add_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4180 // CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x26]
4181
4182 v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4183 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00]
4184
4185 v_add_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4186 // CHECK: [0xfa,0x04,0xfe,0x03,0x01,0xe4,0x00,0x00]
4187
4188 v_add_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4189 // CHECK: [0xfa,0x04,0x0a,0x02,0xff,0xe4,0x00,0x00]
4190
4191 v_add_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4192 // CHECK: [0xfa,0xfe,0x0b,0x02,0x01,0xe4,0x00,0x00]
4193
4194 v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
4195 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0x00]
4196
4197 v_add_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
4198 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0x00]
4199
4200 v_add_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
4201 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0x00]
4202
4203 v_add_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
4204 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x42,0x01,0x00]
4205
4206 v_add_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
4207 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x43,0x01,0x00]
4208
4209 v_add_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
4210 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x30,0x01,0x00]
4211
4212 v_add_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
4213 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x34,0x01,0x00]
4214
4215 v_add_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
4216 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x38,0x01,0x00]
4217
4218 v_add_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
4219 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x3c,0x01,0x00]
4220
4221 v_add_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
4222 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0x00]
4223
4224 v_add_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
4225 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0x00]
4226
4227 v_add_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
4228 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0x00]
4229
4230 v_add_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
4231 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0x00]
4232
4233 v_add_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
4234 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0x00]
4235
4236 v_add_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
4237 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0x00]
4238
4239 v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
4240 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x10]
4241
4242 v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
4243 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x30]
4244
4245 v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
4246 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xf0]
4247
4248 v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
4249 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xf0]
4250
4251 v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
4252 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x01]
4253
4254 v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
4255 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x03]
4256
4257 v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
4258 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f]
4259
4260 v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
4261 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f]
4262
4263 v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
4264 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x08,0x00]
4265
4266 v_add_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4267 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x10,0x00]
4268
4269 v_add_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4270 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x20,0x00]
4271
4272 v_add_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4273 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x40,0x00]
4274
4275 v_add_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4276 // CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x80,0x00]
4277
4278 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4279 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
4280
4281 v_sub_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4282 // CHECK: [0xf9,0x04,0xfe,0x05,0x01,0x06,0x06,0x06]
4283
4284 v_sub_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4285 // CHECK: [0xf9,0x04,0x0a,0x04,0xff,0x06,0x06,0x06]
4286
4287 v_sub_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4288 // CHECK: [0xf9,0xfe,0x0b,0x04,0x01,0x06,0x06,0x06]
4289
4290 v_sub_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4291 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x26,0x06,0x06]
4292
4293 v_sub_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4294 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
4295
4296 v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4297 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x00,0x06,0x06]
4298
4299 v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4300 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x01,0x06,0x06]
4301
4302 v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4303 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x02,0x06,0x06]
4304
4305 v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4306 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x03,0x06,0x06]
4307
4308 v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4309 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x04,0x06,0x06]
4310
4311 v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4312 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x05,0x06,0x06]
4313
4314 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
4315 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x0e,0x06,0x06]
4316
4317 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
4318 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x16,0x06,0x06]
4319
4320 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
4321 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x16,0x06,0x06]
4322
4323 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
4324 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
4325
4326 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
4327 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x00,0x06]
4328
4329 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
4330 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x01,0x06]
4331
4332 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
4333 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x02,0x06]
4334
4335 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
4336 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x03,0x06]
4337
4338 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
4339 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x04,0x06]
4340
4341 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
4342 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x05,0x06]
4343
4344 v_sub_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4345 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x16,0x06]
4346
4347 v_sub_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4348 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x26,0x06]
4349
4350 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
4351 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
4352
4353 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
4354 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x00]
4355
4356 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
4357 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x01]
4358
4359 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
4360 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x02]
4361
4362 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
4363 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x03]
4364
4365 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
4366 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x04]
4367
4368 v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4369 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x05]
4370
4371 v_sub_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4372 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x16]
4373
4374 v_sub_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4375 // CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x26]
4376
4377 v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4378 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x00]
4379
4380 v_sub_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4381 // CHECK: [0xfa,0x04,0xfe,0x05,0x01,0xe4,0x00,0x00]
4382
4383 v_sub_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4384 // CHECK: [0xfa,0x04,0x0a,0x04,0xff,0xe4,0x00,0x00]
4385
4386 v_sub_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4387 // CHECK: [0xfa,0xfe,0x0b,0x04,0x01,0xe4,0x00,0x00]
4388
4389 v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
4390 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0x00]
4391
4392 v_sub_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
4393 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0x00]
4394
4395 v_sub_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
4396 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0x00]
4397
4398 v_sub_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
4399 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x42,0x01,0x00]
4400
4401 v_sub_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
4402 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x43,0x01,0x00]
4403
4404 v_sub_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
4405 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x30,0x01,0x00]
4406
4407 v_sub_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
4408 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x34,0x01,0x00]
4409
4410 v_sub_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
4411 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x38,0x01,0x00]
4412
4413 v_sub_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
4414 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x3c,0x01,0x00]
4415
4416 v_sub_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
4417 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0x00]
4418
4419 v_sub_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
4420 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0x00]
4421
4422 v_sub_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
4423 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0x00]
4424
4425 v_sub_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
4426 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0x00]
4427
4428 v_sub_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
4429 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0x00]
4430
4431 v_sub_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
4432 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0x00]
4433
4434 v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
4435 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x10]
4436
4437 v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
4438 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x30]
4439
4440 v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
4441 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
4442
4443 v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
4444 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
4445
4446 v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
4447 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x01]
4448
4449 v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
4450 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03]
4451
4452 v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
4453 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
4454
4455 v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
4456 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
4457
4458 v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
4459 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
4460
4461 v_sub_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4462 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00]
4463
4464 v_sub_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4465 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00]
4466
4467 v_sub_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4468 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x40,0x00]
4469
4470 v_sub_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4471 // CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x80,0x00]
4472
4473 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4474 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
4475
4476 v_subrev_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4477 // CHECK: [0xf9,0x04,0xfe,0x07,0x01,0x06,0x06,0x06]
4478
4479 v_subrev_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4480 // CHECK: [0xf9,0x04,0x0a,0x06,0xff,0x06,0x06,0x06]
4481
4482 v_subrev_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4483 // CHECK: [0xf9,0xfe,0x0b,0x06,0x01,0x06,0x06,0x06]
4484
4485 v_subrev_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4486 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x26,0x06,0x06]
4487
4488 v_subrev_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4489 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
4490
4491 v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4492 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x00,0x06,0x06]
4493
4494 v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4495 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x01,0x06,0x06]
4496
4497 v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4498 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x02,0x06,0x06]
4499
4500 v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4501 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x03,0x06,0x06]
4502
4503 v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4504 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x04,0x06,0x06]
4505
4506 v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4507 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x05,0x06,0x06]
4508
4509 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
4510 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x0e,0x06,0x06]
4511
4512 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
4513 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
4514
4515 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
4516 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
4517
4518 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
4519 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
4520
4521 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
4522 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x00,0x06]
4523
4524 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
4525 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x01,0x06]
4526
4527 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
4528 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x02,0x06]
4529
4530 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
4531 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x03,0x06]
4532
4533 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
4534 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x04,0x06]
4535
4536 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
4537 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x05,0x06]
4538
4539 v_subrev_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4540 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x16,0x06]
4541
4542 v_subrev_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4543 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x26,0x06]
4544
4545 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
4546 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
4547
4548 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
4549 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x00]
4550
4551 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
4552 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x01]
4553
4554 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
4555 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x02]
4556
4557 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
4558 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x03]
4559
4560 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
4561 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x04]
4562
4563 v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4564 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x05]
4565
4566 v_subrev_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4567 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x16]
4568
4569 v_subrev_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4570 // CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x26]
4571
4572 v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4573 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x00]
4574
4575 v_subrev_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4576 // CHECK: [0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0x00]
4577
4578 v_subrev_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4579 // CHECK: [0xfa,0x04,0x0a,0x06,0xff,0xe4,0x00,0x00]
4580
4581 v_subrev_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4582 // CHECK: [0xfa,0xfe,0x0b,0x06,0x01,0xe4,0x00,0x00]
4583
4584 v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
4585 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0x00]
4586
4587 v_subrev_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
4588 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0x00]
4589
4590 v_subrev_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
4591 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0x00]
4592
4593 v_subrev_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
4594 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x42,0x01,0x00]
4595
4596 v_subrev_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
4597 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x43,0x01,0x00]
4598
4599 v_subrev_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
4600 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x30,0x01,0x00]
4601
4602 v_subrev_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
4603 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x34,0x01,0x00]
4604
4605 v_subrev_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
4606 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x38,0x01,0x00]
4607
4608 v_subrev_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
4609 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x3c,0x01,0x00]
4610
4611 v_subrev_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
4612 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0x00]
4613
4614 v_subrev_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
4615 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0x00]
4616
4617 v_subrev_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
4618 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0x00]
4619
4620 v_subrev_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
4621 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0x00]
4622
4623 v_subrev_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
4624 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0x00]
4625
4626 v_subrev_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
4627 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0x00]
4628
4629 v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
4630 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x10]
4631
4632 v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
4633 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x30]
4634
4635 v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
4636 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xf0]
4637
4638 v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
4639 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xf0]
4640
4641 v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
4642 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x01]
4643
4644 v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
4645 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03]
4646
4647 v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
4648 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
4649
4650 v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
4651 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
4652
4653 v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
4654 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
4655
4656 v_subrev_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4657 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x10,0x00]
4658
4659 v_subrev_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4660 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x20,0x00]
4661
4662 v_subrev_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4663 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x40,0x00]
4664
4665 v_subrev_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4666 // CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x80,0x00]
4667
4668 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4669 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
4670
4671 v_mul_legacy_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4672 // CHECK: [0xf9,0x04,0xfe,0x09,0x01,0x06,0x06,0x06]
4673
4674 v_mul_legacy_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4675 // CHECK: [0xf9,0x04,0x0a,0x08,0xff,0x06,0x06,0x06]
4676
4677 v_mul_legacy_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4678 // CHECK: [0xf9,0xfe,0x0b,0x08,0x01,0x06,0x06,0x06]
4679
4680 v_mul_legacy_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4681 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x26,0x06,0x06]
4682
4683 v_mul_legacy_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4684 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
4685
4686 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4687 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x00,0x06,0x06]
4688
4689 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4690 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x01,0x06,0x06]
4691
4692 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4693 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x02,0x06,0x06]
4694
4695 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4696 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x03,0x06,0x06]
4697
4698 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4699 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x04,0x06,0x06]
4700
4701 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4702 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x05,0x06,0x06]
4703
4704 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
4705 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x0e,0x06,0x06]
4706
4707 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
4708 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
4709
4710 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
4711 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
4712
4713 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
4714 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
4715
4716 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
4717 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x00,0x06]
4718
4719 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
4720 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x01,0x06]
4721
4722 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
4723 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x02,0x06]
4724
4725 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
4726 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x03,0x06]
4727
4728 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
4729 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x04,0x06]
4730
4731 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
4732 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x05,0x06]
4733
4734 v_mul_legacy_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4735 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x16,0x06]
4736
4737 v_mul_legacy_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4738 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x26,0x06]
4739
4740 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
4741 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
4742
4743 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
4744 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x00]
4745
4746 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
4747 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x01]
4748
4749 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
4750 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x02]
4751
4752 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
4753 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x03]
4754
4755 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
4756 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x04]
4757
4758 v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4759 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x05]
4760
4761 v_mul_legacy_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4762 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x16]
4763
4764 v_mul_legacy_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4765 // CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x26]
4766
4767 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4768 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x00]
4769
4770 v_mul_legacy_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4771 // CHECK: [0xfa,0x04,0xfe,0x09,0x01,0xe4,0x00,0x00]
4772
4773 v_mul_legacy_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4774 // CHECK: [0xfa,0x04,0x0a,0x08,0xff,0xe4,0x00,0x00]
4775
4776 v_mul_legacy_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4777 // CHECK: [0xfa,0xfe,0x0b,0x08,0x01,0xe4,0x00,0x00]
4778
4779 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
4780 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0x00]
4781
4782 v_mul_legacy_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
4783 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0x00]
4784
4785 v_mul_legacy_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
4786 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0x00]
4787
4788 v_mul_legacy_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
4789 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x42,0x01,0x00]
4790
4791 v_mul_legacy_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
4792 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x43,0x01,0x00]
4793
4794 v_mul_legacy_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
4795 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x30,0x01,0x00]
4796
4797 v_mul_legacy_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
4798 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x34,0x01,0x00]
4799
4800 v_mul_legacy_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
4801 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x38,0x01,0x00]
4802
4803 v_mul_legacy_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
4804 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x3c,0x01,0x00]
4805
4806 v_mul_legacy_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
4807 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0x00]
4808
4809 v_mul_legacy_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
4810 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0x00]
4811
4812 v_mul_legacy_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
4813 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0x00]
4814
4815 v_mul_legacy_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
4816 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0x00]
4817
4818 v_mul_legacy_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
4819 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0x00]
4820
4821 v_mul_legacy_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
4822 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0x00]
4823
4824 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
4825 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x10]
4826
4827 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
4828 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x30]
4829
4830 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
4831 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xf0]
4832
4833 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
4834 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xf0]
4835
4836 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
4837 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x01]
4838
4839 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
4840 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03]
4841
4842 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
4843 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
4844
4845 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
4846 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
4847
4848 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
4849 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
4850
4851 v_mul_legacy_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4852 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x10,0x00]
4853
4854 v_mul_legacy_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4855 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x20,0x00]
4856
4857 v_mul_legacy_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4858 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x40,0x00]
4859
4860 v_mul_legacy_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4861 // CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x80,0x00]
4862
4863 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4864 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
4865
4866 v_mul_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4867 // CHECK: [0xf9,0x04,0xfe,0x0b,0x01,0x06,0x06,0x06]
4868
4869 v_mul_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4870 // CHECK: [0xf9,0x04,0x0a,0x0a,0xff,0x06,0x06,0x06]
4871
4872 v_mul_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4873 // CHECK: [0xf9,0xfe,0x0b,0x0a,0x01,0x06,0x06,0x06]
4874
4875 v_mul_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4876 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x26,0x06,0x06]
4877
4878 v_mul_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4879 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
4880
4881 v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4882 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x00,0x06,0x06]
4883
4884 v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4885 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x01,0x06,0x06]
4886
4887 v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4888 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x02,0x06,0x06]
4889
4890 v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4891 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x03,0x06,0x06]
4892
4893 v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4894 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x04,0x06,0x06]
4895
4896 v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4897 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x05,0x06,0x06]
4898
4899 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
4900 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x0e,0x06,0x06]
4901
4902 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
4903 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
4904
4905 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
4906 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
4907
4908 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
4909 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
4910
4911 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
4912 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x00,0x06]
4913
4914 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
4915 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x01,0x06]
4916
4917 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
4918 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x02,0x06]
4919
4920 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
4921 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x03,0x06]
4922
4923 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
4924 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x04,0x06]
4925
4926 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
4927 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x05,0x06]
4928
4929 v_mul_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4930 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x16,0x06]
4931
4932 v_mul_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4933 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x26,0x06]
4934
4935 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
4936 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
4937
4938 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
4939 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x00]
4940
4941 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
4942 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x01]
4943
4944 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
4945 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x02]
4946
4947 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
4948 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x03]
4949
4950 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
4951 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x04]
4952
4953 v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
4954 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x05]
4955
4956 v_mul_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4957 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x16]
4958
4959 v_mul_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
4960 // CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x26]
4961
4962 v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4963 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x00]
4964
4965 v_mul_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4966 // CHECK: [0xfa,0x04,0xfe,0x0b,0x01,0xe4,0x00,0x00]
4967
4968 v_mul_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4969 // CHECK: [0xfa,0x04,0x0a,0x0a,0xff,0xe4,0x00,0x00]
4970
4971 v_mul_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
4972 // CHECK: [0xfa,0xfe,0x0b,0x0a,0x01,0xe4,0x00,0x00]
4973
4974 v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
4975 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0x00]
4976
4977 v_mul_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
4978 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0x00]
4979
4980 v_mul_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
4981 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0x00]
4982
4983 v_mul_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
4984 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x42,0x01,0x00]
4985
4986 v_mul_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
4987 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x43,0x01,0x00]
4988
4989 v_mul_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
4990 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x30,0x01,0x00]
4991
4992 v_mul_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
4993 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x34,0x01,0x00]
4994
4995 v_mul_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
4996 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x38,0x01,0x00]
4997
4998 v_mul_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
4999 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x3c,0x01,0x00]
5000
5001 v_mul_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
5002 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0x00]
5003
5004 v_mul_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
5005 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0x00]
5006
5007 v_mul_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
5008 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0x00]
5009
5010 v_mul_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
5011 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0x00]
5012
5013 v_mul_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
5014 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0x00]
5015
5016 v_mul_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
5017 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0x00]
5018
5019 v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
5020 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x10]
5021
5022 v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
5023 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x30]
5024
5025 v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
5026 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xf0]
5027
5028 v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
5029 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xf0]
5030
5031 v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
5032 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x01]
5033
5034 v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
5035 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03]
5036
5037 v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
5038 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
5039
5040 v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
5041 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
5042
5043 v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
5044 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
5045
5046 v_mul_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5047 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x10,0x00]
5048
5049 v_mul_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5050 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x20,0x00]
5051
5052 v_mul_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5053 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x40,0x00]
5054
5055 v_mul_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5056 // CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x80,0x00]
5057
5058 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5059 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
5060
5061 v_mul_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5062 // CHECK: [0xf9,0x04,0xfe,0x0d,0x01,0x06,0x06,0x06]
5063
5064 v_mul_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5065 // CHECK: [0xf9,0x04,0x0a,0x0c,0xff,0x06,0x06,0x06]
5066
5067 v_mul_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5068 // CHECK: [0xf9,0xfe,0x0b,0x0c,0x01,0x06,0x06,0x06]
5069
5070 v_mul_i32_i24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5071 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x26,0x06,0x06]
5072
5073 v_mul_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5074 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
5075
5076 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5077 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x00,0x06,0x06]
5078
5079 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5080 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x01,0x06,0x06]
5081
5082 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5083 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x02,0x06,0x06]
5084
5085 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5086 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x03,0x06,0x06]
5087
5088 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5089 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x04,0x06,0x06]
5090
5091 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5092 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x05,0x06,0x06]
5093
5094 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
5095 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x0e,0x06,0x06]
5096
5097 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
5098 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x16,0x06,0x06]
5099
5100 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
5101 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x16,0x06,0x06]
5102
5103 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
5104 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
5105
5106 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
5107 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x00,0x06]
5108
5109 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
5110 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x01,0x06]
5111
5112 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
5113 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x02,0x06]
5114
5115 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
5116 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x03,0x06]
5117
5118 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
5119 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x04,0x06]
5120
5121 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
5122 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x05,0x06]
5123
5124 v_mul_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5125 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x0e,0x06]
5126
5127 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
5128 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
5129
5130 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
5131 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x00]
5132
5133 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
5134 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x01]
5135
5136 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
5137 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x02]
5138
5139 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
5140 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x03]
5141
5142 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
5143 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x04]
5144
5145 v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
5146 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x05]
5147
5148 v_mul_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5149 // CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x0e]
5150
5151 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5152 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x00]
5153
5154 v_mul_i32_i24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5155 // CHECK: [0xfa,0x04,0xfe,0x0d,0x01,0xe4,0x00,0x00]
5156
5157 v_mul_i32_i24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5158 // CHECK: [0xfa,0x04,0x0a,0x0c,0xff,0xe4,0x00,0x00]
5159
5160 v_mul_i32_i24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5161 // CHECK: [0xfa,0xfe,0x0b,0x0c,0x01,0xe4,0x00,0x00]
5162
5163 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
5164 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x1b,0x00,0x00]
5165
5166 v_mul_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
5167 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x40,0x01,0x00]
5168
5169 v_mul_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
5170 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x41,0x01,0x00]
5171
5172 v_mul_i32_i24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
5173 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x42,0x01,0x00]
5174
5175 v_mul_i32_i24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
5176 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x43,0x01,0x00]
5177
5178 v_mul_i32_i24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
5179 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x30,0x01,0x00]
5180
5181 v_mul_i32_i24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
5182 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x34,0x01,0x00]
5183
5184 v_mul_i32_i24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
5185 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x38,0x01,0x00]
5186
5187 v_mul_i32_i24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
5188 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x3c,0x01,0x00]
5189
5190 v_mul_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
5191 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x01,0x01,0x00]
5192
5193 v_mul_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
5194 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x0f,0x01,0x00]
5195
5196 v_mul_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
5197 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x11,0x01,0x00]
5198
5199 v_mul_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
5200 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x1f,0x01,0x00]
5201
5202 v_mul_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
5203 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x21,0x01,0x00]
5204
5205 v_mul_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
5206 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x2f,0x01,0x00]
5207
5208 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
5209 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x10]
5210
5211 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
5212 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x30]
5213
5214 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
5215 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0xf0]
5216
5217 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
5218 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0xf0]
5219
5220 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
5221 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x01]
5222
5223 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
5224 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x03]
5225
5226 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
5227 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f]
5228
5229 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
5230 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f]
5231
5232 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
5233 // CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x08,0x00]
5234
5235 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5236 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
5237
5238 v_mul_hi_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5239 // CHECK: [0xf9,0x04,0xfe,0x0f,0x01,0x06,0x06,0x06]
5240
5241 v_mul_hi_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5242 // CHECK: [0xf9,0x04,0x0a,0x0e,0xff,0x06,0x06,0x06]
5243
5244 v_mul_hi_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5245 // CHECK: [0xf9,0xfe,0x0b,0x0e,0x01,0x06,0x06,0x06]
5246
5247 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5248 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
5249
5250 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5251 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x00,0x06,0x06]
5252
5253 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5254 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x01,0x06,0x06]
5255
5256 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5257 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x02,0x06,0x06]
5258
5259 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5260 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x03,0x06,0x06]
5261
5262 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5263 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x04,0x06,0x06]
5264
5265 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5266 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x05,0x06,0x06]
5267
5268 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
5269 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x0e,0x06,0x06]
5270
5271 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
5272 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
5273
5274 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
5275 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
5276
5277 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
5278 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
5279
5280 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
5281 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x00,0x06]
5282
5283 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
5284 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x01,0x06]
5285
5286 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
5287 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x02,0x06]
5288
5289 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
5290 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x03,0x06]
5291
5292 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
5293 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x04,0x06]
5294
5295 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
5296 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x05,0x06]
5297
5298 v_mul_hi_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5299 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x0e,0x06]
5300
5301 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
5302 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
5303
5304 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
5305 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x00]
5306
5307 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
5308 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x01]
5309
5310 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
5311 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x02]
5312
5313 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
5314 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x03]
5315
5316 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
5317 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x04]
5318
5319 v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
5320 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x05]
5321
5322 v_mul_hi_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5323 // CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x0e]
5324
5325 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5326 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x00]
5327
5328 v_mul_hi_i32_i24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5329 // CHECK: [0xfa,0x04,0xfe,0x0f,0x01,0xe4,0x00,0x00]
5330
5331 v_mul_hi_i32_i24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5332 // CHECK: [0xfa,0x04,0x0a,0x0e,0xff,0xe4,0x00,0x00]
5333
5334 v_mul_hi_i32_i24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5335 // CHECK: [0xfa,0xfe,0x0b,0x0e,0x01,0xe4,0x00,0x00]
5336
5337 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
5338 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0x00]
5339
5340 v_mul_hi_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
5341 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0x00]
5342
5343 v_mul_hi_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
5344 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0x00]
5345
5346 v_mul_hi_i32_i24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
5347 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x42,0x01,0x00]
5348
5349 v_mul_hi_i32_i24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
5350 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x43,0x01,0x00]
5351
5352 v_mul_hi_i32_i24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
5353 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x30,0x01,0x00]
5354
5355 v_mul_hi_i32_i24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
5356 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x34,0x01,0x00]
5357
5358 v_mul_hi_i32_i24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
5359 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x38,0x01,0x00]
5360
5361 v_mul_hi_i32_i24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
5362 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x3c,0x01,0x00]
5363
5364 v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
5365 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0x00]
5366
5367 v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
5368 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0x00]
5369
5370 v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
5371 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0x00]
5372
5373 v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
5374 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0x00]
5375
5376 v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
5377 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0x00]
5378
5379 v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
5380 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0x00]
5381
5382 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
5383 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x10]
5384
5385 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
5386 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x30]
5387
5388 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
5389 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xf0]
5390
5391 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
5392 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xf0]
5393
5394 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
5395 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x01]
5396
5397 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
5398 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03]
5399
5400 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
5401 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
5402
5403 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
5404 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
5405
5406 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
5407 // CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
5408
5409 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5410 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
5411
5412 v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5413 // CHECK: [0xf9,0x04,0xfe,0x11,0x01,0x06,0x06,0x06]
5414
5415 v_mul_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5416 // CHECK: [0xf9,0x04,0x0a,0x10,0xff,0x06,0x06,0x06]
5417
5418 v_mul_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5419 // CHECK: [0xf9,0xfe,0x0b,0x10,0x01,0x06,0x06,0x06]
5420
5421 v_mul_u32_u24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5422 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x26,0x06,0x06]
5423
5424 v_mul_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5425 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
5426
5427 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5428 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x00,0x06,0x06]
5429
5430 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5431 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x01,0x06,0x06]
5432
5433 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5434 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x02,0x06,0x06]
5435
5436 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5437 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x03,0x06,0x06]
5438
5439 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5440 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x04,0x06,0x06]
5441
5442 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5443 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x05,0x06,0x06]
5444
5445 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
5446 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x0e,0x06,0x06]
5447
5448 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
5449 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
5450
5451 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
5452 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
5453
5454 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
5455 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
5456
5457 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
5458 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x00,0x06]
5459
5460 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
5461 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x01,0x06]
5462
5463 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
5464 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x02,0x06]
5465
5466 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
5467 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x03,0x06]
5468
5469 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
5470 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x04,0x06]
5471
5472 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
5473 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x05,0x06]
5474
5475 v_mul_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5476 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x0e,0x06]
5477
5478 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
5479 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
5480
5481 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
5482 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x00]
5483
5484 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
5485 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x01]
5486
5487 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
5488 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x02]
5489
5490 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
5491 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x03]
5492
5493 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
5494 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x04]
5495
5496 v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
5497 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x05]
5498
5499 v_mul_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5500 // CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x0e]
5501
5502 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5503 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x00]
5504
5505 v_mul_u32_u24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5506 // CHECK: [0xfa,0x04,0xfe,0x11,0x01,0xe4,0x00,0x00]
5507
5508 v_mul_u32_u24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5509 // CHECK: [0xfa,0x04,0x0a,0x10,0xff,0xe4,0x00,0x00]
5510
5511 v_mul_u32_u24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5512 // CHECK: [0xfa,0xfe,0x0b,0x10,0x01,0xe4,0x00,0x00]
5513
5514 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
5515 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0x00]
5516
5517 v_mul_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
5518 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0x00]
5519
5520 v_mul_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
5521 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0x00]
5522
5523 v_mul_u32_u24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
5524 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x42,0x01,0x00]
5525
5526 v_mul_u32_u24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
5527 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x43,0x01,0x00]
5528
5529 v_mul_u32_u24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
5530 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x30,0x01,0x00]
5531
5532 v_mul_u32_u24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
5533 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x34,0x01,0x00]
5534
5535 v_mul_u32_u24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
5536 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x38,0x01,0x00]
5537
5538 v_mul_u32_u24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
5539 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x3c,0x01,0x00]
5540
5541 v_mul_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
5542 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0x00]
5543
5544 v_mul_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
5545 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0x00]
5546
5547 v_mul_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
5548 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0x00]
5549
5550 v_mul_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
5551 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0x00]
5552
5553 v_mul_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
5554 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0x00]
5555
5556 v_mul_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
5557 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0x00]
5558
5559 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
5560 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x10]
5561
5562 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
5563 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x30]
5564
5565 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
5566 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xf0]
5567
5568 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
5569 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xf0]
5570
5571 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
5572 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x01]
5573
5574 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
5575 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03]
5576
5577 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
5578 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
5579
5580 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
5581 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
5582
5583 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
5584 // CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
5585
5586 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5587 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
5588
5589 v_mul_hi_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5590 // CHECK: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06]
5591
5592 v_mul_hi_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5593 // CHECK: [0xf9,0x04,0x0a,0x12,0xff,0x06,0x06,0x06]
5594
5595 v_mul_hi_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5596 // CHECK: [0xf9,0xfe,0x0b,0x12,0x01,0x06,0x06,0x06]
5597
5598 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5599 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
5600
5601 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5602 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x00,0x06,0x06]
5603
5604 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5605 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x01,0x06,0x06]
5606
5607 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5608 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x02,0x06,0x06]
5609
5610 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5611 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x03,0x06,0x06]
5612
5613 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5614 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x04,0x06,0x06]
5615
5616 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5617 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x05,0x06,0x06]
5618
5619 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
5620 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x0e,0x06,0x06]
5621
5622 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
5623 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
5624
5625 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
5626 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
5627
5628 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
5629 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
5630
5631 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
5632 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x00,0x06]
5633
5634 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
5635 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x01,0x06]
5636
5637 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
5638 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x02,0x06]
5639
5640 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
5641 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x03,0x06]
5642
5643 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
5644 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x04,0x06]
5645
5646 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
5647 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x05,0x06]
5648
5649 v_mul_hi_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5650 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x0e,0x06]
5651
5652 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
5653 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
5654
5655 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
5656 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x00]
5657
5658 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
5659 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x01]
5660
5661 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
5662 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x02]
5663
5664 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
5665 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x03]
5666
5667 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
5668 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x04]
5669
5670 v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
5671 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x05]
5672
5673 v_mul_hi_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5674 // CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x0e]
5675
5676 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5677 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x00]
5678
5679 v_mul_hi_u32_u24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5680 // CHECK: [0xfa,0x04,0xfe,0x13,0x01,0xe4,0x00,0x00]
5681
5682 v_mul_hi_u32_u24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5683 // CHECK: [0xfa,0x04,0x0a,0x12,0xff,0xe4,0x00,0x00]
5684
5685 v_mul_hi_u32_u24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5686 // CHECK: [0xfa,0xfe,0x0b,0x12,0x01,0xe4,0x00,0x00]
5687
5688 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
5689 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0x00]
5690
5691 v_mul_hi_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
5692 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0x00]
5693
5694 v_mul_hi_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
5695 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0x00]
5696
5697 v_mul_hi_u32_u24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
5698 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x42,0x01,0x00]
5699
5700 v_mul_hi_u32_u24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
5701 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x43,0x01,0x00]
5702
5703 v_mul_hi_u32_u24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
5704 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x30,0x01,0x00]
5705
5706 v_mul_hi_u32_u24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
5707 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x34,0x01,0x00]
5708
5709 v_mul_hi_u32_u24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
5710 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x38,0x01,0x00]
5711
5712 v_mul_hi_u32_u24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
5713 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x3c,0x01,0x00]
5714
5715 v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
5716 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0x00]
5717
5718 v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
5719 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0x00]
5720
5721 v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
5722 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0x00]
5723
5724 v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
5725 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0x00]
5726
5727 v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
5728 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0x00]
5729
5730 v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
5731 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0x00]
5732
5733 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
5734 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x10]
5735
5736 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
5737 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x30]
5738
5739 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
5740 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xf0]
5741
5742 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
5743 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xf0]
5744
5745 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
5746 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x01]
5747
5748 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
5749 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03]
5750
5751 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
5752 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
5753
5754 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
5755 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
5756
5757 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
5758 // CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
5759
5760 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5761 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
5762
5763 v_min_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5764 // CHECK: [0xf9,0x04,0xfe,0x15,0x01,0x06,0x06,0x06]
5765
5766 v_min_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5767 // CHECK: [0xf9,0x04,0x0a,0x14,0xff,0x06,0x06,0x06]
5768
5769 v_min_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5770 // CHECK: [0xf9,0xfe,0x0b,0x14,0x01,0x06,0x06,0x06]
5771
5772 v_min_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5773 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x26,0x06,0x06]
5774
5775 v_min_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5776 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
5777
5778 v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5779 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x00,0x06,0x06]
5780
5781 v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5782 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x01,0x06,0x06]
5783
5784 v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5785 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x02,0x06,0x06]
5786
5787 v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5788 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x03,0x06,0x06]
5789
5790 v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5791 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x04,0x06,0x06]
5792
5793 v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5794 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x05,0x06,0x06]
5795
5796 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
5797 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x0e,0x06,0x06]
5798
5799 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
5800 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
5801
5802 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
5803 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
5804
5805 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
5806 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
5807
5808 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
5809 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x00,0x06]
5810
5811 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
5812 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x01,0x06]
5813
5814 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
5815 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x02,0x06]
5816
5817 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
5818 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x03,0x06]
5819
5820 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
5821 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x04,0x06]
5822
5823 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
5824 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x05,0x06]
5825
5826 v_min_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5827 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x16,0x06]
5828
5829 v_min_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5830 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x26,0x06]
5831
5832 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
5833 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
5834
5835 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
5836 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x00]
5837
5838 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
5839 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x01]
5840
5841 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
5842 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x02]
5843
5844 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
5845 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x03]
5846
5847 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
5848 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x04]
5849
5850 v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
5851 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x05]
5852
5853 v_min_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5854 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x16]
5855
5856 v_min_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5857 // CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x26]
5858
5859 v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5860 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x00]
5861
5862 v_min_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5863 // CHECK: [0xfa,0x04,0xfe,0x15,0x01,0xe4,0x00,0x00]
5864
5865 v_min_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5866 // CHECK: [0xfa,0x04,0x0a,0x14,0xff,0xe4,0x00,0x00]
5867
5868 v_min_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5869 // CHECK: [0xfa,0xfe,0x0b,0x14,0x01,0xe4,0x00,0x00]
5870
5871 v_min_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
5872 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0x00]
5873
5874 v_min_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
5875 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0x00]
5876
5877 v_min_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
5878 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0x00]
5879
5880 v_min_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
5881 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x42,0x01,0x00]
5882
5883 v_min_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
5884 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x43,0x01,0x00]
5885
5886 v_min_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
5887 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x30,0x01,0x00]
5888
5889 v_min_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
5890 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x34,0x01,0x00]
5891
5892 v_min_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
5893 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x38,0x01,0x00]
5894
5895 v_min_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
5896 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x3c,0x01,0x00]
5897
5898 v_min_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
5899 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0x00]
5900
5901 v_min_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
5902 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0x00]
5903
5904 v_min_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
5905 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0x00]
5906
5907 v_min_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
5908 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0x00]
5909
5910 v_min_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
5911 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0x00]
5912
5913 v_min_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
5914 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0x00]
5915
5916 v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
5917 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x10]
5918
5919 v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
5920 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x30]
5921
5922 v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
5923 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xf0]
5924
5925 v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
5926 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xf0]
5927
5928 v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
5929 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x01]
5930
5931 v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
5932 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03]
5933
5934 v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
5935 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
5936
5937 v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
5938 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
5939
5940 v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
5941 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
5942
5943 v_min_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5944 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x10,0x00]
5945
5946 v_min_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5947 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x20,0x00]
5948
5949 v_min_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5950 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x40,0x00]
5951
5952 v_min_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
5953 // CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x80,0x00]
5954
5955 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5956 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
5957
5958 v_max_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5959 // CHECK: [0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06]
5960
5961 v_max_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5962 // CHECK: [0xf9,0x04,0x0a,0x16,0xff,0x06,0x06,0x06]
5963
5964 v_max_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5965 // CHECK: [0xf9,0xfe,0x0b,0x16,0x01,0x06,0x06,0x06]
5966
5967 v_max_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5968 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x26,0x06,0x06]
5969
5970 v_max_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5971 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
5972
5973 v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5974 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x00,0x06,0x06]
5975
5976 v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5977 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x01,0x06,0x06]
5978
5979 v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5980 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x02,0x06,0x06]
5981
5982 v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5983 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x03,0x06,0x06]
5984
5985 v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5986 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x04,0x06,0x06]
5987
5988 v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
5989 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x05,0x06,0x06]
5990
5991 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
5992 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x0e,0x06,0x06]
5993
5994 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
5995 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
5996
5997 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
5998 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
5999
6000 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
6001 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
6002
6003 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
6004 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x00,0x06]
6005
6006 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
6007 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x01,0x06]
6008
6009 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
6010 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x02,0x06]
6011
6012 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
6013 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x03,0x06]
6014
6015 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
6016 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x04,0x06]
6017
6018 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
6019 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x05,0x06]
6020
6021 v_max_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6022 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x16,0x06]
6023
6024 v_max_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6025 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x26,0x06]
6026
6027 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
6028 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
6029
6030 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
6031 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x00]
6032
6033 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
6034 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x01]
6035
6036 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
6037 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x02]
6038
6039 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
6040 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x03]
6041
6042 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
6043 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x04]
6044
6045 v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
6046 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x05]
6047
6048 v_max_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6049 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x16]
6050
6051 v_max_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6052 // CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x26]
6053
6054 v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6055 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x00]
6056
6057 v_max_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6058 // CHECK: [0xfa,0x04,0xfe,0x17,0x01,0xe4,0x00,0x00]
6059
6060 v_max_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6061 // CHECK: [0xfa,0x04,0x0a,0x16,0xff,0xe4,0x00,0x00]
6062
6063 v_max_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6064 // CHECK: [0xfa,0xfe,0x0b,0x16,0x01,0xe4,0x00,0x00]
6065
6066 v_max_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
6067 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0x00]
6068
6069 v_max_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
6070 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0x00]
6071
6072 v_max_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
6073 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0x00]
6074
6075 v_max_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
6076 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x42,0x01,0x00]
6077
6078 v_max_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
6079 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x43,0x01,0x00]
6080
6081 v_max_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
6082 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x30,0x01,0x00]
6083
6084 v_max_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
6085 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x34,0x01,0x00]
6086
6087 v_max_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
6088 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x38,0x01,0x00]
6089
6090 v_max_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
6091 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x3c,0x01,0x00]
6092
6093 v_max_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
6094 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0x00]
6095
6096 v_max_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
6097 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0x00]
6098
6099 v_max_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
6100 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0x00]
6101
6102 v_max_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
6103 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0x00]
6104
6105 v_max_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
6106 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0x00]
6107
6108 v_max_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
6109 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0x00]
6110
6111 v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
6112 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x10]
6113
6114 v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
6115 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x30]
6116
6117 v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
6118 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xf0]
6119
6120 v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
6121 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xf0]
6122
6123 v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
6124 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x01]
6125
6126 v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
6127 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03]
6128
6129 v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
6130 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
6131
6132 v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
6133 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
6134
6135 v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
6136 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
6137
6138 v_max_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6139 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x10,0x00]
6140
6141 v_max_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6142 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x20,0x00]
6143
6144 v_max_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6145 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x40,0x00]
6146
6147 v_max_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6148 // CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x80,0x00]
6149
6150 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6151 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
6152
6153 v_min_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6154 // CHECK: [0xf9,0x04,0xfe,0x19,0x01,0x06,0x06,0x06]
6155
6156 v_min_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6157 // CHECK: [0xf9,0x04,0x0a,0x18,0xff,0x06,0x06,0x06]
6158
6159 v_min_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6160 // CHECK: [0xf9,0xfe,0x0b,0x18,0x01,0x06,0x06,0x06]
6161
6162 v_min_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6163 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
6164
6165 v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6166 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x00,0x06,0x06]
6167
6168 v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6169 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x01,0x06,0x06]
6170
6171 v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6172 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x02,0x06,0x06]
6173
6174 v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6175 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x03,0x06,0x06]
6176
6177 v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6178 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x04,0x06,0x06]
6179
6180 v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6181 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x05,0x06,0x06]
6182
6183 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
6184 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x0e,0x06,0x06]
6185
6186 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
6187 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
6188
6189 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
6190 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
6191
6192 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
6193 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
6194
6195 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
6196 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x00,0x06]
6197
6198 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
6199 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x01,0x06]
6200
6201 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
6202 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x02,0x06]
6203
6204 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
6205 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x03,0x06]
6206
6207 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
6208 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x04,0x06]
6209
6210 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
6211 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x05,0x06]
6212
6213 v_min_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6214 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x0e,0x06]
6215
6216 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
6217 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
6218
6219 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
6220 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x00]
6221
6222 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
6223 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x01]
6224
6225 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
6226 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x02]
6227
6228 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
6229 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x03]
6230
6231 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
6232 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x04]
6233
6234 v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
6235 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x05]
6236
6237 v_min_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6238 // CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x0e]
6239
6240 v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6241 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x00]
6242
6243 v_min_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6244 // CHECK: [0xfa,0x04,0xfe,0x19,0x01,0xe4,0x00,0x00]
6245
6246 v_min_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6247 // CHECK: [0xfa,0x04,0x0a,0x18,0xff,0xe4,0x00,0x00]
6248
6249 v_min_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6250 // CHECK: [0xfa,0xfe,0x0b,0x18,0x01,0xe4,0x00,0x00]
6251
6252 v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
6253 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0x00]
6254
6255 v_min_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
6256 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0x00]
6257
6258 v_min_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
6259 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0x00]
6260
6261 v_min_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
6262 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x42,0x01,0x00]
6263
6264 v_min_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
6265 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x43,0x01,0x00]
6266
6267 v_min_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
6268 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x30,0x01,0x00]
6269
6270 v_min_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
6271 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x34,0x01,0x00]
6272
6273 v_min_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
6274 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x38,0x01,0x00]
6275
6276 v_min_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
6277 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x3c,0x01,0x00]
6278
6279 v_min_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
6280 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0x00]
6281
6282 v_min_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
6283 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0x00]
6284
6285 v_min_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
6286 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0x00]
6287
6288 v_min_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
6289 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0x00]
6290
6291 v_min_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
6292 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0x00]
6293
6294 v_min_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
6295 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0x00]
6296
6297 v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
6298 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x10]
6299
6300 v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
6301 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x30]
6302
6303 v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
6304 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xf0]
6305
6306 v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
6307 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xf0]
6308
6309 v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
6310 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x01]
6311
6312 v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
6313 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03]
6314
6315 v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
6316 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
6317
6318 v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
6319 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
6320
6321 v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
6322 // CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
6323
6324 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6325 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
6326
6327 v_max_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6328 // CHECK: [0xf9,0x04,0xfe,0x1b,0x01,0x06,0x06,0x06]
6329
6330 v_max_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6331 // CHECK: [0xf9,0x04,0x0a,0x1a,0xff,0x06,0x06,0x06]
6332
6333 v_max_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6334 // CHECK: [0xf9,0xfe,0x0b,0x1a,0x01,0x06,0x06,0x06]
6335
6336 v_max_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6337 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
6338
6339 v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6340 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x00,0x06,0x06]
6341
6342 v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6343 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x01,0x06,0x06]
6344
6345 v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6346 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x02,0x06,0x06]
6347
6348 v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6349 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x03,0x06,0x06]
6350
6351 v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6352 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x04,0x06,0x06]
6353
6354 v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6355 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x05,0x06,0x06]
6356
6357 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
6358 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x0e,0x06,0x06]
6359
6360 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
6361 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x16,0x06,0x06]
6362
6363 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
6364 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x16,0x06,0x06]
6365
6366 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
6367 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
6368
6369 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
6370 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x00,0x06]
6371
6372 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
6373 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x01,0x06]
6374
6375 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
6376 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x02,0x06]
6377
6378 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
6379 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x03,0x06]
6380
6381 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
6382 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x04,0x06]
6383
6384 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
6385 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x05,0x06]
6386
6387 v_max_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6388 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x0e,0x06]
6389
6390 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
6391 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
6392
6393 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
6394 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x00]
6395
6396 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
6397 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x01]
6398
6399 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
6400 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x02]
6401
6402 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
6403 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x03]
6404
6405 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
6406 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x04]
6407
6408 v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
6409 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x05]
6410
6411 v_max_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6412 // CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x0e]
6413
6414 v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6415 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x00]
6416
6417 v_max_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6418 // CHECK: [0xfa,0x04,0xfe,0x1b,0x01,0xe4,0x00,0x00]
6419
6420 v_max_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6421 // CHECK: [0xfa,0x04,0x0a,0x1a,0xff,0xe4,0x00,0x00]
6422
6423 v_max_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6424 // CHECK: [0xfa,0xfe,0x0b,0x1a,0x01,0xe4,0x00,0x00]
6425
6426 v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
6427 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x1b,0x00,0x00]
6428
6429 v_max_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
6430 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x40,0x01,0x00]
6431
6432 v_max_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
6433 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x41,0x01,0x00]
6434
6435 v_max_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
6436 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x42,0x01,0x00]
6437
6438 v_max_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
6439 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x43,0x01,0x00]
6440
6441 v_max_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
6442 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x30,0x01,0x00]
6443
6444 v_max_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
6445 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x34,0x01,0x00]
6446
6447 v_max_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
6448 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x38,0x01,0x00]
6449
6450 v_max_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
6451 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x3c,0x01,0x00]
6452
6453 v_max_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
6454 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x01,0x01,0x00]
6455
6456 v_max_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
6457 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x0f,0x01,0x00]
6458
6459 v_max_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
6460 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x11,0x01,0x00]
6461
6462 v_max_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
6463 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x1f,0x01,0x00]
6464
6465 v_max_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
6466 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x21,0x01,0x00]
6467
6468 v_max_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
6469 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x2f,0x01,0x00]
6470
6471 v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
6472 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x10]
6473
6474 v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
6475 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x30]
6476
6477 v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
6478 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
6479
6480 v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
6481 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
6482
6483 v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
6484 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x01]
6485
6486 v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
6487 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03]
6488
6489 v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
6490 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
6491
6492 v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
6493 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
6494
6495 v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
6496 // CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]
6497
6498 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6499 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
6500
6501 v_min_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6502 // CHECK: [0xf9,0x04,0xfe,0x1d,0x01,0x06,0x06,0x06]
6503
6504 v_min_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6505 // CHECK: [0xf9,0x04,0x0a,0x1c,0xff,0x06,0x06,0x06]
6506
6507 v_min_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6508 // CHECK: [0xf9,0xfe,0x0b,0x1c,0x01,0x06,0x06,0x06]
6509
6510 v_min_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6511 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
6512
6513 v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6514 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x00,0x06,0x06]
6515
6516 v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6517 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x01,0x06,0x06]
6518
6519 v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6520 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x02,0x06,0x06]
6521
6522 v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6523 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x03,0x06,0x06]
6524
6525 v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6526 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x04,0x06,0x06]
6527
6528 v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6529 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x05,0x06,0x06]
6530
6531 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
6532 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x0e,0x06,0x06]
6533
6534 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
6535 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x16,0x06,0x06]
6536
6537 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
6538 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x16,0x06,0x06]
6539
6540 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
6541 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
6542
6543 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
6544 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x00,0x06]
6545
6546 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
6547 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x01,0x06]
6548
6549 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
6550 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x02,0x06]
6551
6552 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
6553 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x03,0x06]
6554
6555 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
6556 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x04,0x06]
6557
6558 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
6559 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x05,0x06]
6560
6561 v_min_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6562 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x0e,0x06]
6563
6564 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
6565 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
6566
6567 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
6568 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x00]
6569
6570 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
6571 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x01]
6572
6573 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
6574 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x02]
6575
6576 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
6577 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x03]
6578
6579 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
6580 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x04]
6581
6582 v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
6583 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x05]
6584
6585 v_min_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6586 // CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x0e]
6587
6588 v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6589 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x00]
6590
6591 v_min_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6592 // CHECK: [0xfa,0x04,0xfe,0x1d,0x01,0xe4,0x00,0x00]
6593
6594 v_min_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6595 // CHECK: [0xfa,0x04,0x0a,0x1c,0xff,0xe4,0x00,0x00]
6596
6597 v_min_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6598 // CHECK: [0xfa,0xfe,0x0b,0x1c,0x01,0xe4,0x00,0x00]
6599
6600 v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
6601 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x1b,0x00,0x00]
6602
6603 v_min_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
6604 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x40,0x01,0x00]
6605
6606 v_min_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
6607 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x41,0x01,0x00]
6608
6609 v_min_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
6610 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x42,0x01,0x00]
6611
6612 v_min_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
6613 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x43,0x01,0x00]
6614
6615 v_min_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
6616 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x30,0x01,0x00]
6617
6618 v_min_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
6619 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x34,0x01,0x00]
6620
6621 v_min_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
6622 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x38,0x01,0x00]
6623
6624 v_min_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
6625 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x3c,0x01,0x00]
6626
6627 v_min_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
6628 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x01,0x01,0x00]
6629
6630 v_min_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
6631 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x0f,0x01,0x00]
6632
6633 v_min_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
6634 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x11,0x01,0x00]
6635
6636 v_min_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
6637 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x1f,0x01,0x00]
6638
6639 v_min_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
6640 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x21,0x01,0x00]
6641
6642 v_min_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
6643 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x2f,0x01,0x00]
6644
6645 v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
6646 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x10]
6647
6648 v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
6649 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x30]
6650
6651 v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
6652 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0xf0]
6653
6654 v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
6655 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0xf0]
6656
6657 v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
6658 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x01]
6659
6660 v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
6661 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x03]
6662
6663 v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
6664 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f]
6665
6666 v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
6667 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f]
6668
6669 v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
6670 // CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x08,0x00]
6671
6672 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6673 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
6674
6675 v_max_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6676 // CHECK: [0xf9,0x04,0xfe,0x1f,0x01,0x06,0x06,0x06]
6677
6678 v_max_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6679 // CHECK: [0xf9,0x04,0x0a,0x1e,0xff,0x06,0x06,0x06]
6680
6681 v_max_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6682 // CHECK: [0xf9,0xfe,0x0b,0x1e,0x01,0x06,0x06,0x06]
6683
6684 v_max_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6685 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
6686
6687 v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6688 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x00,0x06,0x06]
6689
6690 v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6691 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x01,0x06,0x06]
6692
6693 v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6694 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x02,0x06,0x06]
6695
6696 v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6697 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x03,0x06,0x06]
6698
6699 v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6700 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x04,0x06,0x06]
6701
6702 v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6703 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x05,0x06,0x06]
6704
6705 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
6706 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x0e,0x06,0x06]
6707
6708 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
6709 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
6710
6711 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
6712 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
6713
6714 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
6715 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
6716
6717 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
6718 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x00,0x06]
6719
6720 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
6721 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x01,0x06]
6722
6723 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
6724 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x02,0x06]
6725
6726 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
6727 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x03,0x06]
6728
6729 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
6730 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x04,0x06]
6731
6732 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
6733 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x05,0x06]
6734
6735 v_max_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6736 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x0e,0x06]
6737
6738 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
6739 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
6740
6741 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
6742 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x00]
6743
6744 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
6745 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x01]
6746
6747 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
6748 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x02]
6749
6750 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
6751 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x03]
6752
6753 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
6754 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x04]
6755
6756 v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
6757 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x05]
6758
6759 v_max_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6760 // CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x0e]
6761
6762 v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6763 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x00]
6764
6765 v_max_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6766 // CHECK: [0xfa,0x04,0xfe,0x1f,0x01,0xe4,0x00,0x00]
6767
6768 v_max_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6769 // CHECK: [0xfa,0x04,0x0a,0x1e,0xff,0xe4,0x00,0x00]
6770
6771 v_max_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6772 // CHECK: [0xfa,0xfe,0x0b,0x1e,0x01,0xe4,0x00,0x00]
6773
6774 v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
6775 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0x00]
6776
6777 v_max_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
6778 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x40,0x01,0x00]
6779
6780 v_max_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
6781 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x41,0x01,0x00]
6782
6783 v_max_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
6784 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x42,0x01,0x00]
6785
6786 v_max_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
6787 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x43,0x01,0x00]
6788
6789 v_max_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
6790 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x30,0x01,0x00]
6791
6792 v_max_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
6793 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x34,0x01,0x00]
6794
6795 v_max_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
6796 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x38,0x01,0x00]
6797
6798 v_max_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
6799 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x3c,0x01,0x00]
6800
6801 v_max_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
6802 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x01,0x01,0x00]
6803
6804 v_max_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
6805 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x0f,0x01,0x00]
6806
6807 v_max_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
6808 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x11,0x01,0x00]
6809
6810 v_max_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
6811 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x1f,0x01,0x00]
6812
6813 v_max_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
6814 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x21,0x01,0x00]
6815
6816 v_max_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
6817 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x2f,0x01,0x00]
6818
6819 v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
6820 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x10]
6821
6822 v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
6823 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x30]
6824
6825 v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
6826 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xf0]
6827
6828 v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
6829 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xf0]
6830
6831 v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
6832 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x01]
6833
6834 v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
6835 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03]
6836
6837 v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
6838 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
6839
6840 v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
6841 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
6842
6843 v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
6844 // CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
6845
6846 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6847 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
6848
6849 v_lshrrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6850 // CHECK: [0xf9,0x04,0xfe,0x21,0x01,0x06,0x06,0x06]
6851
6852 v_lshrrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6853 // CHECK: [0xf9,0x04,0x0a,0x20,0xff,0x06,0x06,0x06]
6854
6855 v_lshrrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6856 // CHECK: [0xf9,0xfe,0x0b,0x20,0x01,0x06,0x06,0x06]
6857
6858 v_lshrrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6859 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
6860
6861 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6862 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x00,0x06,0x06]
6863
6864 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6865 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x01,0x06,0x06]
6866
6867 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6868 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x02,0x06,0x06]
6869
6870 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6871 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x03,0x06,0x06]
6872
6873 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6874 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x04,0x06,0x06]
6875
6876 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6877 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x05,0x06,0x06]
6878
6879 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
6880 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x0e,0x06,0x06]
6881
6882 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
6883 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
6884
6885 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
6886 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
6887
6888 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
6889 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
6890
6891 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
6892 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x00,0x06]
6893
6894 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
6895 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x01,0x06]
6896
6897 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
6898 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x02,0x06]
6899
6900 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
6901 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x03,0x06]
6902
6903 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
6904 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x04,0x06]
6905
6906 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
6907 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x05,0x06]
6908
6909 v_lshrrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6910 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x0e,0x06]
6911
6912 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
6913 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
6914
6915 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
6916 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x00]
6917
6918 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
6919 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x01]
6920
6921 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
6922 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x02]
6923
6924 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
6925 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x03]
6926
6927 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
6928 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x04]
6929
6930 v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
6931 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x05]
6932
6933 v_lshrrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
6934 // CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x0e]
6935
6936 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6937 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x00]
6938
6939 v_lshrrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6940 // CHECK: [0xfa,0x04,0xfe,0x21,0x01,0xe4,0x00,0x00]
6941
6942 v_lshrrev_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6943 // CHECK: [0xfa,0x04,0x0a,0x20,0xff,0xe4,0x00,0x00]
6944
6945 v_lshrrev_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
6946 // CHECK: [0xfa,0xfe,0x0b,0x20,0x01,0xe4,0x00,0x00]
6947
6948 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
6949 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0x00]
6950
6951 v_lshrrev_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
6952 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x40,0x01,0x00]
6953
6954 v_lshrrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
6955 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x41,0x01,0x00]
6956
6957 v_lshrrev_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
6958 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x42,0x01,0x00]
6959
6960 v_lshrrev_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
6961 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x43,0x01,0x00]
6962
6963 v_lshrrev_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
6964 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x30,0x01,0x00]
6965
6966 v_lshrrev_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
6967 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x34,0x01,0x00]
6968
6969 v_lshrrev_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
6970 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x38,0x01,0x00]
6971
6972 v_lshrrev_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
6973 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x3c,0x01,0x00]
6974
6975 v_lshrrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
6976 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x01,0x01,0x00]
6977
6978 v_lshrrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
6979 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x0f,0x01,0x00]
6980
6981 v_lshrrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
6982 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x11,0x01,0x00]
6983
6984 v_lshrrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
6985 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x1f,0x01,0x00]
6986
6987 v_lshrrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
6988 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x21,0x01,0x00]
6989
6990 v_lshrrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
6991 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x2f,0x01,0x00]
6992
6993 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
6994 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x10]
6995
6996 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
6997 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x30]
6998
6999 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
7000 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xf0]
7001
7002 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
7003 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xf0]
7004
7005 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
7006 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x01]
7007
7008 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
7009 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03]
7010
7011 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
7012 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
7013
7014 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
7015 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
7016
7017 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
7018 // CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
7019
7020 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7021 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
7022
7023 v_ashrrev_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7024 // CHECK: [0xf9,0x04,0xfe,0x23,0x01,0x06,0x06,0x06]
7025
7026 v_ashrrev_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7027 // CHECK: [0xf9,0x04,0x0a,0x22,0xff,0x06,0x06,0x06]
7028
7029 v_ashrrev_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7030 // CHECK: [0xf9,0xfe,0x0b,0x22,0x01,0x06,0x06,0x06]
7031
7032 v_ashrrev_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7033 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
7034
7035 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7036 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x00,0x06,0x06]
7037
7038 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7039 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x01,0x06,0x06]
7040
7041 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7042 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x02,0x06,0x06]
7043
7044 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7045 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x03,0x06,0x06]
7046
7047 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7048 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x04,0x06,0x06]
7049
7050 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7051 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x05,0x06,0x06]
7052
7053 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
7054 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x0e,0x06,0x06]
7055
7056 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
7057 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
7058
7059 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
7060 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
7061
7062 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
7063 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
7064
7065 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
7066 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x00,0x06]
7067
7068 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
7069 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x01,0x06]
7070
7071 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
7072 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x02,0x06]
7073
7074 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
7075 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x03,0x06]
7076
7077 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
7078 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x04,0x06]
7079
7080 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
7081 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x05,0x06]
7082
7083 v_ashrrev_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7084 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x0e,0x06]
7085
7086 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
7087 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
7088
7089 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
7090 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x00]
7091
7092 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
7093 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x01]
7094
7095 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
7096 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x02]
7097
7098 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
7099 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x03]
7100
7101 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
7102 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x04]
7103
7104 v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
7105 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x05]
7106
7107 v_ashrrev_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7108 // CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x0e]
7109
7110 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7111 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x00]
7112
7113 v_ashrrev_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7114 // CHECK: [0xfa,0x04,0xfe,0x23,0x01,0xe4,0x00,0x00]
7115
7116 v_ashrrev_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7117 // CHECK: [0xfa,0x04,0x0a,0x22,0xff,0xe4,0x00,0x00]
7118
7119 v_ashrrev_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7120 // CHECK: [0xfa,0xfe,0x0b,0x22,0x01,0xe4,0x00,0x00]
7121
7122 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
7123 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0x00]
7124
7125 v_ashrrev_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
7126 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0x00]
7127
7128 v_ashrrev_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
7129 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0x00]
7130
7131 v_ashrrev_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
7132 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x42,0x01,0x00]
7133
7134 v_ashrrev_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
7135 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x43,0x01,0x00]
7136
7137 v_ashrrev_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
7138 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x30,0x01,0x00]
7139
7140 v_ashrrev_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
7141 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x34,0x01,0x00]
7142
7143 v_ashrrev_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
7144 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x38,0x01,0x00]
7145
7146 v_ashrrev_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
7147 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x3c,0x01,0x00]
7148
7149 v_ashrrev_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
7150 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0x00]
7151
7152 v_ashrrev_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
7153 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0x00]
7154
7155 v_ashrrev_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
7156 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0x00]
7157
7158 v_ashrrev_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
7159 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0x00]
7160
7161 v_ashrrev_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
7162 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0x00]
7163
7164 v_ashrrev_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
7165 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0x00]
7166
7167 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
7168 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x10]
7169
7170 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
7171 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x30]
7172
7173 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
7174 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xf0]
7175
7176 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
7177 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xf0]
7178
7179 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
7180 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x01]
7181
7182 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
7183 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03]
7184
7185 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
7186 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
7187
7188 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
7189 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
7190
7191 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
7192 // CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
7193
7194 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7195 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
7196
7197 v_lshlrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7198 // CHECK: [0xf9,0x04,0xfe,0x25,0x01,0x06,0x06,0x06]
7199
7200 v_lshlrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7201 // CHECK: [0xf9,0x04,0x0a,0x24,0xff,0x06,0x06,0x06]
7202
7203 v_lshlrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7204 // CHECK: [0xf9,0xfe,0x0b,0x24,0x01,0x06,0x06,0x06]
7205
7206 v_lshlrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7207 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
7208
7209 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7210 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x00,0x06,0x06]
7211
7212 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7213 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x01,0x06,0x06]
7214
7215 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7216 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x02,0x06,0x06]
7217
7218 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7219 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x03,0x06,0x06]
7220
7221 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7222 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x04,0x06,0x06]
7223
7224 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7225 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x05,0x06,0x06]
7226
7227 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
7228 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x0e,0x06,0x06]
7229
7230 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
7231 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
7232
7233 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
7234 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
7235
7236 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
7237 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
7238
7239 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
7240 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x00,0x06]
7241
7242 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
7243 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x01,0x06]
7244
7245 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
7246 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x02,0x06]
7247
7248 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
7249 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x03,0x06]
7250
7251 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
7252 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x04,0x06]
7253
7254 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
7255 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x05,0x06]
7256
7257 v_lshlrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7258 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x0e,0x06]
7259
7260 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
7261 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
7262
7263 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
7264 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x00]
7265
7266 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
7267 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x01]
7268
7269 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
7270 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x02]
7271
7272 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
7273 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x03]
7274
7275 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
7276 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x04]
7277
7278 v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
7279 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x05]
7280
7281 v_lshlrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7282 // CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x0e]
7283
7284 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7285 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x00]
7286
7287 v_lshlrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7288 // CHECK: [0xfa,0x04,0xfe,0x25,0x01,0xe4,0x00,0x00]
7289
7290 v_lshlrev_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7291 // CHECK: [0xfa,0x04,0x0a,0x24,0xff,0xe4,0x00,0x00]
7292
7293 v_lshlrev_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7294 // CHECK: [0xfa,0xfe,0x0b,0x24,0x01,0xe4,0x00,0x00]
7295
7296 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
7297 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0x00]
7298
7299 v_lshlrev_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
7300 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0x00]
7301
7302 v_lshlrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
7303 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0x00]
7304
7305 v_lshlrev_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
7306 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x42,0x01,0x00]
7307
7308 v_lshlrev_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
7309 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x43,0x01,0x00]
7310
7311 v_lshlrev_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
7312 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x30,0x01,0x00]
7313
7314 v_lshlrev_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
7315 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x34,0x01,0x00]
7316
7317 v_lshlrev_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
7318 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x38,0x01,0x00]
7319
7320 v_lshlrev_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
7321 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x3c,0x01,0x00]
7322
7323 v_lshlrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
7324 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0x00]
7325
7326 v_lshlrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
7327 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0x00]
7328
7329 v_lshlrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
7330 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0x00]
7331
7332 v_lshlrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
7333 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0x00]
7334
7335 v_lshlrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
7336 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0x00]
7337
7338 v_lshlrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
7339 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0x00]
7340
7341 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
7342 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x10]
7343
7344 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
7345 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x30]
7346
7347 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
7348 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xf0]
7349
7350 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
7351 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xf0]
7352
7353 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
7354 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x01]
7355
7356 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
7357 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03]
7358
7359 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
7360 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
7361
7362 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
7363 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
7364
7365 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
7366 // CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
7367
7368 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7369 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
7370
7371 v_and_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7372 // CHECK: [0xf9,0x04,0xfe,0x27,0x01,0x06,0x06,0x06]
7373
7374 v_and_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7375 // CHECK: [0xf9,0x04,0x0a,0x26,0xff,0x06,0x06,0x06]
7376
7377 v_and_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7378 // CHECK: [0xf9,0xfe,0x0b,0x26,0x01,0x06,0x06,0x06]
7379
7380 v_and_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7381 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
7382
7383 v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7384 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x00,0x06,0x06]
7385
7386 v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7387 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x01,0x06,0x06]
7388
7389 v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7390 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x02,0x06,0x06]
7391
7392 v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7393 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x03,0x06,0x06]
7394
7395 v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7396 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x04,0x06,0x06]
7397
7398 v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7399 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x05,0x06,0x06]
7400
7401 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
7402 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x0e,0x06,0x06]
7403
7404 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
7405 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
7406
7407 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
7408 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
7409
7410 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
7411 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
7412
7413 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
7414 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x00,0x06]
7415
7416 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
7417 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x01,0x06]
7418
7419 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
7420 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x02,0x06]
7421
7422 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
7423 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x03,0x06]
7424
7425 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
7426 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x04,0x06]
7427
7428 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
7429 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x05,0x06]
7430
7431 v_and_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7432 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x0e,0x06]
7433
7434 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
7435 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
7436
7437 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
7438 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x00]
7439
7440 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
7441 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x01]
7442
7443 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
7444 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x02]
7445
7446 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
7447 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x03]
7448
7449 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
7450 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x04]
7451
7452 v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
7453 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x05]
7454
7455 v_and_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7456 // CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x0e]
7457
7458 v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7459 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x00]
7460
7461 v_and_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7462 // CHECK: [0xfa,0x04,0xfe,0x27,0x01,0xe4,0x00,0x00]
7463
7464 v_and_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7465 // CHECK: [0xfa,0x04,0x0a,0x26,0xff,0xe4,0x00,0x00]
7466
7467 v_and_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7468 // CHECK: [0xfa,0xfe,0x0b,0x26,0x01,0xe4,0x00,0x00]
7469
7470 v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
7471 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0x00]
7472
7473 v_and_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
7474 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0x00]
7475
7476 v_and_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
7477 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0x00]
7478
7479 v_and_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
7480 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x42,0x01,0x00]
7481
7482 v_and_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
7483 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x43,0x01,0x00]
7484
7485 v_and_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
7486 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x30,0x01,0x00]
7487
7488 v_and_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
7489 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x34,0x01,0x00]
7490
7491 v_and_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
7492 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x38,0x01,0x00]
7493
7494 v_and_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
7495 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x3c,0x01,0x00]
7496
7497 v_and_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
7498 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0x00]
7499
7500 v_and_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
7501 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0x00]
7502
7503 v_and_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
7504 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0x00]
7505
7506 v_and_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
7507 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0x00]
7508
7509 v_and_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
7510 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0x00]
7511
7512 v_and_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
7513 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0x00]
7514
7515 v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
7516 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x10]
7517
7518 v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
7519 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x30]
7520
7521 v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
7522 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xf0]
7523
7524 v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
7525 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xf0]
7526
7527 v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
7528 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x01]
7529
7530 v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
7531 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03]
7532
7533 v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
7534 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
7535
7536 v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
7537 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
7538
7539 v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
7540 // CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
7541
7542 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7543 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
7544
7545 v_or_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7546 // CHECK: [0xf9,0x04,0xfe,0x29,0x01,0x06,0x06,0x06]
7547
7548 v_or_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7549 // CHECK: [0xf9,0x04,0x0a,0x28,0xff,0x06,0x06,0x06]
7550
7551 v_or_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7552 // CHECK: [0xf9,0xfe,0x0b,0x28,0x01,0x06,0x06,0x06]
7553
7554 v_or_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7555 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
7556
7557 v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7558 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x00,0x06,0x06]
7559
7560 v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7561 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x01,0x06,0x06]
7562
7563 v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7564 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x02,0x06,0x06]
7565
7566 v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7567 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x03,0x06,0x06]
7568
7569 v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7570 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x04,0x06,0x06]
7571
7572 v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7573 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x05,0x06,0x06]
7574
7575 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
7576 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x0e,0x06,0x06]
7577
7578 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
7579 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
7580
7581 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
7582 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
7583
7584 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
7585 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
7586
7587 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
7588 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x00,0x06]
7589
7590 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
7591 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x01,0x06]
7592
7593 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
7594 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x02,0x06]
7595
7596 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
7597 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x03,0x06]
7598
7599 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
7600 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x04,0x06]
7601
7602 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
7603 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x05,0x06]
7604
7605 v_or_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7606 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x0e,0x06]
7607
7608 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
7609 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
7610
7611 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
7612 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x00]
7613
7614 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
7615 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x01]
7616
7617 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
7618 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x02]
7619
7620 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
7621 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x03]
7622
7623 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
7624 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x04]
7625
7626 v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
7627 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x05]
7628
7629 v_or_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7630 // CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x0e]
7631
7632 v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7633 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x00]
7634
7635 v_or_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7636 // CHECK: [0xfa,0x04,0xfe,0x29,0x01,0xe4,0x00,0x00]
7637
7638 v_or_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7639 // CHECK: [0xfa,0x04,0x0a,0x28,0xff,0xe4,0x00,0x00]
7640
7641 v_or_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7642 // CHECK: [0xfa,0xfe,0x0b,0x28,0x01,0xe4,0x00,0x00]
7643
7644 v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
7645 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0x00]
7646
7647 v_or_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
7648 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0x00]
7649
7650 v_or_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
7651 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0x00]
7652
7653 v_or_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
7654 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x42,0x01,0x00]
7655
7656 v_or_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
7657 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x43,0x01,0x00]
7658
7659 v_or_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
7660 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x30,0x01,0x00]
7661
7662 v_or_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
7663 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x34,0x01,0x00]
7664
7665 v_or_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
7666 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x38,0x01,0x00]
7667
7668 v_or_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
7669 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x3c,0x01,0x00]
7670
7671 v_or_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
7672 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0x00]
7673
7674 v_or_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
7675 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0x00]
7676
7677 v_or_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
7678 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0x00]
7679
7680 v_or_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
7681 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0x00]
7682
7683 v_or_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
7684 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0x00]
7685
7686 v_or_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
7687 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0x00]
7688
7689 v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
7690 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x10]
7691
7692 v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
7693 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x30]
7694
7695 v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
7696 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xf0]
7697
7698 v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
7699 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xf0]
7700
7701 v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
7702 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x01]
7703
7704 v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
7705 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03]
7706
7707 v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
7708 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
7709
7710 v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
7711 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
7712
7713 v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
7714 // CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
7715
7716 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7717 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
7718
7719 v_xor_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7720 // CHECK: [0xf9,0x04,0xfe,0x2b,0x01,0x06,0x06,0x06]
7721
7722 v_xor_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7723 // CHECK: [0xf9,0x04,0x0a,0x2a,0xff,0x06,0x06,0x06]
7724
7725 v_xor_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7726 // CHECK: [0xf9,0xfe,0x0b,0x2a,0x01,0x06,0x06,0x06]
7727
7728 v_xor_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7729 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
7730
7731 v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7732 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x00,0x06,0x06]
7733
7734 v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7735 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x01,0x06,0x06]
7736
7737 v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7738 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x02,0x06,0x06]
7739
7740 v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7741 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x03,0x06,0x06]
7742
7743 v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7744 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x04,0x06,0x06]
7745
7746 v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7747 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x05,0x06,0x06]
7748
7749 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
7750 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x0e,0x06,0x06]
7751
7752 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
7753 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x16,0x06,0x06]
7754
7755 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
7756 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x16,0x06,0x06]
7757
7758 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
7759 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
7760
7761 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
7762 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x00,0x06]
7763
7764 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
7765 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x01,0x06]
7766
7767 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
7768 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x02,0x06]
7769
7770 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
7771 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x03,0x06]
7772
7773 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
7774 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x04,0x06]
7775
7776 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
7777 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x05,0x06]
7778
7779 v_xor_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7780 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x0e,0x06]
7781
7782 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
7783 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
7784
7785 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
7786 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x00]
7787
7788 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
7789 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x01]
7790
7791 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
7792 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x02]
7793
7794 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
7795 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x03]
7796
7797 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
7798 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x04]
7799
7800 v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
7801 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x05]
7802
7803 v_xor_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7804 // CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x0e]
7805
7806 v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7807 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x00]
7808
7809 v_xor_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7810 // CHECK: [0xfa,0x04,0xfe,0x2b,0x01,0xe4,0x00,0x00]
7811
7812 v_xor_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7813 // CHECK: [0xfa,0x04,0x0a,0x2a,0xff,0xe4,0x00,0x00]
7814
7815 v_xor_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7816 // CHECK: [0xfa,0xfe,0x0b,0x2a,0x01,0xe4,0x00,0x00]
7817
7818 v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
7819 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x1b,0x00,0x00]
7820
7821 v_xor_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
7822 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x40,0x01,0x00]
7823
7824 v_xor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
7825 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x41,0x01,0x00]
7826
7827 v_xor_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
7828 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x42,0x01,0x00]
7829
7830 v_xor_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
7831 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x43,0x01,0x00]
7832
7833 v_xor_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
7834 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x30,0x01,0x00]
7835
7836 v_xor_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
7837 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x34,0x01,0x00]
7838
7839 v_xor_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
7840 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x38,0x01,0x00]
7841
7842 v_xor_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
7843 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x3c,0x01,0x00]
7844
7845 v_xor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
7846 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x01,0x01,0x00]
7847
7848 v_xor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
7849 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x0f,0x01,0x00]
7850
7851 v_xor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
7852 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x11,0x01,0x00]
7853
7854 v_xor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
7855 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x1f,0x01,0x00]
7856
7857 v_xor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
7858 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x21,0x01,0x00]
7859
7860 v_xor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
7861 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x2f,0x01,0x00]
7862
7863 v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
7864 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x10]
7865
7866 v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
7867 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x30]
7868
7869 v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
7870 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xf0]
7871
7872 v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
7873 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xf0]
7874
7875 v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
7876 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x01]
7877
7878 v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
7879 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x03]
7880
7881 v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
7882 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f]
7883
7884 v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
7885 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f]
7886
7887 v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
7888 // CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x08,0x00]
7889
7890 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7891 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
7892
7893 v_mac_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7894 // CHECK: [0xf9,0x04,0xfe,0x2d,0x01,0x06,0x06,0x06]
7895
7896 v_mac_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7897 // CHECK: [0xf9,0x04,0x0a,0x2c,0xff,0x06,0x06,0x06]
7898
7899 v_mac_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7900 // CHECK: [0xf9,0xfe,0x0b,0x2c,0x01,0x06,0x06,0x06]
7901
7902 v_mac_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7903 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x26,0x06,0x06]
7904
7905 v_mac_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7906 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
7907
7908 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
7909 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x0e,0x06,0x06]
7910
7911 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
7912 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x16,0x06,0x06]
7913
7914 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
7915 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x16,0x06,0x06]
7916
7917 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
7918 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
7919
7920 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
7921 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x00,0x06]
7922
7923 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
7924 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x01,0x06]
7925
7926 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
7927 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x02,0x06]
7928
7929 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
7930 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x03,0x06]
7931
7932 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
7933 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x04,0x06]
7934
7935 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
7936 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x05,0x06]
7937
7938 v_mac_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7939 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x16,0x06]
7940
7941 v_mac_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7942 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x26,0x06]
7943
7944 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
7945 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
7946
7947 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
7948 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x00]
7949
7950 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
7951 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x01]
7952
7953 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
7954 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x02]
7955
7956 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
7957 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x03]
7958
7959 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
7960 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x04]
7961
7962 v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
7963 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x05]
7964
7965 v_mac_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7966 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x16]
7967
7968 v_mac_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
7969 // CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x26]
7970
7971 v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7972 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00]
7973
7974 v_mac_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7975 // CHECK: [0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00]
7976
7977 v_mac_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7978 // CHECK: [0xfa,0x04,0x0a,0x2c,0xff,0xe4,0x00,0x00]
7979
7980 v_mac_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
7981 // CHECK: [0xfa,0xfe,0x0b,0x2c,0x01,0xe4,0x00,0x00]
7982
7983 v_mac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
7984 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0x00]
7985
7986 v_mac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
7987 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0x00]
7988
7989 v_mac_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
7990 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0x00]
7991
7992 v_mac_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
7993 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x42,0x01,0x00]
7994
7995 v_mac_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
7996 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x43,0x01,0x00]
7997
7998 v_mac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
7999 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x30,0x01,0x00]
8000
8001 v_mac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
8002 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x34,0x01,0x00]
8003
8004 v_mac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
8005 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x38,0x01,0x00]
8006
8007 v_mac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
8008 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x3c,0x01,0x00]
8009
8010 v_mac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
8011 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0x00]
8012
8013 v_mac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
8014 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0x00]
8015
8016 v_mac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
8017 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0x00]
8018
8019 v_mac_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
8020 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0x00]
8021
8022 v_mac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
8023 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0x00]
8024
8025 v_mac_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
8026 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0x00]
8027
8028 v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
8029 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x10]
8030
8031 v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
8032 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x30]
8033
8034 v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
8035 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xf0]
8036
8037 v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
8038 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xf0]
8039
8040 v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
8041 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x01]
8042
8043 v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
8044 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03]
8045
8046 v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
8047 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
8048
8049 v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
8050 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
8051
8052 v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
8053 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
8054
8055 v_mac_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8056 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x10,0x00]
8057
8058 v_mac_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8059 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x20,0x00]
8060
8061 v_mac_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8062 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x40,0x00]
8063
8064 v_mac_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8065 // CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x80,0x00]
8066
8067 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8068 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
8069
8070 v_add_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8071 // CHECK: [0xf9,0x04,0xfe,0x33,0x01,0x06,0x06,0x06]
8072
8073 v_add_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8074 // CHECK: [0xf9,0x04,0x0a,0x32,0xff,0x06,0x06,0x06]
8075
8076 v_add_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8077 // CHECK: [0xf9,0xfe,0x0b,0x32,0x01,0x06,0x06,0x06]
8078
8079 v_add_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8080 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x26,0x06,0x06]
8081
8082 v_add_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8083 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
8084
8085 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8086 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x00,0x06,0x06]
8087
8088 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8089 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x01,0x06,0x06]
8090
8091 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8092 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x02,0x06,0x06]
8093
8094 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8095 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x03,0x06,0x06]
8096
8097 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8098 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x04,0x06,0x06]
8099
8100 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8101 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x05,0x06,0x06]
8102
8103 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
8104 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x0e,0x06,0x06]
8105
8106 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
8107 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x16,0x06,0x06]
8108
8109 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
8110 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x16,0x06,0x06]
8111
8112 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
8113 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
8114
8115 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
8116 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x00,0x06]
8117
8118 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
8119 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x01,0x06]
8120
8121 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
8122 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x02,0x06]
8123
8124 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
8125 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x03,0x06]
8126
8127 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
8128 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x04,0x06]
8129
8130 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
8131 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x05,0x06]
8132
8133 v_add_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8134 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x0e,0x06]
8135
8136 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
8137 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
8138
8139 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
8140 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x00]
8141
8142 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
8143 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x01]
8144
8145 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
8146 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x02]
8147
8148 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
8149 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x03]
8150
8151 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
8152 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x04]
8153
8154 v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
8155 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x05]
8156
8157 v_add_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8158 // CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x0e]
8159
8160 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8161 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x00]
8162
8163 v_add_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8164 // CHECK: [0xfa,0x04,0xfe,0x33,0x01,0xe4,0x00,0x00]
8165
8166 v_add_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8167 // CHECK: [0xfa,0x04,0x0a,0x32,0xff,0xe4,0x00,0x00]
8168
8169 v_add_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8170 // CHECK: [0xfa,0xfe,0x0b,0x32,0x01,0xe4,0x00,0x00]
8171
8172 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
8173 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0x00]
8174
8175 v_add_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
8176 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0x00]
8177
8178 v_add_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
8179 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0x00]
8180
8181 v_add_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
8182 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x42,0x01,0x00]
8183
8184 v_add_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
8185 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x43,0x01,0x00]
8186
8187 v_add_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
8188 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x30,0x01,0x00]
8189
8190 v_add_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
8191 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x34,0x01,0x00]
8192
8193 v_add_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
8194 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x38,0x01,0x00]
8195
8196 v_add_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
8197 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x3c,0x01,0x00]
8198
8199 v_add_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
8200 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0x00]
8201
8202 v_add_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
8203 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0x00]
8204
8205 v_add_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
8206 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0x00]
8207
8208 v_add_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
8209 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0x00]
8210
8211 v_add_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
8212 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0x00]
8213
8214 v_add_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
8215 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0x00]
8216
8217 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
8218 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x10]
8219
8220 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
8221 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x30]
8222
8223 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
8224 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xf0]
8225
8226 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
8227 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xf0]
8228
8229 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
8230 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x01]
8231
8232 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
8233 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x03]
8234
8235 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
8236 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f]
8237
8238 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
8239 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f]
8240
8241 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
8242 // CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x08,0x00]
8243
8244 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8245 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
8246
8247 v_sub_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8248 // CHECK: [0xf9,0x04,0xfe,0x35,0x01,0x06,0x06,0x06]
8249
8250 v_sub_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8251 // CHECK: [0xf9,0x04,0x0a,0x34,0xff,0x06,0x06,0x06]
8252
8253 v_sub_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8254 // CHECK: [0xf9,0xfe,0x0b,0x34,0x01,0x06,0x06,0x06]
8255
8256 v_sub_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8257 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x26,0x06,0x06]
8258
8259 v_sub_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8260 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
8261
8262 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8263 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x00,0x06,0x06]
8264
8265 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8266 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x01,0x06,0x06]
8267
8268 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8269 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x02,0x06,0x06]
8270
8271 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8272 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x03,0x06,0x06]
8273
8274 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8275 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x04,0x06,0x06]
8276
8277 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8278 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x05,0x06,0x06]
8279
8280 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
8281 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x0e,0x06,0x06]
8282
8283 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
8284 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
8285
8286 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
8287 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
8288
8289 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
8290 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
8291
8292 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
8293 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x00,0x06]
8294
8295 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
8296 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x01,0x06]
8297
8298 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
8299 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x02,0x06]
8300
8301 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
8302 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x03,0x06]
8303
8304 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
8305 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x04,0x06]
8306
8307 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
8308 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x05,0x06]
8309
8310 v_sub_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8311 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x0e,0x06]
8312
8313 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
8314 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
8315
8316 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
8317 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x00]
8318
8319 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
8320 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x01]
8321
8322 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
8323 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x02]
8324
8325 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
8326 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x03]
8327
8328 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
8329 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x04]
8330
8331 v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
8332 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x05]
8333
8334 v_sub_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8335 // CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x0e]
8336
8337 v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8338 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x00]
8339
8340 v_sub_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8341 // CHECK: [0xfa,0x04,0xfe,0x35,0x01,0xe4,0x00,0x00]
8342
8343 v_sub_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8344 // CHECK: [0xfa,0x04,0x0a,0x34,0xff,0xe4,0x00,0x00]
8345
8346 v_sub_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8347 // CHECK: [0xfa,0xfe,0x0b,0x34,0x01,0xe4,0x00,0x00]
8348
8349 v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
8350 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0x00]
8351
8352 v_sub_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
8353 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0x00]
8354
8355 v_sub_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
8356 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0x00]
8357
8358 v_sub_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
8359 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x42,0x01,0x00]
8360
8361 v_sub_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
8362 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x43,0x01,0x00]
8363
8364 v_sub_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
8365 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x30,0x01,0x00]
8366
8367 v_sub_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
8368 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x34,0x01,0x00]
8369
8370 v_sub_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
8371 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x38,0x01,0x00]
8372
8373 v_sub_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
8374 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x3c,0x01,0x00]
8375
8376 v_sub_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
8377 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0x00]
8378
8379 v_sub_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
8380 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0x00]
8381
8382 v_sub_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
8383 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0x00]
8384
8385 v_sub_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
8386 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0x00]
8387
8388 v_sub_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
8389 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0x00]
8390
8391 v_sub_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
8392 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0x00]
8393
8394 v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
8395 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x10]
8396
8397 v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
8398 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x30]
8399
8400 v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
8401 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xf0]
8402
8403 v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
8404 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xf0]
8405
8406 v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
8407 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x01]
8408
8409 v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
8410 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03]
8411
8412 v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
8413 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
8414
8415 v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
8416 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
8417
8418 v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
8419 // CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
8420
8421 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8422 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
8423
8424 v_subrev_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8425 // CHECK: [0xf9,0x04,0xfe,0x37,0x01,0x06,0x06,0x06]
8426
8427 v_subrev_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8428 // CHECK: [0xf9,0x04,0x0a,0x36,0xff,0x06,0x06,0x06]
8429
8430 v_subrev_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8431 // CHECK: [0xf9,0xfe,0x0b,0x36,0x01,0x06,0x06,0x06]
8432
8433 v_subrev_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8434 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x26,0x06,0x06]
8435
8436 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8437 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
8438
8439 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8440 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x00,0x06,0x06]
8441
8442 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8443 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x01,0x06,0x06]
8444
8445 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8446 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x02,0x06,0x06]
8447
8448 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8449 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x03,0x06,0x06]
8450
8451 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8452 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x04,0x06,0x06]
8453
8454 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8455 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x05,0x06,0x06]
8456
8457 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
8458 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x0e,0x06,0x06]
8459
8460 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
8461 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
8462
8463 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
8464 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
8465
8466 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
8467 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
8468
8469 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
8470 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x00,0x06]
8471
8472 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
8473 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x01,0x06]
8474
8475 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
8476 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x02,0x06]
8477
8478 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
8479 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x03,0x06]
8480
8481 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
8482 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x04,0x06]
8483
8484 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
8485 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x05,0x06]
8486
8487 v_subrev_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8488 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x0e,0x06]
8489
8490 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
8491 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
8492
8493 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
8494 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x00]
8495
8496 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
8497 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x01]
8498
8499 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
8500 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x02]
8501
8502 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
8503 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x03]
8504
8505 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
8506 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x04]
8507
8508 v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
8509 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x05]
8510
8511 v_subrev_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8512 // CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x0e]
8513
8514 v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8515 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x00]
8516
8517 v_subrev_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8518 // CHECK: [0xfa,0x04,0xfe,0x37,0x01,0xe4,0x00,0x00]
8519
8520 v_subrev_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8521 // CHECK: [0xfa,0x04,0x0a,0x36,0xff,0xe4,0x00,0x00]
8522
8523 v_subrev_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8524 // CHECK: [0xfa,0xfe,0x0b,0x36,0x01,0xe4,0x00,0x00]
8525
8526 v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
8527 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0x00]
8528
8529 v_subrev_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
8530 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0x00]
8531
8532 v_subrev_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
8533 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0x00]
8534
8535 v_subrev_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
8536 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x42,0x01,0x00]
8537
8538 v_subrev_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
8539 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x43,0x01,0x00]
8540
8541 v_subrev_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
8542 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x30,0x01,0x00]
8543
8544 v_subrev_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
8545 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x34,0x01,0x00]
8546
8547 v_subrev_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
8548 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x38,0x01,0x00]
8549
8550 v_subrev_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
8551 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x3c,0x01,0x00]
8552
8553 v_subrev_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
8554 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0x00]
8555
8556 v_subrev_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
8557 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0x00]
8558
8559 v_subrev_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
8560 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0x00]
8561
8562 v_subrev_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
8563 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0x00]
8564
8565 v_subrev_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
8566 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0x00]
8567
8568 v_subrev_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
8569 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0x00]
8570
8571 v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
8572 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x10]
8573
8574 v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
8575 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x30]
8576
8577 v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
8578 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xf0]
8579
8580 v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
8581 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xf0]
8582
8583 v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
8584 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x01]
8585
8586 v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
8587 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03]
8588
8589 v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
8590 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
8591
8592 v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
8593 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
8594
8595 v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
8596 // CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
8597
8598 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8599 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
8600
8601 v_addc_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8602 // CHECK: [0xf9,0x04,0xfe,0x39,0x01,0x06,0x06,0x06]
8603
8604 v_addc_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8605 // CHECK: [0xf9,0x04,0x0a,0x38,0xff,0x06,0x06,0x06]
8606
8607 v_addc_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8608 // CHECK: [0xf9,0xfe,0x0b,0x38,0x01,0x06,0x06,0x06]
8609
8610 v_addc_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8611 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x26,0x06,0x06]
8612
8613 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8614 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
8615
8616 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8617 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x00,0x06,0x06]
8618
8619 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8620 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x01,0x06,0x06]
8621
8622 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8623 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x02,0x06,0x06]
8624
8625 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8626 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x03,0x06,0x06]
8627
8628 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8629 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x04,0x06,0x06]
8630
8631 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8632 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x05,0x06,0x06]
8633
8634 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
8635 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x0e,0x06,0x06]
8636
8637 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
8638 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
8639
8640 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
8641 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
8642
8643 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
8644 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
8645
8646 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
8647 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x00,0x06]
8648
8649 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
8650 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x01,0x06]
8651
8652 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
8653 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x02,0x06]
8654
8655 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
8656 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x03,0x06]
8657
8658 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
8659 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x04,0x06]
8660
8661 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
8662 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x05,0x06]
8663
8664 v_addc_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8665 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x0e,0x06]
8666
8667 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
8668 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
8669
8670 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
8671 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x00]
8672
8673 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
8674 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x01]
8675
8676 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
8677 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x02]
8678
8679 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
8680 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x03]
8681
8682 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
8683 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x04]
8684
8685 v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
8686 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x05]
8687
8688 v_addc_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8689 // CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x0e]
8690
8691 v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8692 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x00]
8693
8694 v_addc_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8695 // CHECK: [0xfa,0x04,0xfe,0x39,0x01,0xe4,0x00,0x00]
8696
8697 v_addc_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8698 // CHECK: [0xfa,0x04,0x0a,0x38,0xff,0xe4,0x00,0x00]
8699
8700 v_addc_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8701 // CHECK: [0xfa,0xfe,0x0b,0x38,0x01,0xe4,0x00,0x00]
8702
8703 v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
8704 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0x00]
8705
8706 v_addc_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
8707 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0x00]
8708
8709 v_addc_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
8710 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0x00]
8711
8712 v_addc_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
8713 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x42,0x01,0x00]
8714
8715 v_addc_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
8716 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x43,0x01,0x00]
8717
8718 v_addc_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
8719 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x30,0x01,0x00]
8720
8721 v_addc_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
8722 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x34,0x01,0x00]
8723
8724 v_addc_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
8725 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x38,0x01,0x00]
8726
8727 v_addc_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
8728 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x3c,0x01,0x00]
8729
8730 v_addc_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
8731 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0x00]
8732
8733 v_addc_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
8734 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0x00]
8735
8736 v_addc_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
8737 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0x00]
8738
8739 v_addc_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
8740 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0x00]
8741
8742 v_addc_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
8743 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0x00]
8744
8745 v_addc_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
8746 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0x00]
8747
8748 v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
8749 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x10]
8750
8751 v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
8752 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x30]
8753
8754 v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
8755 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xf0]
8756
8757 v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
8758 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xf0]
8759
8760 v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
8761 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x01]
8762
8763 v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
8764 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03]
8765
8766 v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
8767 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
8768
8769 v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
8770 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
8771
8772 v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
8773 // CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
8774
8775 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8776 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
8777
8778 v_subb_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8779 // CHECK: [0xf9,0x04,0xfe,0x3b,0x01,0x06,0x06,0x06]
8780
8781 v_subb_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8782 // CHECK: [0xf9,0x04,0x0a,0x3a,0xff,0x06,0x06,0x06]
8783
8784 v_subb_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8785 // CHECK: [0xf9,0xfe,0x0b,0x3a,0x01,0x06,0x06,0x06]
8786
8787 v_subb_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8788 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x26,0x06,0x06]
8789
8790 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8791 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
8792
8793 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8794 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x00,0x06,0x06]
8795
8796 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8797 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x01,0x06,0x06]
8798
8799 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8800 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x02,0x06,0x06]
8801
8802 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8803 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x03,0x06,0x06]
8804
8805 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8806 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x04,0x06,0x06]
8807
8808 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8809 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x05,0x06,0x06]
8810
8811 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
8812 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x0e,0x06,0x06]
8813
8814 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
8815 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
8816
8817 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
8818 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
8819
8820 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
8821 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
8822
8823 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
8824 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x00,0x06]
8825
8826 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
8827 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x01,0x06]
8828
8829 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
8830 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x02,0x06]
8831
8832 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
8833 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x03,0x06]
8834
8835 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
8836 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x04,0x06]
8837
8838 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
8839 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x05,0x06]
8840
8841 v_subb_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8842 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x0e,0x06]
8843
8844 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
8845 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
8846
8847 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
8848 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x00]
8849
8850 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
8851 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x01]
8852
8853 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
8854 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x02]
8855
8856 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
8857 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x03]
8858
8859 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
8860 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x04]
8861
8862 v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
8863 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x05]
8864
8865 v_subb_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8866 // CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x0e]
8867
8868 v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8869 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x00]
8870
8871 v_subb_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8872 // CHECK: [0xfa,0x04,0xfe,0x3b,0x01,0xe4,0x00,0x00]
8873
8874 v_subb_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8875 // CHECK: [0xfa,0x04,0x0a,0x3a,0xff,0xe4,0x00,0x00]
8876
8877 v_subb_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
8878 // CHECK: [0xfa,0xfe,0x0b,0x3a,0x01,0xe4,0x00,0x00]
8879
8880 v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
8881 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0x00]
8882
8883 v_subb_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
8884 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0x00]
8885
8886 v_subb_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
8887 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0x00]
8888
8889 v_subb_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
8890 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x42,0x01,0x00]
8891
8892 v_subb_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
8893 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x43,0x01,0x00]
8894
8895 v_subb_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
8896 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x30,0x01,0x00]
8897
8898 v_subb_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
8899 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x34,0x01,0x00]
8900
8901 v_subb_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
8902 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x38,0x01,0x00]
8903
8904 v_subb_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
8905 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x3c,0x01,0x00]
8906
8907 v_subb_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
8908 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0x00]
8909
8910 v_subb_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
8911 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0x00]
8912
8913 v_subb_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
8914 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0x00]
8915
8916 v_subb_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
8917 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0x00]
8918
8919 v_subb_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
8920 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0x00]
8921
8922 v_subb_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
8923 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0x00]
8924
8925 v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
8926 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x10]
8927
8928 v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
8929 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x30]
8930
8931 v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
8932 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xf0]
8933
8934 v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
8935 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xf0]
8936
8937 v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
8938 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x01]
8939
8940 v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
8941 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03]
8942
8943 v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
8944 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
8945
8946 v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
8947 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
8948
8949 v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
8950 // CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
8951
8952 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8953 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
8954
8955 v_subbrev_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8956 // CHECK: [0xf9,0x04,0xfe,0x3d,0x01,0x06,0x06,0x06]
8957
8958 v_subbrev_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8959 // CHECK: [0xf9,0x04,0x0a,0x3c,0xff,0x06,0x06,0x06]
8960
8961 v_subbrev_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8962 // CHECK: [0xf9,0xfe,0x0b,0x3c,0x01,0x06,0x06,0x06]
8963
8964 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8965 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x26,0x06,0x06]
8966
8967 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8968 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
8969
8970 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8971 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x00,0x06,0x06]
8972
8973 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8974 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x01,0x06,0x06]
8975
8976 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8977 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x02,0x06,0x06]
8978
8979 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8980 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x03,0x06,0x06]
8981
8982 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8983 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x04,0x06,0x06]
8984
8985 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
8986 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x05,0x06,0x06]
8987
8988 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
8989 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x0e,0x06,0x06]
8990
8991 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
8992 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
8993
8994 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
8995 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
8996
8997 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
8998 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
8999
9000 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
9001 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x00,0x06]
9002
9003 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
9004 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x01,0x06]
9005
9006 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
9007 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x02,0x06]
9008
9009 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
9010 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x03,0x06]
9011
9012 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
9013 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x04,0x06]
9014
9015 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
9016 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x05,0x06]
9017
9018 v_subbrev_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9019 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x0e,0x06]
9020
9021 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
9022 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
9023
9024 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
9025 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x00]
9026
9027 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
9028 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x01]
9029
9030 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
9031 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x02]
9032
9033 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
9034 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x03]
9035
9036 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
9037 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x04]
9038
9039 v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
9040 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x05]
9041
9042 v_subbrev_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9043 // CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x0e]
9044
9045 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9046 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x00]
9047
9048 v_subbrev_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9049 // CHECK: [0xfa,0x04,0xfe,0x3d,0x01,0xe4,0x00,0x00]
9050
9051 v_subbrev_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9052 // CHECK: [0xfa,0x04,0x0a,0x3c,0xff,0xe4,0x00,0x00]
9053
9054 v_subbrev_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9055 // CHECK: [0xfa,0xfe,0x0b,0x3c,0x01,0xe4,0x00,0x00]
9056
9057 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
9058 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0x00]
9059
9060 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
9061 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0x00]
9062
9063 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
9064 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0x00]
9065
9066 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
9067 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x42,0x01,0x00]
9068
9069 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
9070 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x43,0x01,0x00]
9071
9072 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
9073 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x30,0x01,0x00]
9074
9075 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
9076 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x34,0x01,0x00]
9077
9078 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
9079 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x38,0x01,0x00]
9080
9081 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
9082 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x3c,0x01,0x00]
9083
9084 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
9085 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0x00]
9086
9087 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
9088 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0x00]
9089
9090 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
9091 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0x00]
9092
9093 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
9094 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0x00]
9095
9096 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
9097 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0x00]
9098
9099 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
9100 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0x00]
9101
9102 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
9103 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x10]
9104
9105 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
9106 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x30]
9107
9108 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
9109 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xf0]
9110
9111 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
9112 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xf0]
9113
9114 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
9115 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x01]
9116
9117 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
9118 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03]
9119
9120 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
9121 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
9122
9123 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
9124 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
9125
9126 v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
9127 // CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
9128
9129 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9130 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
9131
9132 v_add_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9133 // CHECK: [0xf9,0x04,0xfe,0x3f,0x01,0x06,0x06,0x06]
9134
9135 v_add_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9136 // CHECK: [0xf9,0x04,0x0a,0x3e,0xff,0x06,0x06,0x06]
9137
9138 v_add_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9139 // CHECK: [0xf9,0xfe,0x0b,0x3e,0x01,0x06,0x06,0x06]
9140
9141 v_add_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9142 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x26,0x06,0x06]
9143
9144 v_add_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9145 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
9146
9147 v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9148 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x00,0x06,0x06]
9149
9150 v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9151 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x01,0x06,0x06]
9152
9153 v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9154 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x02,0x06,0x06]
9155
9156 v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9157 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x03,0x06,0x06]
9158
9159 v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9160 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x04,0x06,0x06]
9161
9162 v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9163 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x05,0x06,0x06]
9164
9165 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
9166 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x0e,0x06,0x06]
9167
9168 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
9169 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x16,0x06,0x06]
9170
9171 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
9172 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x16,0x06,0x06]
9173
9174 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
9175 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
9176
9177 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
9178 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x00,0x06]
9179
9180 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
9181 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x01,0x06]
9182
9183 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
9184 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x02,0x06]
9185
9186 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
9187 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x03,0x06]
9188
9189 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
9190 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x04,0x06]
9191
9192 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
9193 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x05,0x06]
9194
9195 v_add_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9196 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x16,0x06]
9197
9198 v_add_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9199 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x26,0x06]
9200
9201 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
9202 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
9203
9204 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
9205 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x00]
9206
9207 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
9208 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x01]
9209
9210 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
9211 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x02]
9212
9213 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
9214 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x03]
9215
9216 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
9217 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x04]
9218
9219 v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
9220 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x05]
9221
9222 v_add_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9223 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x16]
9224
9225 v_add_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9226 // CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x26]
9227
9228 v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9229 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x00]
9230
9231 v_add_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9232 // CHECK: [0xfa,0x04,0xfe,0x3f,0x01,0xe4,0x00,0x00]
9233
9234 v_add_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9235 // CHECK: [0xfa,0x04,0x0a,0x3e,0xff,0xe4,0x00,0x00]
9236
9237 v_add_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9238 // CHECK: [0xfa,0xfe,0x0b,0x3e,0x01,0xe4,0x00,0x00]
9239
9240 v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
9241 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x1b,0x00,0x00]
9242
9243 v_add_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
9244 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x40,0x01,0x00]
9245
9246 v_add_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
9247 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x41,0x01,0x00]
9248
9249 v_add_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
9250 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x42,0x01,0x00]
9251
9252 v_add_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
9253 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x43,0x01,0x00]
9254
9255 v_add_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
9256 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x30,0x01,0x00]
9257
9258 v_add_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
9259 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x34,0x01,0x00]
9260
9261 v_add_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
9262 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x38,0x01,0x00]
9263
9264 v_add_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
9265 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x3c,0x01,0x00]
9266
9267 v_add_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
9268 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x01,0x01,0x00]
9269
9270 v_add_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
9271 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x0f,0x01,0x00]
9272
9273 v_add_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
9274 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x11,0x01,0x00]
9275
9276 v_add_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
9277 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x1f,0x01,0x00]
9278
9279 v_add_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
9280 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x21,0x01,0x00]
9281
9282 v_add_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
9283 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x2f,0x01,0x00]
9284
9285 v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
9286 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x10]
9287
9288 v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
9289 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x30]
9290
9291 v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
9292 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0xf0]
9293
9294 v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
9295 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0xf0]
9296
9297 v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
9298 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x01]
9299
9300 v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
9301 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x03]
9302
9303 v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
9304 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f]
9305
9306 v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
9307 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f]
9308
9309 v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
9310 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x08,0x00]
9311
9312 v_add_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9313 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x10,0x00]
9314
9315 v_add_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9316 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x20,0x00]
9317
9318 v_add_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9319 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x40,0x00]
9320
9321 v_add_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9322 // CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x80,0x00]
9323
9324 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9325 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
9326
9327 v_sub_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9328 // CHECK: [0xf9,0x04,0xfe,0x41,0x01,0x06,0x06,0x06]
9329
9330 v_sub_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9331 // CHECK: [0xf9,0x04,0x0a,0x40,0xff,0x06,0x06,0x06]
9332
9333 v_sub_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9334 // CHECK: [0xf9,0xfe,0x0b,0x40,0x01,0x06,0x06,0x06]
9335
9336 v_sub_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9337 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x26,0x06,0x06]
9338
9339 v_sub_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9340 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
9341
9342 v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9343 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x00,0x06,0x06]
9344
9345 v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9346 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x01,0x06,0x06]
9347
9348 v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9349 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x02,0x06,0x06]
9350
9351 v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9352 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x03,0x06,0x06]
9353
9354 v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9355 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x04,0x06,0x06]
9356
9357 v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9358 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x05,0x06,0x06]
9359
9360 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
9361 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x0e,0x06,0x06]
9362
9363 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
9364 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x16,0x06,0x06]
9365
9366 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
9367 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x16,0x06,0x06]
9368
9369 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
9370 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
9371
9372 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
9373 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x00,0x06]
9374
9375 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
9376 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x01,0x06]
9377
9378 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
9379 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x02,0x06]
9380
9381 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
9382 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x03,0x06]
9383
9384 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
9385 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x04,0x06]
9386
9387 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
9388 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x05,0x06]
9389
9390 v_sub_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9391 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x16,0x06]
9392
9393 v_sub_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9394 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x26,0x06]
9395
9396 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
9397 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
9398
9399 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
9400 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x00]
9401
9402 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
9403 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x01]
9404
9405 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
9406 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x02]
9407
9408 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
9409 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x03]
9410
9411 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
9412 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x04]
9413
9414 v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
9415 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x05]
9416
9417 v_sub_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9418 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x16]
9419
9420 v_sub_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9421 // CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x26]
9422
9423 v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9424 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x00]
9425
9426 v_sub_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9427 // CHECK: [0xfa,0x04,0xfe,0x41,0x01,0xe4,0x00,0x00]
9428
9429 v_sub_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9430 // CHECK: [0xfa,0x04,0x0a,0x40,0xff,0xe4,0x00,0x00]
9431
9432 v_sub_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9433 // CHECK: [0xfa,0xfe,0x0b,0x40,0x01,0xe4,0x00,0x00]
9434
9435 v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
9436 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0x00]
9437
9438 v_sub_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
9439 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0x00]
9440
9441 v_sub_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
9442 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0x00]
9443
9444 v_sub_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
9445 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x42,0x01,0x00]
9446
9447 v_sub_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
9448 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x43,0x01,0x00]
9449
9450 v_sub_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
9451 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x30,0x01,0x00]
9452
9453 v_sub_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
9454 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x34,0x01,0x00]
9455
9456 v_sub_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
9457 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x38,0x01,0x00]
9458
9459 v_sub_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
9460 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x3c,0x01,0x00]
9461
9462 v_sub_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
9463 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0x00]
9464
9465 v_sub_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
9466 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0x00]
9467
9468 v_sub_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
9469 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0x00]
9470
9471 v_sub_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
9472 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0x00]
9473
9474 v_sub_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
9475 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0x00]
9476
9477 v_sub_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
9478 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0x00]
9479
9480 v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
9481 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x10]
9482
9483 v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
9484 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x30]
9485
9486 v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
9487 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xf0]
9488
9489 v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
9490 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xf0]
9491
9492 v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
9493 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x01]
9494
9495 v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
9496 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x03]
9497
9498 v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
9499 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f]
9500
9501 v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
9502 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f]
9503
9504 v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
9505 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x08,0x00]
9506
9507 v_sub_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9508 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x10,0x00]
9509
9510 v_sub_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9511 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x20,0x00]
9512
9513 v_sub_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9514 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x40,0x00]
9515
9516 v_sub_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9517 // CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x80,0x00]
9518
9519 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9520 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
9521
9522 v_subrev_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9523 // CHECK: [0xf9,0x04,0xfe,0x43,0x01,0x06,0x06,0x06]
9524
9525 v_subrev_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9526 // CHECK: [0xf9,0x04,0x0a,0x42,0xff,0x06,0x06,0x06]
9527
9528 v_subrev_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9529 // CHECK: [0xf9,0xfe,0x0b,0x42,0x01,0x06,0x06,0x06]
9530
9531 v_subrev_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9532 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x26,0x06,0x06]
9533
9534 v_subrev_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9535 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
9536
9537 v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9538 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x00,0x06,0x06]
9539
9540 v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9541 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x01,0x06,0x06]
9542
9543 v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9544 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x02,0x06,0x06]
9545
9546 v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9547 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x03,0x06,0x06]
9548
9549 v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9550 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x04,0x06,0x06]
9551
9552 v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9553 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x05,0x06,0x06]
9554
9555 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
9556 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x0e,0x06,0x06]
9557
9558 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
9559 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x16,0x06,0x06]
9560
9561 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
9562 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x16,0x06,0x06]
9563
9564 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
9565 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
9566
9567 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
9568 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x00,0x06]
9569
9570 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
9571 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x01,0x06]
9572
9573 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
9574 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x02,0x06]
9575
9576 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
9577 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x03,0x06]
9578
9579 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
9580 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x04,0x06]
9581
9582 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
9583 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x05,0x06]
9584
9585 v_subrev_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9586 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x16,0x06]
9587
9588 v_subrev_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9589 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x26,0x06]
9590
9591 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
9592 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
9593
9594 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
9595 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x00]
9596
9597 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
9598 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x01]
9599
9600 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
9601 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x02]
9602
9603 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
9604 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x03]
9605
9606 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
9607 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x04]
9608
9609 v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
9610 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x05]
9611
9612 v_subrev_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9613 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x16]
9614
9615 v_subrev_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9616 // CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x26]
9617
9618 v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9619 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x00]
9620
9621 v_subrev_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9622 // CHECK: [0xfa,0x04,0xfe,0x43,0x01,0xe4,0x00,0x00]
9623
9624 v_subrev_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9625 // CHECK: [0xfa,0x04,0x0a,0x42,0xff,0xe4,0x00,0x00]
9626
9627 v_subrev_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9628 // CHECK: [0xfa,0xfe,0x0b,0x42,0x01,0xe4,0x00,0x00]
9629
9630 v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
9631 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0x00]
9632
9633 v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
9634 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0x00]
9635
9636 v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
9637 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0x00]
9638
9639 v_subrev_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
9640 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x42,0x01,0x00]
9641
9642 v_subrev_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
9643 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x43,0x01,0x00]
9644
9645 v_subrev_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
9646 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x30,0x01,0x00]
9647
9648 v_subrev_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
9649 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x34,0x01,0x00]
9650
9651 v_subrev_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
9652 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x38,0x01,0x00]
9653
9654 v_subrev_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
9655 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x3c,0x01,0x00]
9656
9657 v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
9658 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0x00]
9659
9660 v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
9661 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0x00]
9662
9663 v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
9664 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0x00]
9665
9666 v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
9667 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0x00]
9668
9669 v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
9670 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0x00]
9671
9672 v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
9673 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0x00]
9674
9675 v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
9676 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x10]
9677
9678 v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
9679 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x30]
9680
9681 v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
9682 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xf0]
9683
9684 v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
9685 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xf0]
9686
9687 v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
9688 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x01]
9689
9690 v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
9691 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x03]
9692
9693 v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
9694 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f]
9695
9696 v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
9697 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f]
9698
9699 v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
9700 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x08,0x00]
9701
9702 v_subrev_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9703 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x10,0x00]
9704
9705 v_subrev_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9706 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x20,0x00]
9707
9708 v_subrev_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9709 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x40,0x00]
9710
9711 v_subrev_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9712 // CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x80,0x00]
9713
9714 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9715 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
9716
9717 v_mul_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9718 // CHECK: [0xf9,0x04,0xfe,0x45,0x01,0x06,0x06,0x06]
9719
9720 v_mul_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9721 // CHECK: [0xf9,0x04,0x0a,0x44,0xff,0x06,0x06,0x06]
9722
9723 v_mul_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9724 // CHECK: [0xf9,0xfe,0x0b,0x44,0x01,0x06,0x06,0x06]
9725
9726 v_mul_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9727 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x26,0x06,0x06]
9728
9729 v_mul_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9730 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
9731
9732 v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9733 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x00,0x06,0x06]
9734
9735 v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9736 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x01,0x06,0x06]
9737
9738 v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9739 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x02,0x06,0x06]
9740
9741 v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9742 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x03,0x06,0x06]
9743
9744 v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9745 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x04,0x06,0x06]
9746
9747 v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9748 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x05,0x06,0x06]
9749
9750 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
9751 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x0e,0x06,0x06]
9752
9753 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
9754 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x16,0x06,0x06]
9755
9756 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
9757 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x16,0x06,0x06]
9758
9759 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
9760 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
9761
9762 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
9763 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x00,0x06]
9764
9765 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
9766 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x01,0x06]
9767
9768 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
9769 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x02,0x06]
9770
9771 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
9772 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x03,0x06]
9773
9774 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
9775 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x04,0x06]
9776
9777 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
9778 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x05,0x06]
9779
9780 v_mul_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9781 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x16,0x06]
9782
9783 v_mul_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9784 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x26,0x06]
9785
9786 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
9787 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
9788
9789 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
9790 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x00]
9791
9792 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
9793 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x01]
9794
9795 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
9796 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x02]
9797
9798 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
9799 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x03]
9800
9801 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
9802 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x04]
9803
9804 v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
9805 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x05]
9806
9807 v_mul_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9808 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x16]
9809
9810 v_mul_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9811 // CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x26]
9812
9813 v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9814 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x00]
9815
9816 v_mul_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9817 // CHECK: [0xfa,0x04,0xfe,0x45,0x01,0xe4,0x00,0x00]
9818
9819 v_mul_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9820 // CHECK: [0xfa,0x04,0x0a,0x44,0xff,0xe4,0x00,0x00]
9821
9822 v_mul_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9823 // CHECK: [0xfa,0xfe,0x0b,0x44,0x01,0xe4,0x00,0x00]
9824
9825 v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
9826 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0x00]
9827
9828 v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
9829 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0x00]
9830
9831 v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
9832 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0x00]
9833
9834 v_mul_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
9835 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x42,0x01,0x00]
9836
9837 v_mul_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
9838 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x43,0x01,0x00]
9839
9840 v_mul_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
9841 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x30,0x01,0x00]
9842
9843 v_mul_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
9844 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x34,0x01,0x00]
9845
9846 v_mul_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
9847 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x38,0x01,0x00]
9848
9849 v_mul_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
9850 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x3c,0x01,0x00]
9851
9852 v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
9853 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0x00]
9854
9855 v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
9856 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0x00]
9857
9858 v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
9859 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0x00]
9860
9861 v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
9862 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0x00]
9863
9864 v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
9865 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0x00]
9866
9867 v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
9868 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0x00]
9869
9870 v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
9871 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x10]
9872
9873 v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
9874 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x30]
9875
9876 v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
9877 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xf0]
9878
9879 v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
9880 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xf0]
9881
9882 v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
9883 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x01]
9884
9885 v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
9886 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x03]
9887
9888 v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
9889 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f]
9890
9891 v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
9892 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f]
9893
9894 v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
9895 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x08,0x00]
9896
9897 v_mul_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9898 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x10,0x00]
9899
9900 v_mul_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9901 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x20,0x00]
9902
9903 v_mul_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9904 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x40,0x00]
9905
9906 v_mul_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9907 // CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x80,0x00]
9908
9909 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9910 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x06]
9911
9912 v_mac_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9913 // CHECK: [0xf9,0x04,0xfe,0x47,0x01,0x06,0x06,0x06]
9914
9915 v_mac_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9916 // CHECK: [0xf9,0x04,0x0a,0x46,0xff,0x06,0x06,0x06]
9917
9918 v_mac_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9919 // CHECK: [0xf9,0xfe,0x0b,0x46,0x01,0x06,0x06,0x06]
9920
9921 v_mac_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9922 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x26,0x06,0x06]
9923
9924 v_mac_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9925 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x06]
9926
9927 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
9928 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x0e,0x06,0x06]
9929
9930 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
9931 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x16,0x06,0x06]
9932
9933 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
9934 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x16,0x06,0x06]
9935
9936 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
9937 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x06]
9938
9939 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
9940 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x00,0x06]
9941
9942 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
9943 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x01,0x06]
9944
9945 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
9946 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x02,0x06]
9947
9948 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
9949 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x03,0x06]
9950
9951 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
9952 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x04,0x06]
9953
9954 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
9955 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x05,0x06]
9956
9957 v_mac_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9958 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x16,0x06]
9959
9960 v_mac_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9961 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x26,0x06]
9962
9963 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
9964 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x06]
9965
9966 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
9967 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x00]
9968
9969 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
9970 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x01]
9971
9972 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
9973 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x02]
9974
9975 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
9976 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x03]
9977
9978 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
9979 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x04]
9980
9981 v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
9982 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x05]
9983
9984 v_mac_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9985 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x16]
9986
9987 v_mac_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
9988 // CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x26]
9989
9990 v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9991 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x00]
9992
9993 v_mac_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9994 // CHECK: [0xfa,0x04,0xfe,0x47,0x01,0xe4,0x00,0x00]
9995
9996 v_mac_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
9997 // CHECK: [0xfa,0x04,0x0a,0x46,0xff,0xe4,0x00,0x00]
9998
9999 v_mac_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10000 // CHECK: [0xfa,0xfe,0x0b,0x46,0x01,0xe4,0x00,0x00]
10001
10002 v_mac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
10003 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x1b,0x00,0x00]
10004
10005 v_mac_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
10006 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x40,0x01,0x00]
10007
10008 v_mac_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
10009 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x41,0x01,0x00]
10010
10011 v_mac_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
10012 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x42,0x01,0x00]
10013
10014 v_mac_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
10015 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x43,0x01,0x00]
10016
10017 v_mac_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
10018 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x30,0x01,0x00]
10019
10020 v_mac_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
10021 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x34,0x01,0x00]
10022
10023 v_mac_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
10024 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x38,0x01,0x00]
10025
10026 v_mac_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
10027 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x3c,0x01,0x00]
10028
10029 v_mac_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
10030 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x01,0x01,0x00]
10031
10032 v_mac_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
10033 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x0f,0x01,0x00]
10034
10035 v_mac_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
10036 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x11,0x01,0x00]
10037
10038 v_mac_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
10039 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x1f,0x01,0x00]
10040
10041 v_mac_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
10042 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x21,0x01,0x00]
10043
10044 v_mac_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
10045 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x2f,0x01,0x00]
10046
10047 v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
10048 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x10]
10049
10050 v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
10051 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x30]
10052
10053 v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
10054 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0xf0]
10055
10056 v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
10057 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0xf0]
10058
10059 v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
10060 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x01]
10061
10062 v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
10063 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x03]
10064
10065 v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
10066 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f]
10067
10068 v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
10069 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f]
10070
10071 v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
10072 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x08,0x00]
10073
10074 v_mac_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10075 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x10,0x00]
10076
10077 v_mac_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10078 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x20,0x00]
10079
10080 v_mac_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10081 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x40,0x00]
10082
10083 v_mac_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10084 // CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x80,0x00]
10085
10086 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10087 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
10088
10089 v_add_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10090 // CHECK: [0xf9,0x04,0xfe,0x4d,0x01,0x06,0x06,0x06]
10091
10092 v_add_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10093 // CHECK: [0xf9,0x04,0x0a,0x4c,0xff,0x06,0x06,0x06]
10094
10095 v_add_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10096 // CHECK: [0xf9,0xfe,0x0b,0x4c,0x01,0x06,0x06,0x06]
10097
10098 v_add_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10099 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x26,0x06,0x06]
10100
10101 v_add_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10102 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
10103
10104 v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10105 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x00,0x06,0x06]
10106
10107 v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10108 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x01,0x06,0x06]
10109
10110 v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10111 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x02,0x06,0x06]
10112
10113 v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10114 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x03,0x06,0x06]
10115
10116 v_add_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10117 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x04,0x06,0x06]
10118
10119 v_add_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10120 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x05,0x06,0x06]
10121
10122 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
10123 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x0e,0x06,0x06]
10124
10125 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
10126 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
10127
10128 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
10129 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
10130
10131 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
10132 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
10133
10134 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
10135 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x00,0x06]
10136
10137 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
10138 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x01,0x06]
10139
10140 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
10141 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x02,0x06]
10142
10143 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
10144 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x03,0x06]
10145
10146 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
10147 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x04,0x06]
10148
10149 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
10150 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x05,0x06]
10151
10152 v_add_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10153 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x0e,0x06]
10154
10155 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
10156 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
10157
10158 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
10159 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x00]
10160
10161 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
10162 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x01]
10163
10164 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
10165 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x02]
10166
10167 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
10168 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x03]
10169
10170 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
10171 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x04]
10172
10173 v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
10174 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x05]
10175
10176 v_add_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10177 // CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x0e]
10178
10179 v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10180 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x00]
10181
10182 v_add_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10183 // CHECK: [0xfa,0x04,0xfe,0x4d,0x01,0xe4,0x00,0x00]
10184
10185 v_add_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10186 // CHECK: [0xfa,0x04,0x0a,0x4c,0xff,0xe4,0x00,0x00]
10187
10188 v_add_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10189 // CHECK: [0xfa,0xfe,0x0b,0x4c,0x01,0xe4,0x00,0x00]
10190
10191 v_add_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
10192 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0x00]
10193
10194 v_add_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
10195 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0x00]
10196
10197 v_add_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
10198 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0x00]
10199
10200 v_add_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
10201 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x42,0x01,0x00]
10202
10203 v_add_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
10204 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x43,0x01,0x00]
10205
10206 v_add_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
10207 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x30,0x01,0x00]
10208
10209 v_add_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
10210 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x34,0x01,0x00]
10211
10212 v_add_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
10213 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x38,0x01,0x00]
10214
10215 v_add_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
10216 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x3c,0x01,0x00]
10217
10218 v_add_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
10219 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0x00]
10220
10221 v_add_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
10222 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0x00]
10223
10224 v_add_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
10225 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0x00]
10226
10227 v_add_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
10228 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0x00]
10229
10230 v_add_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
10231 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0x00]
10232
10233 v_add_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
10234 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0x00]
10235
10236 v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
10237 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x10]
10238
10239 v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
10240 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x30]
10241
10242 v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
10243 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xf0]
10244
10245 v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
10246 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xf0]
10247
10248 v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
10249 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x01]
10250
10251 v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
10252 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x03]
10253
10254 v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
10255 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f]
10256
10257 v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
10258 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f]
10259
10260 v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
10261 // CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x08,0x00]
10262
10263 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10264 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
10265
10266 v_sub_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10267 // CHECK: [0xf9,0x04,0xfe,0x4f,0x01,0x06,0x06,0x06]
10268
10269 v_sub_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10270 // CHECK: [0xf9,0x04,0x0a,0x4e,0xff,0x06,0x06,0x06]
10271
10272 v_sub_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10273 // CHECK: [0xf9,0xfe,0x0b,0x4e,0x01,0x06,0x06,0x06]
10274
10275 v_sub_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10276 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x26,0x06,0x06]
10277
10278 v_sub_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10279 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
10280
10281 v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10282 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x00,0x06,0x06]
10283
10284 v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10285 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x01,0x06,0x06]
10286
10287 v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10288 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x02,0x06,0x06]
10289
10290 v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10291 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x03,0x06,0x06]
10292
10293 v_sub_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10294 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x04,0x06,0x06]
10295
10296 v_sub_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10297 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x05,0x06,0x06]
10298
10299 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
10300 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x0e,0x06,0x06]
10301
10302 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
10303 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
10304
10305 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
10306 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
10307
10308 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
10309 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
10310
10311 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
10312 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x00,0x06]
10313
10314 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
10315 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x01,0x06]
10316
10317 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
10318 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x02,0x06]
10319
10320 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
10321 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x03,0x06]
10322
10323 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
10324 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x04,0x06]
10325
10326 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
10327 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x05,0x06]
10328
10329 v_sub_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10330 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x0e,0x06]
10331
10332 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
10333 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
10334
10335 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
10336 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x00]
10337
10338 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
10339 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x01]
10340
10341 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
10342 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x02]
10343
10344 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
10345 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x03]
10346
10347 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
10348 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x04]
10349
10350 v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
10351 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x05]
10352
10353 v_sub_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10354 // CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x0e]
10355
10356 v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10357 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x00]
10358
10359 v_sub_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10360 // CHECK: [0xfa,0x04,0xfe,0x4f,0x01,0xe4,0x00,0x00]
10361
10362 v_sub_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10363 // CHECK: [0xfa,0x04,0x0a,0x4e,0xff,0xe4,0x00,0x00]
10364
10365 v_sub_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10366 // CHECK: [0xfa,0xfe,0x0b,0x4e,0x01,0xe4,0x00,0x00]
10367
10368 v_sub_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
10369 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0x00]
10370
10371 v_sub_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
10372 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0x00]
10373
10374 v_sub_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
10375 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0x00]
10376
10377 v_sub_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
10378 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x42,0x01,0x00]
10379
10380 v_sub_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
10381 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x43,0x01,0x00]
10382
10383 v_sub_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
10384 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x30,0x01,0x00]
10385
10386 v_sub_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
10387 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x34,0x01,0x00]
10388
10389 v_sub_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
10390 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x38,0x01,0x00]
10391
10392 v_sub_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
10393 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x3c,0x01,0x00]
10394
10395 v_sub_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
10396 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0x00]
10397
10398 v_sub_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
10399 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0x00]
10400
10401 v_sub_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
10402 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0x00]
10403
10404 v_sub_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
10405 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0x00]
10406
10407 v_sub_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
10408 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0x00]
10409
10410 v_sub_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
10411 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0x00]
10412
10413 v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
10414 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x10]
10415
10416 v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
10417 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x30]
10418
10419 v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
10420 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xf0]
10421
10422 v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
10423 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xf0]
10424
10425 v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
10426 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x01]
10427
10428 v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
10429 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x03]
10430
10431 v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
10432 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f]
10433
10434 v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
10435 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f]
10436
10437 v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
10438 // CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x08,0x00]
10439
10440 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10441 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
10442
10443 v_subrev_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10444 // CHECK: [0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06]
10445
10446 v_subrev_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10447 // CHECK: [0xf9,0x04,0x0a,0x50,0xff,0x06,0x06,0x06]
10448
10449 v_subrev_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10450 // CHECK: [0xf9,0xfe,0x0b,0x50,0x01,0x06,0x06,0x06]
10451
10452 v_subrev_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10453 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x26,0x06,0x06]
10454
10455 v_subrev_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10456 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
10457
10458 v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10459 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x00,0x06,0x06]
10460
10461 v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10462 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x01,0x06,0x06]
10463
10464 v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10465 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x02,0x06,0x06]
10466
10467 v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10468 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x03,0x06,0x06]
10469
10470 v_subrev_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10471 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x04,0x06,0x06]
10472
10473 v_subrev_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10474 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x05,0x06,0x06]
10475
10476 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
10477 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x0e,0x06,0x06]
10478
10479 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
10480 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
10481
10482 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
10483 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
10484
10485 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
10486 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
10487
10488 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
10489 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x00,0x06]
10490
10491 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
10492 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x01,0x06]
10493
10494 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
10495 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x02,0x06]
10496
10497 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
10498 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x03,0x06]
10499
10500 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
10501 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x04,0x06]
10502
10503 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
10504 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x05,0x06]
10505
10506 v_subrev_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10507 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x0e,0x06]
10508
10509 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
10510 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
10511
10512 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
10513 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x00]
10514
10515 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
10516 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x01]
10517
10518 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
10519 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x02]
10520
10521 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
10522 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x03]
10523
10524 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
10525 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x04]
10526
10527 v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
10528 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x05]
10529
10530 v_subrev_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10531 // CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x0e]
10532
10533 v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10534 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x00]
10535
10536 v_subrev_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10537 // CHECK: [0xfa,0x04,0xfe,0x51,0x01,0xe4,0x00,0x00]
10538
10539 v_subrev_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10540 // CHECK: [0xfa,0x04,0x0a,0x50,0xff,0xe4,0x00,0x00]
10541
10542 v_subrev_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10543 // CHECK: [0xfa,0xfe,0x0b,0x50,0x01,0xe4,0x00,0x00]
10544
10545 v_subrev_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
10546 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x00,0x00]
10547
10548 v_subrev_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
10549 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x40,0x01,0x00]
10550
10551 v_subrev_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
10552 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x41,0x01,0x00]
10553
10554 v_subrev_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
10555 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x42,0x01,0x00]
10556
10557 v_subrev_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
10558 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x43,0x01,0x00]
10559
10560 v_subrev_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
10561 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x30,0x01,0x00]
10562
10563 v_subrev_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
10564 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x34,0x01,0x00]
10565
10566 v_subrev_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
10567 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x38,0x01,0x00]
10568
10569 v_subrev_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
10570 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x3c,0x01,0x00]
10571
10572 v_subrev_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
10573 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x01,0x01,0x00]
10574
10575 v_subrev_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
10576 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x0f,0x01,0x00]
10577
10578 v_subrev_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
10579 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x11,0x01,0x00]
10580
10581 v_subrev_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
10582 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x1f,0x01,0x00]
10583
10584 v_subrev_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
10585 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x21,0x01,0x00]
10586
10587 v_subrev_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
10588 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x2f,0x01,0x00]
10589
10590 v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
10591 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x10]
10592
10593 v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
10594 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x30]
10595
10596 v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
10597 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0xf0]
10598
10599 v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
10600 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0xf0]
10601
10602 v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
10603 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x01]
10604
10605 v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
10606 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x03]
10607
10608 v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
10609 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f]
10610
10611 v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
10612 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f]
10613
10614 v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
10615 // CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x08,0x00]
10616
10617 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10618 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
10619
10620 v_mul_lo_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10621 // CHECK: [0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06]
10622
10623 v_mul_lo_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10624 // CHECK: [0xf9,0x04,0x0a,0x52,0xff,0x06,0x06,0x06]
10625
10626 v_mul_lo_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10627 // CHECK: [0xf9,0xfe,0x0b,0x52,0x01,0x06,0x06,0x06]
10628
10629 v_mul_lo_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10630 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
10631
10632 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10633 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x00,0x06,0x06]
10634
10635 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10636 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x01,0x06,0x06]
10637
10638 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10639 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x02,0x06,0x06]
10640
10641 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10642 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x03,0x06,0x06]
10643
10644 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10645 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x04,0x06,0x06]
10646
10647 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10648 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x05,0x06,0x06]
10649
10650 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
10651 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x0e,0x06,0x06]
10652
10653 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
10654 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
10655
10656 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
10657 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
10658
10659 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
10660 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
10661
10662 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
10663 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x00,0x06]
10664
10665 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
10666 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x01,0x06]
10667
10668 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
10669 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x02,0x06]
10670
10671 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
10672 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x03,0x06]
10673
10674 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
10675 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x04,0x06]
10676
10677 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
10678 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x05,0x06]
10679
10680 v_mul_lo_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10681 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x0e,0x06]
10682
10683 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
10684 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
10685
10686 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
10687 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x00]
10688
10689 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
10690 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x01]
10691
10692 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
10693 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x02]
10694
10695 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
10696 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x03]
10697
10698 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
10699 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x04]
10700
10701 v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
10702 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x05]
10703
10704 v_mul_lo_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10705 // CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x0e]
10706
10707 v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10708 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x00]
10709
10710 v_mul_lo_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10711 // CHECK: [0xfa,0x04,0xfe,0x53,0x01,0xe4,0x00,0x00]
10712
10713 v_mul_lo_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10714 // CHECK: [0xfa,0x04,0x0a,0x52,0xff,0xe4,0x00,0x00]
10715
10716 v_mul_lo_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10717 // CHECK: [0xfa,0xfe,0x0b,0x52,0x01,0xe4,0x00,0x00]
10718
10719 v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
10720 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x00,0x00]
10721
10722 v_mul_lo_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
10723 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x40,0x01,0x00]
10724
10725 v_mul_lo_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
10726 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x41,0x01,0x00]
10727
10728 v_mul_lo_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
10729 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x42,0x01,0x00]
10730
10731 v_mul_lo_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
10732 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x43,0x01,0x00]
10733
10734 v_mul_lo_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
10735 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x30,0x01,0x00]
10736
10737 v_mul_lo_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
10738 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x34,0x01,0x00]
10739
10740 v_mul_lo_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
10741 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x38,0x01,0x00]
10742
10743 v_mul_lo_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
10744 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x3c,0x01,0x00]
10745
10746 v_mul_lo_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
10747 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x01,0x01,0x00]
10748
10749 v_mul_lo_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
10750 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x0f,0x01,0x00]
10751
10752 v_mul_lo_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
10753 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x11,0x01,0x00]
10754
10755 v_mul_lo_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
10756 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x1f,0x01,0x00]
10757
10758 v_mul_lo_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
10759 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x21,0x01,0x00]
10760
10761 v_mul_lo_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
10762 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x2f,0x01,0x00]
10763
10764 v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
10765 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x10]
10766
10767 v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
10768 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x30]
10769
10770 v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
10771 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0xf0]
10772
10773 v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
10774 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0xf0]
10775
10776 v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
10777 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x01]
10778
10779 v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
10780 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x03]
10781
10782 v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
10783 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f]
10784
10785 v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
10786 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f]
10787
10788 v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
10789 // CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x08,0x00]
10790
10791 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10792 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
10793
10794 v_lshlrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10795 // CHECK: [0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06]
10796
10797 v_lshlrev_b16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10798 // CHECK: [0xf9,0x04,0x0a,0x54,0xff,0x06,0x06,0x06]
10799
10800 v_lshlrev_b16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10801 // CHECK: [0xf9,0xfe,0x0b,0x54,0x01,0x06,0x06,0x06]
10802
10803 v_lshlrev_b16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10804 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
10805
10806 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10807 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x00,0x06,0x06]
10808
10809 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10810 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x01,0x06,0x06]
10811
10812 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10813 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x02,0x06,0x06]
10814
10815 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10816 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x03,0x06,0x06]
10817
10818 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10819 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x04,0x06,0x06]
10820
10821 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10822 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x05,0x06,0x06]
10823
10824 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
10825 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x0e,0x06,0x06]
10826
10827 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
10828 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
10829
10830 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
10831 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
10832
10833 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
10834 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
10835
10836 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
10837 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x00,0x06]
10838
10839 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
10840 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x01,0x06]
10841
10842 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
10843 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x02,0x06]
10844
10845 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
10846 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x03,0x06]
10847
10848 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
10849 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x04,0x06]
10850
10851 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
10852 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x05,0x06]
10853
10854 v_lshlrev_b16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10855 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x0e,0x06]
10856
10857 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
10858 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
10859
10860 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
10861 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x00]
10862
10863 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
10864 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x01]
10865
10866 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
10867 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x02]
10868
10869 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
10870 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x03]
10871
10872 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
10873 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x04]
10874
10875 v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
10876 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x05]
10877
10878 v_lshlrev_b16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10879 // CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x0e]
10880
10881 v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10882 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00]
10883
10884 v_lshlrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10885 // CHECK: [0xfa,0x04,0xfe,0x55,0x01,0xe4,0x00,0x00]
10886
10887 v_lshlrev_b16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10888 // CHECK: [0xfa,0x04,0x0a,0x54,0xff,0xe4,0x00,0x00]
10889
10890 v_lshlrev_b16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
10891 // CHECK: [0xfa,0xfe,0x0b,0x54,0x01,0xe4,0x00,0x00]
10892
10893 v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
10894 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x00,0x00]
10895
10896 v_lshlrev_b16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
10897 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x40,0x01,0x00]
10898
10899 v_lshlrev_b16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
10900 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x41,0x01,0x00]
10901
10902 v_lshlrev_b16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
10903 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x42,0x01,0x00]
10904
10905 v_lshlrev_b16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
10906 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x43,0x01,0x00]
10907
10908 v_lshlrev_b16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
10909 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x30,0x01,0x00]
10910
10911 v_lshlrev_b16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
10912 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x34,0x01,0x00]
10913
10914 v_lshlrev_b16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
10915 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x38,0x01,0x00]
10916
10917 v_lshlrev_b16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
10918 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x3c,0x01,0x00]
10919
10920 v_lshlrev_b16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
10921 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x01,0x01,0x00]
10922
10923 v_lshlrev_b16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
10924 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x0f,0x01,0x00]
10925
10926 v_lshlrev_b16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
10927 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x11,0x01,0x00]
10928
10929 v_lshlrev_b16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
10930 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x1f,0x01,0x00]
10931
10932 v_lshlrev_b16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
10933 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x21,0x01,0x00]
10934
10935 v_lshlrev_b16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
10936 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x2f,0x01,0x00]
10937
10938 v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
10939 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x10]
10940
10941 v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
10942 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x30]
10943
10944 v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
10945 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0xf0]
10946
10947 v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
10948 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0xf0]
10949
10950 v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
10951 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x01]
10952
10953 v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
10954 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x03]
10955
10956 v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
10957 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f]
10958
10959 v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
10960 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f]
10961
10962 v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
10963 // CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x08,0x00]
10964
10965 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10966 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
10967
10968 v_lshrrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10969 // CHECK: [0xf9,0x04,0xfe,0x57,0x01,0x06,0x06,0x06]
10970
10971 v_lshrrev_b16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10972 // CHECK: [0xf9,0x04,0x0a,0x56,0xff,0x06,0x06,0x06]
10973
10974 v_lshrrev_b16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10975 // CHECK: [0xf9,0xfe,0x0b,0x56,0x01,0x06,0x06,0x06]
10976
10977 v_lshrrev_b16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10978 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
10979
10980 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10981 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x00,0x06,0x06]
10982
10983 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10984 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x01,0x06,0x06]
10985
10986 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10987 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x02,0x06,0x06]
10988
10989 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10990 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x03,0x06,0x06]
10991
10992 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10993 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x04,0x06,0x06]
10994
10995 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
10996 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x05,0x06,0x06]
10997
10998 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
10999 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x0e,0x06,0x06]
11000
11001 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
11002 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x16,0x06,0x06]
11003
11004 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
11005 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x16,0x06,0x06]
11006
11007 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
11008 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
11009
11010 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
11011 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x00,0x06]
11012
11013 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
11014 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x01,0x06]
11015
11016 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
11017 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x02,0x06]
11018
11019 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
11020 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x03,0x06]
11021
11022 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
11023 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x04,0x06]
11024
11025 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
11026 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x05,0x06]
11027
11028 v_lshrrev_b16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11029 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x0e,0x06]
11030
11031 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
11032 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
11033
11034 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
11035 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x00]
11036
11037 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
11038 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x01]
11039
11040 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
11041 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x02]
11042
11043 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
11044 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x03]
11045
11046 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
11047 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x04]
11048
11049 v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
11050 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x05]
11051
11052 v_lshrrev_b16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11053 // CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x0e]
11054
11055 v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11056 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x00]
11057
11058 v_lshrrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11059 // CHECK: [0xfa,0x04,0xfe,0x57,0x01,0xe4,0x00,0x00]
11060
11061 v_lshrrev_b16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11062 // CHECK: [0xfa,0x04,0x0a,0x56,0xff,0xe4,0x00,0x00]
11063
11064 v_lshrrev_b16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11065 // CHECK: [0xfa,0xfe,0x0b,0x56,0x01,0xe4,0x00,0x00]
11066
11067 v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
11068 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0x00]
11069
11070 v_lshrrev_b16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
11071 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0x00]
11072
11073 v_lshrrev_b16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
11074 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0x00]
11075
11076 v_lshrrev_b16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
11077 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x42,0x01,0x00]
11078
11079 v_lshrrev_b16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
11080 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x43,0x01,0x00]
11081
11082 v_lshrrev_b16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
11083 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x30,0x01,0x00]
11084
11085 v_lshrrev_b16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
11086 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x34,0x01,0x00]
11087
11088 v_lshrrev_b16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
11089 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x38,0x01,0x00]
11090
11091 v_lshrrev_b16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
11092 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x3c,0x01,0x00]
11093
11094 v_lshrrev_b16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
11095 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0x00]
11096
11097 v_lshrrev_b16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
11098 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0x00]
11099
11100 v_lshrrev_b16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
11101 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0x00]
11102
11103 v_lshrrev_b16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
11104 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0x00]
11105
11106 v_lshrrev_b16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
11107 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0x00]
11108
11109 v_lshrrev_b16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
11110 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0x00]
11111
11112 v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
11113 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x10]
11114
11115 v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
11116 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x30]
11117
11118 v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
11119 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xf0]
11120
11121 v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
11122 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xf0]
11123
11124 v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
11125 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x01]
11126
11127 v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
11128 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x03]
11129
11130 v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
11131 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f]
11132
11133 v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
11134 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f]
11135
11136 v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
11137 // CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x08,0x00]
11138
11139 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11140 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
11141
11142 v_ashrrev_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11143 // CHECK: [0xf9,0x04,0xfe,0x59,0x01,0x06,0x06,0x06]
11144
11145 v_ashrrev_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11146 // CHECK: [0xf9,0x04,0x0a,0x58,0xff,0x06,0x06,0x06]
11147
11148 v_ashrrev_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11149 // CHECK: [0xf9,0xfe,0x0b,0x58,0x01,0x06,0x06,0x06]
11150
11151 v_ashrrev_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11152 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
11153
11154 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11155 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x00,0x06,0x06]
11156
11157 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11158 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x01,0x06,0x06]
11159
11160 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11161 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x02,0x06,0x06]
11162
11163 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11164 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x03,0x06,0x06]
11165
11166 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11167 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x04,0x06,0x06]
11168
11169 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11170 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x05,0x06,0x06]
11171
11172 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
11173 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x0e,0x06,0x06]
11174
11175 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
11176 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x16,0x06,0x06]
11177
11178 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
11179 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x16,0x06,0x06]
11180
11181 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
11182 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
11183
11184 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
11185 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x00,0x06]
11186
11187 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
11188 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x01,0x06]
11189
11190 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
11191 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x02,0x06]
11192
11193 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
11194 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x03,0x06]
11195
11196 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
11197 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x04,0x06]
11198
11199 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
11200 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x05,0x06]
11201
11202 v_ashrrev_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11203 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x0e,0x06]
11204
11205 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
11206 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
11207
11208 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
11209 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x00]
11210
11211 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
11212 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x01]
11213
11214 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
11215 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x02]
11216
11217 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
11218 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x03]
11219
11220 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
11221 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x04]
11222
11223 v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
11224 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x05]
11225
11226 v_ashrrev_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11227 // CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x0e]
11228
11229 v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11230 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x00]
11231
11232 v_ashrrev_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11233 // CHECK: [0xfa,0x04,0xfe,0x59,0x01,0xe4,0x00,0x00]
11234
11235 v_ashrrev_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11236 // CHECK: [0xfa,0x04,0x0a,0x58,0xff,0xe4,0x00,0x00]
11237
11238 v_ashrrev_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11239 // CHECK: [0xfa,0xfe,0x0b,0x58,0x01,0xe4,0x00,0x00]
11240
11241 v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
11242 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x1b,0x00,0x00]
11243
11244 v_ashrrev_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
11245 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x40,0x01,0x00]
11246
11247 v_ashrrev_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
11248 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x41,0x01,0x00]
11249
11250 v_ashrrev_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
11251 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x42,0x01,0x00]
11252
11253 v_ashrrev_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
11254 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x43,0x01,0x00]
11255
11256 v_ashrrev_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
11257 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x30,0x01,0x00]
11258
11259 v_ashrrev_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
11260 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x34,0x01,0x00]
11261
11262 v_ashrrev_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
11263 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x38,0x01,0x00]
11264
11265 v_ashrrev_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
11266 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x3c,0x01,0x00]
11267
11268 v_ashrrev_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
11269 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x01,0x01,0x00]
11270
11271 v_ashrrev_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
11272 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x0f,0x01,0x00]
11273
11274 v_ashrrev_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
11275 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x11,0x01,0x00]
11276
11277 v_ashrrev_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
11278 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x1f,0x01,0x00]
11279
11280 v_ashrrev_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
11281 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x21,0x01,0x00]
11282
11283 v_ashrrev_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
11284 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x2f,0x01,0x00]
11285
11286 v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
11287 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x10]
11288
11289 v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
11290 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x30]
11291
11292 v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
11293 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0xf0]
11294
11295 v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
11296 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0xf0]
11297
11298 v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
11299 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x01]
11300
11301 v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
11302 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x03]
11303
11304 v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
11305 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f]
11306
11307 v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
11308 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f]
11309
11310 v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
11311 // CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x08,0x00]
11312
11313 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11314 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
11315
11316 v_max_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11317 // CHECK: [0xf9,0x04,0xfe,0x5b,0x01,0x06,0x06,0x06]
11318
11319 v_max_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11320 // CHECK: [0xf9,0x04,0x0a,0x5a,0xff,0x06,0x06,0x06]
11321
11322 v_max_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11323 // CHECK: [0xf9,0xfe,0x0b,0x5a,0x01,0x06,0x06,0x06]
11324
11325 v_max_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11326 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x26,0x06,0x06]
11327
11328 v_max_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11329 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
11330
11331 v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11332 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x00,0x06,0x06]
11333
11334 v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11335 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x01,0x06,0x06]
11336
11337 v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11338 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x02,0x06,0x06]
11339
11340 v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11341 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x03,0x06,0x06]
11342
11343 v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11344 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x04,0x06,0x06]
11345
11346 v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11347 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x05,0x06,0x06]
11348
11349 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
11350 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x0e,0x06,0x06]
11351
11352 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
11353 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x16,0x06,0x06]
11354
11355 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
11356 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x16,0x06,0x06]
11357
11358 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
11359 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
11360
11361 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
11362 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x00,0x06]
11363
11364 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
11365 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x01,0x06]
11366
11367 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
11368 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x02,0x06]
11369
11370 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
11371 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x03,0x06]
11372
11373 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
11374 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x04,0x06]
11375
11376 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
11377 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x05,0x06]
11378
11379 v_max_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11380 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x16,0x06]
11381
11382 v_max_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11383 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x26,0x06]
11384
11385 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
11386 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
11387
11388 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
11389 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x00]
11390
11391 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
11392 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x01]
11393
11394 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
11395 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x02]
11396
11397 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
11398 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x03]
11399
11400 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
11401 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x04]
11402
11403 v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
11404 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x05]
11405
11406 v_max_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11407 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x16]
11408
11409 v_max_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11410 // CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x26]
11411
11412 v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11413 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x00]
11414
11415 v_max_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11416 // CHECK: [0xfa,0x04,0xfe,0x5b,0x01,0xe4,0x00,0x00]
11417
11418 v_max_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11419 // CHECK: [0xfa,0x04,0x0a,0x5a,0xff,0xe4,0x00,0x00]
11420
11421 v_max_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11422 // CHECK: [0xfa,0xfe,0x0b,0x5a,0x01,0xe4,0x00,0x00]
11423
11424 v_max_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
11425 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x1b,0x00,0x00]
11426
11427 v_max_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
11428 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x40,0x01,0x00]
11429
11430 v_max_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
11431 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x41,0x01,0x00]
11432
11433 v_max_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
11434 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x42,0x01,0x00]
11435
11436 v_max_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
11437 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x43,0x01,0x00]
11438
11439 v_max_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
11440 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x30,0x01,0x00]
11441
11442 v_max_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
11443 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x34,0x01,0x00]
11444
11445 v_max_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
11446 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x38,0x01,0x00]
11447
11448 v_max_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
11449 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x3c,0x01,0x00]
11450
11451 v_max_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
11452 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x01,0x01,0x00]
11453
11454 v_max_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
11455 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x0f,0x01,0x00]
11456
11457 v_max_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
11458 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x11,0x01,0x00]
11459
11460 v_max_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
11461 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x1f,0x01,0x00]
11462
11463 v_max_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
11464 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x21,0x01,0x00]
11465
11466 v_max_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
11467 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x2f,0x01,0x00]
11468
11469 v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
11470 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x10]
11471
11472 v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
11473 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x30]
11474
11475 v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
11476 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0xf0]
11477
11478 v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
11479 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0xf0]
11480
11481 v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
11482 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x01]
11483
11484 v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
11485 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x03]
11486
11487 v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
11488 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f]
11489
11490 v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
11491 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f]
11492
11493 v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
11494 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x08,0x00]
11495
11496 v_max_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11497 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x10,0x00]
11498
11499 v_max_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11500 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x20,0x00]
11501
11502 v_max_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11503 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x40,0x00]
11504
11505 v_max_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11506 // CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x80,0x00]
11507
11508 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11509 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
11510
11511 v_min_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11512 // CHECK: [0xf9,0x04,0xfe,0x5d,0x01,0x06,0x06,0x06]
11513
11514 v_min_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11515 // CHECK: [0xf9,0x04,0x0a,0x5c,0xff,0x06,0x06,0x06]
11516
11517 v_min_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11518 // CHECK: [0xf9,0xfe,0x0b,0x5c,0x01,0x06,0x06,0x06]
11519
11520 v_min_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11521 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x26,0x06,0x06]
11522
11523 v_min_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11524 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
11525
11526 v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11527 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x00,0x06,0x06]
11528
11529 v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11530 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x01,0x06,0x06]
11531
11532 v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11533 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x02,0x06,0x06]
11534
11535 v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11536 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x03,0x06,0x06]
11537
11538 v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11539 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x04,0x06,0x06]
11540
11541 v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11542 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x05,0x06,0x06]
11543
11544 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
11545 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x0e,0x06,0x06]
11546
11547 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
11548 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x16,0x06,0x06]
11549
11550 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
11551 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x16,0x06,0x06]
11552
11553 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
11554 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
11555
11556 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
11557 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x00,0x06]
11558
11559 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
11560 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x01,0x06]
11561
11562 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
11563 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x02,0x06]
11564
11565 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
11566 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x03,0x06]
11567
11568 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
11569 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x04,0x06]
11570
11571 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
11572 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x05,0x06]
11573
11574 v_min_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11575 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x16,0x06]
11576
11577 v_min_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11578 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x26,0x06]
11579
11580 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
11581 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
11582
11583 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
11584 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x00]
11585
11586 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
11587 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x01]
11588
11589 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
11590 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x02]
11591
11592 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
11593 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x03]
11594
11595 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
11596 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x04]
11597
11598 v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
11599 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x05]
11600
11601 v_min_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11602 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x16]
11603
11604 v_min_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11605 // CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x26]
11606
11607 v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11608 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x00]
11609
11610 v_min_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11611 // CHECK: [0xfa,0x04,0xfe,0x5d,0x01,0xe4,0x00,0x00]
11612
11613 v_min_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11614 // CHECK: [0xfa,0x04,0x0a,0x5c,0xff,0xe4,0x00,0x00]
11615
11616 v_min_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11617 // CHECK: [0xfa,0xfe,0x0b,0x5c,0x01,0xe4,0x00,0x00]
11618
11619 v_min_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
11620 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x1b,0x00,0x00]
11621
11622 v_min_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
11623 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x40,0x01,0x00]
11624
11625 v_min_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
11626 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x41,0x01,0x00]
11627
11628 v_min_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
11629 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x42,0x01,0x00]
11630
11631 v_min_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
11632 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x43,0x01,0x00]
11633
11634 v_min_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
11635 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x30,0x01,0x00]
11636
11637 v_min_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
11638 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x34,0x01,0x00]
11639
11640 v_min_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
11641 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x38,0x01,0x00]
11642
11643 v_min_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
11644 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x3c,0x01,0x00]
11645
11646 v_min_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
11647 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x01,0x01,0x00]
11648
11649 v_min_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
11650 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x0f,0x01,0x00]
11651
11652 v_min_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
11653 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x11,0x01,0x00]
11654
11655 v_min_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
11656 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x1f,0x01,0x00]
11657
11658 v_min_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
11659 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x21,0x01,0x00]
11660
11661 v_min_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
11662 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x2f,0x01,0x00]
11663
11664 v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
11665 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x10]
11666
11667 v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
11668 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x30]
11669
11670 v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
11671 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0xf0]
11672
11673 v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
11674 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0xf0]
11675
11676 v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
11677 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x01]
11678
11679 v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
11680 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x03]
11681
11682 v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
11683 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f]
11684
11685 v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
11686 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f]
11687
11688 v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
11689 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x08,0x00]
11690
11691 v_min_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11692 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x10,0x00]
11693
11694 v_min_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11695 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x20,0x00]
11696
11697 v_min_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11698 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x40,0x00]
11699
11700 v_min_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11701 // CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x80,0x00]
11702
11703 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11704 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
11705
11706 v_max_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11707 // CHECK: [0xf9,0x04,0xfe,0x5f,0x01,0x06,0x06,0x06]
11708
11709 v_max_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11710 // CHECK: [0xf9,0x04,0x0a,0x5e,0xff,0x06,0x06,0x06]
11711
11712 v_max_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11713 // CHECK: [0xf9,0xfe,0x0b,0x5e,0x01,0x06,0x06,0x06]
11714
11715 v_max_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11716 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
11717
11718 v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11719 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x00,0x06,0x06]
11720
11721 v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11722 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x01,0x06,0x06]
11723
11724 v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11725 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x02,0x06,0x06]
11726
11727 v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11728 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x03,0x06,0x06]
11729
11730 v_max_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11731 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x04,0x06,0x06]
11732
11733 v_max_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11734 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x05,0x06,0x06]
11735
11736 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
11737 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x0e,0x06,0x06]
11738
11739 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
11740 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x16,0x06,0x06]
11741
11742 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
11743 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x16,0x06,0x06]
11744
11745 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
11746 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
11747
11748 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
11749 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x00,0x06]
11750
11751 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
11752 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x01,0x06]
11753
11754 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
11755 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x02,0x06]
11756
11757 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
11758 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x03,0x06]
11759
11760 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
11761 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x04,0x06]
11762
11763 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
11764 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x05,0x06]
11765
11766 v_max_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11767 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x0e,0x06]
11768
11769 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
11770 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
11771
11772 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
11773 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x00]
11774
11775 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
11776 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x01]
11777
11778 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
11779 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x02]
11780
11781 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
11782 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x03]
11783
11784 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
11785 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x04]
11786
11787 v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
11788 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x05]
11789
11790 v_max_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11791 // CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x0e]
11792
11793 v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11794 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x00]
11795
11796 v_max_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11797 // CHECK: [0xfa,0x04,0xfe,0x5f,0x01,0xe4,0x00,0x00]
11798
11799 v_max_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11800 // CHECK: [0xfa,0x04,0x0a,0x5e,0xff,0xe4,0x00,0x00]
11801
11802 v_max_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11803 // CHECK: [0xfa,0xfe,0x0b,0x5e,0x01,0xe4,0x00,0x00]
11804
11805 v_max_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
11806 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0x00]
11807
11808 v_max_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
11809 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0x00]
11810
11811 v_max_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
11812 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0x00]
11813
11814 v_max_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
11815 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x42,0x01,0x00]
11816
11817 v_max_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
11818 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x43,0x01,0x00]
11819
11820 v_max_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
11821 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x30,0x01,0x00]
11822
11823 v_max_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
11824 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x34,0x01,0x00]
11825
11826 v_max_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
11827 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x38,0x01,0x00]
11828
11829 v_max_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
11830 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x3c,0x01,0x00]
11831
11832 v_max_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
11833 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0x00]
11834
11835 v_max_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
11836 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0x00]
11837
11838 v_max_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
11839 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0x00]
11840
11841 v_max_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
11842 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0x00]
11843
11844 v_max_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
11845 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0x00]
11846
11847 v_max_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
11848 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0x00]
11849
11850 v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
11851 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x10]
11852
11853 v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
11854 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x30]
11855
11856 v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
11857 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xf0]
11858
11859 v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
11860 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xf0]
11861
11862 v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
11863 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x01]
11864
11865 v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
11866 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x03]
11867
11868 v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
11869 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f]
11870
11871 v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
11872 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f]
11873
11874 v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
11875 // CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x08,0x00]
11876
11877 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11878 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
11879
11880 v_max_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11881 // CHECK: [0xf9,0x04,0xfe,0x61,0x01,0x06,0x06,0x06]
11882
11883 v_max_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11884 // CHECK: [0xf9,0x04,0x0a,0x60,0xff,0x06,0x06,0x06]
11885
11886 v_max_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11887 // CHECK: [0xf9,0xfe,0x0b,0x60,0x01,0x06,0x06,0x06]
11888
11889 v_max_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11890 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
11891
11892 v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11893 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x00,0x06,0x06]
11894
11895 v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11896 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x01,0x06,0x06]
11897
11898 v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11899 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x02,0x06,0x06]
11900
11901 v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11902 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x03,0x06,0x06]
11903
11904 v_max_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11905 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x04,0x06,0x06]
11906
11907 v_max_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11908 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x05,0x06,0x06]
11909
11910 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
11911 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x0e,0x06,0x06]
11912
11913 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
11914 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x16,0x06,0x06]
11915
11916 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
11917 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x16,0x06,0x06]
11918
11919 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
11920 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
11921
11922 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
11923 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x00,0x06]
11924
11925 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
11926 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x01,0x06]
11927
11928 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
11929 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x02,0x06]
11930
11931 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
11932 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x03,0x06]
11933
11934 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
11935 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x04,0x06]
11936
11937 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
11938 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x05,0x06]
11939
11940 v_max_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11941 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x0e,0x06]
11942
11943 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
11944 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
11945
11946 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
11947 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x00]
11948
11949 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
11950 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x01]
11951
11952 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
11953 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x02]
11954
11955 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
11956 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x03]
11957
11958 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
11959 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x04]
11960
11961 v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
11962 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x05]
11963
11964 v_max_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
11965 // CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x0e]
11966
11967 v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11968 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x00]
11969
11970 v_max_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11971 // CHECK: [0xfa,0x04,0xfe,0x61,0x01,0xe4,0x00,0x00]
11972
11973 v_max_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11974 // CHECK: [0xfa,0x04,0x0a,0x60,0xff,0xe4,0x00,0x00]
11975
11976 v_max_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
11977 // CHECK: [0xfa,0xfe,0x0b,0x60,0x01,0xe4,0x00,0x00]
11978
11979 v_max_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
11980 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0x00]
11981
11982 v_max_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
11983 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0x00]
11984
11985 v_max_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
11986 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0x00]
11987
11988 v_max_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
11989 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x42,0x01,0x00]
11990
11991 v_max_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
11992 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x43,0x01,0x00]
11993
11994 v_max_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
11995 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x30,0x01,0x00]
11996
11997 v_max_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
11998 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x34,0x01,0x00]
11999
12000 v_max_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
12001 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x38,0x01,0x00]
12002
12003 v_max_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
12004 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x3c,0x01,0x00]
12005
12006 v_max_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
12007 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0x00]
12008
12009 v_max_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
12010 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0x00]
12011
12012 v_max_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
12013 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0x00]
12014
12015 v_max_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
12016 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0x00]
12017
12018 v_max_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
12019 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0x00]
12020
12021 v_max_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
12022 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0x00]
12023
12024 v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
12025 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x10]
12026
12027 v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
12028 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x30]
12029
12030 v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
12031 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xf0]
12032
12033 v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
12034 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xf0]
12035
12036 v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
12037 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x01]
12038
12039 v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
12040 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x03]
12041
12042 v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
12043 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f]
12044
12045 v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
12046 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f]
12047
12048 v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
12049 // CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x08,0x00]
12050
12051 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12052 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
12053
12054 v_min_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12055 // CHECK: [0xf9,0x04,0xfe,0x63,0x01,0x06,0x06,0x06]
12056
12057 v_min_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12058 // CHECK: [0xf9,0x04,0x0a,0x62,0xff,0x06,0x06,0x06]
12059
12060 v_min_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12061 // CHECK: [0xf9,0xfe,0x0b,0x62,0x01,0x06,0x06,0x06]
12062
12063 v_min_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12064 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
12065
12066 v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12067 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x00,0x06,0x06]
12068
12069 v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12070 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x01,0x06,0x06]
12071
12072 v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12073 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x02,0x06,0x06]
12074
12075 v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12076 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x03,0x06,0x06]
12077
12078 v_min_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12079 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x04,0x06,0x06]
12080
12081 v_min_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12082 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x05,0x06,0x06]
12083
12084 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
12085 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x0e,0x06,0x06]
12086
12087 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
12088 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x16,0x06,0x06]
12089
12090 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
12091 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x16,0x06,0x06]
12092
12093 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
12094 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
12095
12096 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
12097 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x00,0x06]
12098
12099 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
12100 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x01,0x06]
12101
12102 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
12103 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x02,0x06]
12104
12105 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
12106 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x03,0x06]
12107
12108 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
12109 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x04,0x06]
12110
12111 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
12112 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x05,0x06]
12113
12114 v_min_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12115 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x0e,0x06]
12116
12117 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
12118 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
12119
12120 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
12121 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x00]
12122
12123 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
12124 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x01]
12125
12126 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
12127 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x02]
12128
12129 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
12130 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x03]
12131
12132 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
12133 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x04]
12134
12135 v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
12136 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x05]
12137
12138 v_min_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12139 // CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x0e]
12140
12141 v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12142 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x00]
12143
12144 v_min_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12145 // CHECK: [0xfa,0x04,0xfe,0x63,0x01,0xe4,0x00,0x00]
12146
12147 v_min_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12148 // CHECK: [0xfa,0x04,0x0a,0x62,0xff,0xe4,0x00,0x00]
12149
12150 v_min_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12151 // CHECK: [0xfa,0xfe,0x0b,0x62,0x01,0xe4,0x00,0x00]
12152
12153 v_min_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
12154 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0x00]
12155
12156 v_min_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
12157 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0x00]
12158
12159 v_min_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
12160 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0x00]
12161
12162 v_min_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
12163 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x42,0x01,0x00]
12164
12165 v_min_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
12166 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x43,0x01,0x00]
12167
12168 v_min_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
12169 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x30,0x01,0x00]
12170
12171 v_min_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
12172 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x34,0x01,0x00]
12173
12174 v_min_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
12175 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x38,0x01,0x00]
12176
12177 v_min_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
12178 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x3c,0x01,0x00]
12179
12180 v_min_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
12181 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0x00]
12182
12183 v_min_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
12184 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0x00]
12185
12186 v_min_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
12187 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0x00]
12188
12189 v_min_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
12190 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0x00]
12191
12192 v_min_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
12193 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0x00]
12194
12195 v_min_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
12196 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0x00]
12197
12198 v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
12199 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x10]
12200
12201 v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
12202 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x30]
12203
12204 v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
12205 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xf0]
12206
12207 v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
12208 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xf0]
12209
12210 v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
12211 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x01]
12212
12213 v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
12214 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x03]
12215
12216 v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
12217 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f]
12218
12219 v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
12220 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f]
12221
12222 v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
12223 // CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x08,0x00]
12224
12225 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12226 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
12227
12228 v_min_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12229 // CHECK: [0xf9,0x04,0xfe,0x65,0x01,0x06,0x06,0x06]
12230
12231 v_min_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12232 // CHECK: [0xf9,0x04,0x0a,0x64,0xff,0x06,0x06,0x06]
12233
12234 v_min_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12235 // CHECK: [0xf9,0xfe,0x0b,0x64,0x01,0x06,0x06,0x06]
12236
12237 v_min_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12238 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
12239
12240 v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12241 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x00,0x06,0x06]
12242
12243 v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12244 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x01,0x06,0x06]
12245
12246 v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12247 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x02,0x06,0x06]
12248
12249 v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12250 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x03,0x06,0x06]
12251
12252 v_min_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12253 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x04,0x06,0x06]
12254
12255 v_min_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12256 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x05,0x06,0x06]
12257
12258 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
12259 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x0e,0x06,0x06]
12260
12261 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
12262 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
12263
12264 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
12265 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
12266
12267 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
12268 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
12269
12270 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
12271 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x00,0x06]
12272
12273 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
12274 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x01,0x06]
12275
12276 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
12277 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x02,0x06]
12278
12279 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
12280 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x03,0x06]
12281
12282 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
12283 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x04,0x06]
12284
12285 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
12286 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x05,0x06]
12287
12288 v_min_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12289 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x0e,0x06]
12290
12291 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
12292 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
12293
12294 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
12295 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x00]
12296
12297 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
12298 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x01]
12299
12300 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
12301 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x02]
12302
12303 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
12304 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x03]
12305
12306 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
12307 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x04]
12308
12309 v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
12310 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x05]
12311
12312 v_min_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12313 // CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x0e]
12314
12315 v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12316 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x00]
12317
12318 v_min_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12319 // CHECK: [0xfa,0x04,0xfe,0x65,0x01,0xe4,0x00,0x00]
12320
12321 v_min_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12322 // CHECK: [0xfa,0x04,0x0a,0x64,0xff,0xe4,0x00,0x00]
12323
12324 v_min_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12325 // CHECK: [0xfa,0xfe,0x0b,0x64,0x01,0xe4,0x00,0x00]
12326
12327 v_min_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
12328 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0x00]
12329
12330 v_min_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
12331 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0x00]
12332
12333 v_min_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
12334 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0x00]
12335
12336 v_min_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
12337 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x42,0x01,0x00]
12338
12339 v_min_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
12340 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x43,0x01,0x00]
12341
12342 v_min_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
12343 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x30,0x01,0x00]
12344
12345 v_min_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
12346 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x34,0x01,0x00]
12347
12348 v_min_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
12349 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x38,0x01,0x00]
12350
12351 v_min_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
12352 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x3c,0x01,0x00]
12353
12354 v_min_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
12355 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0x00]
12356
12357 v_min_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
12358 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0x00]
12359
12360 v_min_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
12361 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0x00]
12362
12363 v_min_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
12364 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0x00]
12365
12366 v_min_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
12367 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0x00]
12368
12369 v_min_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
12370 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0x00]
12371
12372 v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
12373 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x10]
12374
12375 v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
12376 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x30]
12377
12378 v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
12379 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xf0]
12380
12381 v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
12382 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xf0]
12383
12384 v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
12385 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x01]
12386
12387 v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
12388 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03]
12389
12390 v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
12391 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
12392
12393 v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
12394 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
12395
12396 v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
12397 // CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
12398
12399 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12400 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
12401
12402 v_ldexp_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12403 // CHECK: [0xf9,0x04,0xfe,0x67,0x01,0x06,0x06,0x06]
12404
12405 v_ldexp_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12406 // CHECK: [0xf9,0x04,0x0a,0x66,0xff,0x06,0x06,0x06]
12407
12408 v_ldexp_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12409 // CHECK: [0xf9,0xfe,0x0b,0x66,0x01,0x06,0x06,0x06]
12410
12411 v_ldexp_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12412 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x26,0x06,0x06]
12413
12414 v_ldexp_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12415 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
12416
12417 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12418 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x00,0x06,0x06]
12419
12420 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12421 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x01,0x06,0x06]
12422
12423 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12424 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x02,0x06,0x06]
12425
12426 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12427 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x03,0x06,0x06]
12428
12429 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12430 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x04,0x06,0x06]
12431
12432 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12433 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x05,0x06,0x06]
12434
12435 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
12436 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x0e,0x06,0x06]
12437
12438 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
12439 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
12440
12441 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
12442 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
12443
12444 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
12445 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
12446
12447 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
12448 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x00,0x06]
12449
12450 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
12451 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x01,0x06]
12452
12453 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
12454 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x02,0x06]
12455
12456 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
12457 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x03,0x06]
12458
12459 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
12460 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x04,0x06]
12461
12462 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
12463 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x05,0x06]
12464
12465 v_ldexp_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12466 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x16,0x06]
12467
12468 v_ldexp_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12469 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x26,0x06]
12470
12471 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
12472 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
12473
12474 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
12475 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x00]
12476
12477 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
12478 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x01]
12479
12480 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
12481 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x02]
12482
12483 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
12484 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x03]
12485
12486 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
12487 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x04]
12488
12489 v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
12490 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x05]
12491
12492 v_ldexp_f16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
12493 // CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x0e]
12494
12495 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12496 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x00]
12497
12498 v_ldexp_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12499 // CHECK: [0xfa,0x04,0xfe,0x67,0x01,0xe4,0x00,0x00]
12500
12501 v_ldexp_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12502 // CHECK: [0xfa,0x04,0x0a,0x66,0xff,0xe4,0x00,0x00]
12503
12504 v_ldexp_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12505 // CHECK: [0xfa,0xfe,0x0b,0x66,0x01,0xe4,0x00,0x00]
12506
12507 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
12508 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0x00]
12509
12510 v_ldexp_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
12511 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0x00]
12512
12513 v_ldexp_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
12514 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0x00]
12515
12516 v_ldexp_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
12517 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x42,0x01,0x00]
12518
12519 v_ldexp_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
12520 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x43,0x01,0x00]
12521
12522 v_ldexp_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
12523 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x30,0x01,0x00]
12524
12525 v_ldexp_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
12526 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x34,0x01,0x00]
12527
12528 v_ldexp_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
12529 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x38,0x01,0x00]
12530
12531 v_ldexp_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
12532 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x3c,0x01,0x00]
12533
12534 v_ldexp_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
12535 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0x00]
12536
12537 v_ldexp_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
12538 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0x00]
12539
12540 v_ldexp_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
12541 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0x00]
12542
12543 v_ldexp_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
12544 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0x00]
12545
12546 v_ldexp_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
12547 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0x00]
12548
12549 v_ldexp_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
12550 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0x00]
12551
12552 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
12553 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x10]
12554
12555 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
12556 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x30]
12557
12558 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
12559 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xf0]
12560
12561 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
12562 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xf0]
12563
12564 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
12565 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x01]
12566
12567 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
12568 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03]
12569
12570 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
12571 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
12572
12573 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
12574 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
12575
12576 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
12577 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
12578
12579 v_ldexp_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12580 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00]
12581
12582 v_ldexp_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
12583 // CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x20,0x00]