llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx90a.s

   1 // RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck --check-prefix=ASM %s
   2 // RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx90a -filetype=obj < %s > %t
   3 // RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s
   4
   5 // When going from asm -> asm, the expressions should remain the same (i.e., symbolic).
   6 // When going from asm -> obj, the expressions should get resolved (through fixups),
   7
   8 // OBJDUMP: Contents of section .rodata
   9 // expr_defined_later
  10 // OBJDUMP-NEXT: 0000 00000000 00000000 00000000 00000000
  11 // OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000
  12 // OBJDUMP-NEXT: 0020 00000000 00000000 00000000 00000100
  13 // OBJDUMP-NEXT: 0030 4000ac04 81000000 00000000 00000000
  14 // expr_defined
  15 // OBJDUMP-NEXT: 0040 00000000 00000000 00000000 00000000
  16 // OBJDUMP-NEXT: 0050 00000000 00000000 00000000 00000000
  17 // OBJDUMP-NEXT: 0060 00000000 00000000 00000000 00000100
  18 // OBJDUMP-NEXT: 0070 4000ac04 81000000 00000000 00000000
  19
  20 .text
  21 // ASM: .text
  22
  23 .amdhsa_code_object_version 4
  24 // ASM: .amdhsa_code_object_version 4
  25
  26 .p2align 8
  27 .type expr_defined_later,@function
  28 expr_defined_later:
  29   s_endpgm
  30
  31 .p2align 8
  32 .type expr_defined,@function
  33 expr_defined:
  34   s_endpgm
  35
  36 .rodata
  37 // ASM: .rodata
  38
  39 .p2align 6
  40 .amdhsa_kernel expr_defined_later
  41   .amdhsa_system_sgpr_private_segment_wavefront_offset defined_boolean
  42   .amdhsa_dx10_clamp defined_boolean
  43   .amdhsa_ieee_mode defined_boolean
  44   .amdhsa_fp16_overflow defined_boolean
  45   .amdhsa_tg_split defined_boolean
  46   .amdhsa_next_free_vgpr defined_boolean+1
  47   .amdhsa_next_free_sgpr defined_boolean+2
  48   .amdhsa_accum_offset 4
  49   .amdhsa_reserve_vcc defined_boolean
  50   .amdhsa_reserve_flat_scratch defined_boolean
  51 .end_amdhsa_kernel
  52
  53 .set defined_boolean, 1
  54
  55 .p2align 6
  56 .amdhsa_kernel expr_defined
  57   .amdhsa_system_sgpr_private_segment_wavefront_offset defined_boolean
  58   .amdhsa_dx10_clamp defined_boolean
  59   .amdhsa_ieee_mode defined_boolean
  60   .amdhsa_fp16_overflow defined_boolean
  61   .amdhsa_tg_split defined_boolean
  62   .amdhsa_next_free_vgpr defined_boolean+1
  63   .amdhsa_next_free_sgpr defined_boolean+2
  64   .amdhsa_accum_offset 4
  65   .amdhsa_reserve_vcc defined_boolean
  66   .amdhsa_reserve_flat_scratch defined_boolean
  67 .end_amdhsa_kernel
  68
  69 // ASM: .amdhsa_kernel expr_defined_later
  70 // ASM-NEXT: .amdhsa_group_segment_fixed_size 0
  71 // ASM-NEXT: .amdhsa_private_segment_fixed_size 0
  72 // ASM-NEXT: .amdhsa_kernarg_size 0
  73 // ASM-NEXT: .amdhsa_user_sgpr_count 0
  74 // ASM-NEXT: .amdhsa_user_sgpr_private_segment_buffer 0
  75 // ASM-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
  76 // ASM-NEXT: .amdhsa_user_sgpr_queue_ptr 0
  77 // ASM-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
  78 // ASM-NEXT: .amdhsa_user_sgpr_dispatch_id 0
  79 // ASM-NEXT: .amdhsa_user_sgpr_flat_scratch_init 0
  80 // ASM-NEXT: .amdhsa_user_sgpr_kernarg_preload_length 0
  81 // ASM-NEXT: .amdhsa_user_sgpr_kernarg_preload_offset 0
  82 // ASM-NEXT: .amdhsa_user_sgpr_private_segment_size 0
  83 // ASM-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset ((128|defined_boolean)&(~62))&1
  84 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
  85 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_y (((128|defined_boolean)&(~62))&256)>>8
  86 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_z (((128|defined_boolean)&(~62))&512)>>9
  87 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_info (((128|defined_boolean)&(~62))&1024)>>10
  88 // ASM-NEXT: .amdhsa_system_vgpr_workitem_id (((128|defined_boolean)&(~62))&6144)>>11
  89 // ASM-NEXT: .amdhsa_next_free_vgpr defined_boolean+1
  90 // ASM-NEXT: .amdhsa_next_free_sgpr defined_boolean+2
  91 // ASM-NEXT: .amdhsa_accum_offset 4
  92 // ASM-NEXT: .amdhsa_reserve_vcc defined_boolean
  93 // ASM-NEXT: .amdhsa_reserve_flat_scratch defined_boolean
  94 // ASM-NEXT: .amdhsa_reserve_xnack_mask 1
  95 // ASM-NEXT: .amdhsa_float_round_mode_32 ((((((((((9175040|(defined_boolean<<21))&(~8388608))|(defined_boolean<<23))&(~67108864))|(defined_boolean<<26))&(~63))|(((alignto(max(defined_boolean+1, 1), 8))/8)-1))&(~960))|((((alignto(max((defined_boolean+2)+(extrasgprs(defined_boolean, defined_boolean, 1)), 1), 8))/8)-1)<<6))&12288)>>12
  96 // ASM-NEXT: .amdhsa_float_round_mode_16_64 ((((((((((9175040|(defined_boolean<<21))&(~8388608))|(defined_boolean<<23))&(~67108864))|(defined_boolean<<26))&(~63))|(((alignto(max(defined_boolean+1, 1), 8))/8)-1))&(~960))|((((alignto(max((defined_boolean+2)+(extrasgprs(defined_boolean, defined_boolean, 1)), 1), 8))/8)-1)<<6))&49152)>>14
  97 // ASM-NEXT: .amdhsa_float_denorm_mode_32 ((((((((((9175040|(defined_boolean<<21))&(~8388608))|(defined_boolean<<23))&(~67108864))|(defined_boolean<<26))&(~63))|(((alignto(max(defined_boolean+1, 1), 8))/8)-1))&(~960))|((((alignto(max((defined_boolean+2)+(extrasgprs(defined_boolean, defined_boolean, 1)), 1), 8))/8)-1)<<6))&196608)>>16
  98 // ASM-NEXT: .amdhsa_float_denorm_mode_16_64 3
  99 // ASM-NEXT: .amdhsa_dx10_clamp ((((((((((9175040|(defined_boolean<<21))&(~8388608))|(defined_boolean<<23))&(~67108864))|(defined_boolean<<26))&(~63))|(((alignto(max(defined_boolean+1, 1), 8))/8)-1))&(~960))|((((alignto(max((defined_boolean+2)+(extrasgprs(defined_boolean, defined_boolean, 1)), 1), 8))/8)-1)<<6))&2097152)>>21
 100 // ASM-NEXT: .amdhsa_ieee_mode ((((((((((9175040|(defined_boolean<<21))&(~8388608))|(defined_boolean<<23))&(~67108864))|(defined_boolean<<26))&(~63))|(((alignto(max(defined_boolean+1, 1), 8))/8)-1))&(~960))|((((alignto(max((defined_boolean+2)+(extrasgprs(defined_boolean, defined_boolean, 1)), 1), 8))/8)-1)<<6))&8388608)>>23
 101 // ASM-NEXT: .amdhsa_fp16_overflow ((((((((((9175040|(defined_boolean<<21))&(~8388608))|(defined_boolean<<23))&(~67108864))|(defined_boolean<<26))&(~63))|(((alignto(max(defined_boolean+1, 1), 8))/8)-1))&(~960))|((((alignto(max((defined_boolean+2)+(extrasgprs(defined_boolean, defined_boolean, 1)), 1), 8))/8)-1)<<6))&67108864)>>26
 102 // ASM-NEXT: .amdhsa_tg_split (((defined_boolean<<16)&(~63))&65536)>>16
 103 // ASM-NEXT: .amdhsa_exception_fp_ieee_invalid_op (((128|defined_boolean)&(~62))&16777216)>>24
 104 // ASM-NEXT: .amdhsa_exception_fp_denorm_src (((128|defined_boolean)&(~62))&33554432)>>25
 105 // ASM-NEXT: .amdhsa_exception_fp_ieee_div_zero (((128|defined_boolean)&(~62))&67108864)>>26
 106 // ASM-NEXT: .amdhsa_exception_fp_ieee_overflow (((128|defined_boolean)&(~62))&134217728)>>27
 107 // ASM-NEXT: .amdhsa_exception_fp_ieee_underflow (((128|defined_boolean)&(~62))&268435456)>>28
 108 // ASM-NEXT: .amdhsa_exception_fp_ieee_inexact (((128|defined_boolean)&(~62))&536870912)>>29
 109 // ASM-NEXT: .amdhsa_exception_int_div_zero (((128|defined_boolean)&(~62))&1073741824)>>30
 110 // ASM-NEXT: .end_amdhsa_kernel
 111
 112 // ASM:       .set defined_boolean, 1
 113 // ASM-NEXT:  .no_dead_strip defined_boolean
 114
 115 // ASM: .amdhsa_kernel expr_defined
 116 // ASM-NEXT: .amdhsa_group_segment_fixed_size 0
 117 // ASM-NEXT: .amdhsa_private_segment_fixed_size 0
 118 // ASM-NEXT: .amdhsa_kernarg_size 0
 119 // ASM-NEXT: .amdhsa_user_sgpr_count 0
 120 // ASM-NEXT: .amdhsa_user_sgpr_private_segment_buffer 0
 121 // ASM-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
 122 // ASM-NEXT: .amdhsa_user_sgpr_queue_ptr 0
 123 // ASM-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
 124 // ASM-NEXT: .amdhsa_user_sgpr_dispatch_id 0
 125 // ASM-NEXT: .amdhsa_user_sgpr_flat_scratch_init 0
 126 // ASM-NEXT: .amdhsa_user_sgpr_kernarg_preload_length 0
 127 // ASM-NEXT: .amdhsa_user_sgpr_kernarg_preload_offset 0
 128 // ASM-NEXT: .amdhsa_user_sgpr_private_segment_size 0
 129 // ASM-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
 130 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
 131 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
 132 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
 133 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_info 0
 134 // ASM-NEXT: .amdhsa_system_vgpr_workitem_id 0
 135 // ASM-NEXT: .amdhsa_next_free_vgpr 2
 136 // ASM-NEXT: .amdhsa_next_free_sgpr 3
 137 // ASM-NEXT: .amdhsa_accum_offset 4
 138 // ASM-NEXT: .amdhsa_reserve_vcc 1
 139 // ASM-NEXT: .amdhsa_reserve_flat_scratch 1
 140 // ASM-NEXT: .amdhsa_reserve_xnack_mask 1
 141 // ASM-NEXT: .amdhsa_float_round_mode_32 0
 142 // ASM-NEXT: .amdhsa_float_round_mode_16_64 0
 143 // ASM-NEXT: .amdhsa_float_denorm_mode_32 0
 144 // ASM-NEXT: .amdhsa_float_denorm_mode_16_64 3
 145 // ASM-NEXT: .amdhsa_dx10_clamp 1
 146 // ASM-NEXT: .amdhsa_ieee_mode 1
 147 // ASM-NEXT: .amdhsa_fp16_overflow 1
 148 // ASM-NEXT: .amdhsa_tg_split 1
 149 // ASM-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
 150 // ASM-NEXT: .amdhsa_exception_fp_denorm_src 0
 151 // ASM-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
 152 // ASM-NEXT: .amdhsa_exception_fp_ieee_overflow 0
 153 // ASM-NEXT: .amdhsa_exception_fp_ieee_underflow 0
 154 // ASM-NEXT: .amdhsa_exception_fp_ieee_inexact 0
 155 // ASM-NEXT: .amdhsa_exception_int_div_zero 0
 156 // ASM-NEXT: .end_amdhsa_kernel