llvm/utils/TableGen/X86RecognizableInstr.cpp

   1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec -*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file is part of the X86 Disassembler Emitter.
  10 // It contains the implementation of a single recognizable instruction.
  11 // Documentation for the disassembler emitter in general can be found in
  12 //  X86DisassemblerEmitter.h.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "X86RecognizableInstr.h"
  17 #include "X86DisassemblerShared.h"
  18 #include "X86DisassemblerTables.h"
  19 #include "X86ModRMFilters.h"
  20 #include "llvm/Support/ErrorHandling.h"
  21 #include "llvm/TableGen/Record.h"
  22 #include <string>
  23
  24 using namespace llvm;
  25 using namespace X86Disassembler;
  26
  27 std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I,
  28                                          unsigned Variant) {
  29   // Extract a mnemonic assuming it's separated by \t
  30   std::string Mnemonic =
  31       StringRef(I->FlattenAsmStringVariants(I->AsmString, Variant))
  32           .take_until([](char C) { return C == '\t'; })
  33           .str();
  34
  35   // Special case: CMOVCC, JCC, SETCC, CMPCCXADD have "${cond}" in mnemonic.
  36   // Replace it with "CC" in-place.
  37   auto CondPos = Mnemonic.find("${cond}");
  38   if (CondPos != std::string::npos)
  39     Mnemonic = Mnemonic.replace(CondPos, 7, "CC");
  40   return StringRef(Mnemonic).upper();
  41 }
  42
  43 bool X86Disassembler::isRegisterOperand(const Record *Rec) {
  44   return Rec->isSubClassOf("RegisterClass") ||
  45          Rec->isSubClassOf("RegisterOperand");
  46 }
  47
  48 bool X86Disassembler::isMemoryOperand(const Record *Rec) {
  49   return Rec->isSubClassOf("Operand") &&
  50          Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
  51 }
  52
  53 bool X86Disassembler::isImmediateOperand(const Record *Rec) {
  54   return Rec->isSubClassOf("Operand") &&
  55          Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
  56 }
  57
  58 unsigned X86Disassembler::getRegOperandSize(const Record *RegRec) {
  59   if (RegRec->isSubClassOf("RegisterClass"))
  60     return RegRec->getValueAsInt("Alignment");
  61   if (RegRec->isSubClassOf("RegisterOperand"))
  62     return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
  63
  64   llvm_unreachable("Register operand's size not known!");
  65 }
  66
  67 unsigned X86Disassembler::getMemOperandSize(const Record *MemRec) {
  68   if (MemRec->isSubClassOf("X86MemOperand"))
  69     return MemRec->getValueAsInt("Size");
  70
  71   llvm_unreachable("Memory operand's size not known!");
  72 }
  73
  74 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
  75 ///   Useful for switch statements and the like.
  76 ///
  77 /// @param init - A reference to the BitsInit to be decoded.
  78 /// @return     - The field, with the first bit in the BitsInit as the lowest
  79 ///               order bit.
  80 static uint8_t byteFromBitsInit(const BitsInit &init) {
  81   int width = init.getNumBits();
  82
  83   assert(width <= 8 && "Field is too large for uint8_t!");
  84
  85   uint8_t mask = 0x01;
  86   uint8_t ret = 0;
  87
  88   for (int index = 0; index < width; index++) {
  89     if (cast<BitInit>(init.getBit(index))->getValue())
  90       ret |= mask;
  91
  92     mask <<= 1;
  93   }
  94
  95   return ret;
  96 }
  97
  98 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
  99 ///   name of the field.
 100 ///
 101 /// @param rec  - The record from which to extract the value.
 102 /// @param name - The name of the field in the record.
 103 /// @return     - The field, as translated by byteFromBitsInit().
 104 static uint8_t byteFromRec(const Record *rec, StringRef name) {
 105   const BitsInit *bits = rec->getValueAsBitsInit(name);
 106   return byteFromBitsInit(*bits);
 107 }
 108
 109 RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) {
 110   const Record *Rec = insn.TheDef;
 111   assert(Rec->isSubClassOf("X86Inst") && "Not a X86 Instruction");
 112   OpPrefix = byteFromRec(Rec, "OpPrefixBits");
 113   OpMap = byteFromRec(Rec, "OpMapBits");
 114   Opcode = byteFromRec(Rec, "Opcode");
 115   Form = byteFromRec(Rec, "FormBits");
 116   Encoding = byteFromRec(Rec, "OpEncBits");
 117   OpSize = byteFromRec(Rec, "OpSizeBits");
 118   AdSize = byteFromRec(Rec, "AdSizeBits");
 119   HasREX_W = Rec->getValueAsBit("hasREX_W");
 120   HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
 121   IgnoresW = Rec->getValueAsBit("IgnoresW");
 122   IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
 123   HasEVEX_L2 = Rec->getValueAsBit("hasEVEX_L2");
 124   HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
 125   HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
 126   HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
 127   HasEVEX_U = Rec->getValueAsBit("hasEVEX_U");
 128   HasEVEX_NF = Rec->getValueAsBit("hasEVEX_NF");
 129   HasTwoConditionalOps = Rec->getValueAsBit("hasTwoConditionalOps");
 130   IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
 131   IsAsmParserOnly = Rec->getValueAsBit("isAsmParserOnly");
 132   ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
 133   CD8_Scale = byteFromRec(Rec, "CD8_Scale");
 134   HasVEX_L = Rec->getValueAsBit("hasVEX_L");
 135   ExplicitREX2Prefix =
 136       byteFromRec(Rec, "explicitOpPrefixBits") == X86Local::ExplicitREX2;
 137
 138   EncodeRC = HasEVEX_B &&
 139              (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg);
 140 }
 141
 142 bool RecognizableInstrBase::shouldBeEmitted() const {
 143   return Form != X86Local::Pseudo && (!IsCodeGenOnly || ForceDisassemble) &&
 144          !IsAsmParserOnly;
 145 }
 146
 147 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
 148                                      const CodeGenInstruction &insn,
 149                                      InstrUID uid)
 150     : RecognizableInstrBase(insn), Rec(insn.TheDef), Name(Rec->getName().str()),
 151       Is32Bit(false), Is64Bit(false), Operands(&insn.Operands.OperandList),
 152       UID(uid), Spec(&tables.specForUID(uid)) {
 153   // Check for 64-bit inst which does not require REX
 154   // FIXME: Is there some better way to check for In64BitMode?
 155   for (const Record *Predicate : Rec->getValueAsListOfDefs("Predicates")) {
 156     if (Predicate->getName().contains("Not64Bit") ||
 157         Predicate->getName().contains("In32Bit")) {
 158       Is32Bit = true;
 159       break;
 160     }
 161     if (Predicate->getName().contains("In64Bit")) {
 162       Is64Bit = true;
 163       break;
 164     }
 165   }
 166 }
 167
 168 void RecognizableInstr::processInstr(DisassemblerTables &tables,
 169                                      const CodeGenInstruction &insn,
 170                                      InstrUID uid) {
 171   if (!insn.TheDef->isSubClassOf("X86Inst"))
 172     return;
 173   RecognizableInstr recogInstr(tables, insn, uid);
 174
 175   if (!recogInstr.shouldBeEmitted())
 176     return;
 177   recogInstr.emitInstructionSpecifier();
 178   recogInstr.emitDecodePath(tables);
 179 }
 180
 181 #define EVEX_KB(n)                                                             \
 182   (HasEVEX_KZ && HasEVEX_B                                                     \
 183        ? n##_KZ_B                                                              \
 184        : (HasEVEX_K && HasEVEX_B                                               \
 185               ? n##_K_B                                                        \
 186               : (HasEVEX_KZ ? n##_KZ                                           \
 187                             : (HasEVEX_K ? n##_K : (HasEVEX_B ? n##_B : n)))))
 188
 189 #define EVEX_NF(n) (HasEVEX_NF ? n##_NF : n)
 190 #define EVEX_B_NF(n) (HasEVEX_B ? EVEX_NF(n##_B) : EVEX_NF(n))
 191 #define EVEX_KB_ADSIZE(n) AdSize == X86Local::AdSize32 ? n##_ADSIZE : EVEX_KB(n)
 192 #define EVEX_KB_U(n)                                                           \
 193   (HasEVEX_KZ ? n##_KZ_B_U : (HasEVEX_K ? n##_K_B_U : n##_B_U))
 194
 195 InstructionContext RecognizableInstr::insnContext() const {
 196   InstructionContext insnContext;
 197
 198   if (Encoding == X86Local::EVEX) {
 199     if (HasVEX_L && HasEVEX_L2) {
 200       errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
 201       llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
 202     }
 203     if (EncodeRC && HasEVEX_U) {
 204       // EVEX_U
 205       if (HasREX_W) {
 206         if (OpPrefix == X86Local::PD)
 207           insnContext = EVEX_KB_U(IC_EVEX_W_OPSIZE);
 208         else if (OpPrefix == X86Local::XS)
 209           insnContext = EVEX_KB_U(IC_EVEX_W_XS);
 210         else if (OpPrefix == X86Local::XD)
 211           insnContext = EVEX_KB_U(IC_EVEX_W_XD);
 212         else if (OpPrefix == X86Local::PS)
 213           insnContext = EVEX_KB_U(IC_EVEX_W);
 214         else {
 215           errs() << "Instruction does not use a prefix: " << Name << "\n";
 216           llvm_unreachable("Invalid prefix");
 217         }
 218       } else {
 219         if (OpPrefix == X86Local::PD)
 220           insnContext = EVEX_KB_U(IC_EVEX_OPSIZE);
 221         else if (OpPrefix == X86Local::XS)
 222           insnContext = EVEX_KB_U(IC_EVEX_XS);
 223         else if (OpPrefix == X86Local::XD)
 224           insnContext = EVEX_KB_U(IC_EVEX_XD);
 225         else if (OpPrefix == X86Local::PS)
 226           insnContext = EVEX_KB_U(IC_EVEX);
 227         else {
 228           errs() << "Instruction does not use a prefix: " << Name << "\n";
 229           llvm_unreachable("Invalid prefix");
 230         }
 231       }
 232     } else if (HasEVEX_NF) {
 233       if (OpPrefix == X86Local::PD)
 234         insnContext = EVEX_B_NF(IC_EVEX_OPSIZE);
 235       else if (HasREX_W)
 236         insnContext = EVEX_B_NF(IC_EVEX_W);
 237       else
 238         insnContext = EVEX_B_NF(IC_EVEX);
 239     } else if (!EncodeRC && HasVEX_L && HasREX_W) {
 240       // VEX_L & VEX_W
 241       if (OpPrefix == X86Local::PD)
 242         insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
 243       else if (OpPrefix == X86Local::XS)
 244         insnContext = EVEX_KB(IC_EVEX_L_W_XS);
 245       else if (OpPrefix == X86Local::XD)
 246         insnContext = EVEX_KB(IC_EVEX_L_W_XD);
 247       else if (OpPrefix == X86Local::PS)
 248         insnContext = EVEX_KB(IC_EVEX_L_W);
 249       else {
 250         errs() << "Instruction does not use a prefix: " << Name << "\n";
 251         llvm_unreachable("Invalid prefix");
 252       }
 253     } else if (!EncodeRC && HasVEX_L) {
 254       // VEX_L
 255       if (OpPrefix == X86Local::PD)
 256         insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
 257       else if (OpPrefix == X86Local::XS)
 258         insnContext = EVEX_KB(IC_EVEX_L_XS);
 259       else if (OpPrefix == X86Local::XD)
 260         insnContext = EVEX_KB(IC_EVEX_L_XD);
 261       else if (OpPrefix == X86Local::PS)
 262         insnContext = EVEX_KB(IC_EVEX_L);
 263       else {
 264         errs() << "Instruction does not use a prefix: " << Name << "\n";
 265         llvm_unreachable("Invalid prefix");
 266       }
 267     } else if (!EncodeRC && HasEVEX_L2 && HasREX_W) {
 268       // EVEX_L2 & VEX_W
 269       if (OpPrefix == X86Local::PD)
 270         insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
 271       else if (OpPrefix == X86Local::XS)
 272         insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
 273       else if (OpPrefix == X86Local::XD)
 274         insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
 275       else if (OpPrefix == X86Local::PS)
 276         insnContext = EVEX_KB(IC_EVEX_L2_W);
 277       else {
 278         errs() << "Instruction does not use a prefix: " << Name << "\n";
 279         llvm_unreachable("Invalid prefix");
 280       }
 281     } else if (!EncodeRC && HasEVEX_L2) {
 282       // EVEX_L2
 283       if (OpPrefix == X86Local::PD)
 284         insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
 285       else if (OpPrefix == X86Local::XD)
 286         insnContext = EVEX_KB(IC_EVEX_L2_XD);
 287       else if (OpPrefix == X86Local::XS)
 288         insnContext = EVEX_KB(IC_EVEX_L2_XS);
 289       else if (OpPrefix == X86Local::PS)
 290         insnContext = EVEX_KB(IC_EVEX_L2);
 291       else {
 292         errs() << "Instruction does not use a prefix: " << Name << "\n";
 293         llvm_unreachable("Invalid prefix");
 294       }
 295     } else if (HasREX_W) {
 296       // VEX_W
 297       if (OpPrefix == X86Local::PD)
 298         insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
 299       else if (OpPrefix == X86Local::XS)
 300         insnContext = EVEX_KB(IC_EVEX_W_XS);
 301       else if (OpPrefix == X86Local::XD)
 302         insnContext = EVEX_KB(IC_EVEX_W_XD);
 303       else if (OpPrefix == X86Local::PS)
 304         insnContext = EVEX_KB(IC_EVEX_W);
 305       else {
 306         errs() << "Instruction does not use a prefix: " << Name << "\n";
 307         llvm_unreachable("Invalid prefix");
 308       }
 309     }
 310     // No L, no W
 311     else if (OpPrefix == X86Local::PD) {
 312       insnContext = EVEX_KB_ADSIZE(IC_EVEX_OPSIZE);
 313     } else if (OpPrefix == X86Local::XD)
 314       insnContext = EVEX_KB_ADSIZE(IC_EVEX_XD);
 315     else if (OpPrefix == X86Local::XS)
 316       insnContext = EVEX_KB_ADSIZE(IC_EVEX_XS);
 317     else if (OpPrefix == X86Local::PS)
 318       insnContext = EVEX_KB(IC_EVEX);
 319     else {
 320       errs() << "Instruction does not use a prefix: " << Name << "\n";
 321       llvm_unreachable("Invalid prefix");
 322     }
 323     /// eof EVEX
 324   } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
 325     if (HasVEX_L && HasREX_W) {
 326       if (OpPrefix == X86Local::PD)
 327         insnContext = IC_VEX_L_W_OPSIZE;
 328       else if (OpPrefix == X86Local::XS)
 329         insnContext = IC_VEX_L_W_XS;
 330       else if (OpPrefix == X86Local::XD)
 331         insnContext = IC_VEX_L_W_XD;
 332       else if (OpPrefix == X86Local::PS)
 333         insnContext = IC_VEX_L_W;
 334       else {
 335         errs() << "Instruction does not use a prefix: " << Name << "\n";
 336         llvm_unreachable("Invalid prefix");
 337       }
 338     } else if (OpPrefix == X86Local::PD && HasVEX_L)
 339       insnContext = IC_VEX_L_OPSIZE;
 340     else if (OpPrefix == X86Local::PD && HasREX_W)
 341       insnContext = IC_VEX_W_OPSIZE;
 342     else if (OpPrefix == X86Local::PD)
 343       insnContext = IC_VEX_OPSIZE;
 344     else if (HasVEX_L && OpPrefix == X86Local::XS)
 345       insnContext = IC_VEX_L_XS;
 346     else if (HasVEX_L && OpPrefix == X86Local::XD)
 347       insnContext = IC_VEX_L_XD;
 348     else if (HasREX_W && OpPrefix == X86Local::XS)
 349       insnContext = IC_VEX_W_XS;
 350     else if (HasREX_W && OpPrefix == X86Local::XD)
 351       insnContext = IC_VEX_W_XD;
 352     else if (HasREX_W && OpPrefix == X86Local::PS)
 353       insnContext = IC_VEX_W;
 354     else if (HasVEX_L && OpPrefix == X86Local::PS)
 355       insnContext = IC_VEX_L;
 356     else if (OpPrefix == X86Local::XD)
 357       insnContext = IC_VEX_XD;
 358     else if (OpPrefix == X86Local::XS)
 359       insnContext = IC_VEX_XS;
 360     else if (OpPrefix == X86Local::PS)
 361       insnContext = IC_VEX;
 362     else {
 363       errs() << "Instruction does not use a prefix: " << Name << "\n";
 364       llvm_unreachable("Invalid prefix");
 365     }
 366   } else if (Is64Bit || HasREX_W || AdSize == X86Local::AdSize64) {
 367     if (HasREX_W && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
 368       insnContext = IC_64BIT_REXW_OPSIZE;
 369     else if (HasREX_W && AdSize == X86Local::AdSize32)
 370       insnContext = IC_64BIT_REXW_ADSIZE;
 371     else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
 372       insnContext = IC_64BIT_XD_OPSIZE;
 373     else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
 374       insnContext = IC_64BIT_XS_OPSIZE;
 375     else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD)
 376       insnContext = IC_64BIT_OPSIZE_ADSIZE;
 377     else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
 378       insnContext = IC_64BIT_OPSIZE_ADSIZE;
 379     else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
 380       insnContext = IC_64BIT_OPSIZE;
 381     else if (AdSize == X86Local::AdSize32)
 382       insnContext = IC_64BIT_ADSIZE;
 383     else if (HasREX_W && OpPrefix == X86Local::XS)
 384       insnContext = IC_64BIT_REXW_XS;
 385     else if (HasREX_W && OpPrefix == X86Local::XD)
 386       insnContext = IC_64BIT_REXW_XD;
 387     else if (OpPrefix == X86Local::XD)
 388       insnContext = IC_64BIT_XD;
 389     else if (OpPrefix == X86Local::XS)
 390       insnContext = IC_64BIT_XS;
 391     else if (ExplicitREX2Prefix)
 392       insnContext = IC_64BIT_REX2;
 393     else if (HasREX_W)
 394       insnContext = IC_64BIT_REXW;
 395     else
 396       insnContext = IC_64BIT;
 397   } else {
 398     if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
 399       insnContext = IC_XD_OPSIZE;
 400     else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
 401       insnContext = IC_XS_OPSIZE;
 402     else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD)
 403       insnContext = IC_XD_ADSIZE;
 404     else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS)
 405       insnContext = IC_XS_ADSIZE;
 406     else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD)
 407       insnContext = IC_OPSIZE_ADSIZE;
 408     else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
 409       insnContext = IC_OPSIZE_ADSIZE;
 410     else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
 411       insnContext = IC_OPSIZE;
 412     else if (AdSize == X86Local::AdSize16)
 413       insnContext = IC_ADSIZE;
 414     else if (OpPrefix == X86Local::XD)
 415       insnContext = IC_XD;
 416     else if (OpPrefix == X86Local::XS)
 417       insnContext = IC_XS;
 418     else
 419       insnContext = IC;
 420   }
 421
 422   return insnContext;
 423 }
 424
 425 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
 426   // The scaling factor for AVX512 compressed displacement encoding is an
 427   // instruction attribute.  Adjust the ModRM encoding type to include the
 428   // scale for compressed displacement.
 429   if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB &&
 430        encoding != ENCODING_SIB) ||
 431       CD8_Scale == 0)
 432     return;
 433   encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
 434   assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) ||
 435           (encoding == ENCODING_SIB) ||
 436           (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) &&
 437          "Invalid CDisp scaling");
 438 }
 439
 440 void RecognizableInstr::handleOperand(
 441     bool optional, unsigned &operandIndex, unsigned &physicalOperandIndex,
 442     unsigned numPhysicalOperands, const unsigned *operandMapping,
 443     OperandEncoding (*encodingFromString)(const std::string &,
 444                                           uint8_t OpSize)) {
 445   if (optional) {
 446     if (physicalOperandIndex >= numPhysicalOperands)
 447       return;
 448   } else {
 449     assert(physicalOperandIndex < numPhysicalOperands);
 450   }
 451
 452   while (operandMapping[operandIndex] != operandIndex) {
 453     Spec->operands[operandIndex].encoding = ENCODING_DUP;
 454     Spec->operands[operandIndex].type =
 455         (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
 456     ++operandIndex;
 457   }
 458
 459   StringRef typeName = (*Operands)[operandIndex].Rec->getName();
 460
 461   OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize);
 462   // Adjust the encoding type for an operand based on the instruction.
 463   adjustOperandEncoding(encoding);
 464   Spec->operands[operandIndex].encoding = encoding;
 465   Spec->operands[operandIndex].type =
 466       typeFromString(std::string(typeName), HasREX_W, OpSize);
 467
 468   ++operandIndex;
 469   ++physicalOperandIndex;
 470 }
 471
 472 void RecognizableInstr::emitInstructionSpecifier() {
 473   Spec->name = Name;
 474
 475   Spec->insnContext = insnContext();
 476
 477   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
 478
 479   unsigned numOperands = OperandList.size();
 480   unsigned numPhysicalOperands = 0;
 481
 482   // operandMapping maps from operands in OperandList to their originals.
 483   // If operandMapping[i] != i, then the entry is a duplicate.
 484   unsigned operandMapping[X86_MAX_OPERANDS];
 485   assert(numOperands <= X86_MAX_OPERANDS &&
 486          "X86_MAX_OPERANDS is not large enough");
 487
 488   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
 489     if (!OperandList[operandIndex].Constraints.empty()) {
 490       const CGIOperandList::ConstraintInfo &Constraint =
 491           OperandList[operandIndex].Constraints[0];
 492       if (Constraint.isTied()) {
 493         operandMapping[operandIndex] = operandIndex;
 494         operandMapping[Constraint.getTiedOperand()] = operandIndex;
 495       } else {
 496         ++numPhysicalOperands;
 497         operandMapping[operandIndex] = operandIndex;
 498       }
 499     } else {
 500       ++numPhysicalOperands;
 501       operandMapping[operandIndex] = operandIndex;
 502     }
 503   }
 504
 505 #define HANDLE_OPERAND(class)                                                  \
 506   handleOperand(false, operandIndex, physicalOperandIndex,                     \
 507                 numPhysicalOperands, operandMapping,                           \
 508                 class##EncodingFromString);
 509
 510 #define HANDLE_OPTIONAL(class)                                                 \
 511   handleOperand(true, operandIndex, physicalOperandIndex, numPhysicalOperands, \
 512                 operandMapping, class##EncodingFromString);
 513
 514   // operandIndex should always be < numOperands
 515   unsigned operandIndex = 0;
 516   // physicalOperandIndex should always be < numPhysicalOperands
 517   unsigned physicalOperandIndex = 0;
 518
 519 #ifndef NDEBUG
 520   // Given the set of prefix bits, how many additional operands does the
 521   // instruction have?
 522   unsigned additionalOperands = 0;
 523   if (HasVEX_4V)
 524     ++additionalOperands;
 525   if (HasEVEX_K)
 526     ++additionalOperands;
 527   if (HasTwoConditionalOps)
 528     additionalOperands += 2;
 529 #endif
 530
 531   bool IsND = OpMap == X86Local::T_MAP4 && HasEVEX_B && HasVEX_4V;
 532   switch (Form) {
 533   default:
 534     llvm_unreachable("Unhandled form");
 535   case X86Local::PrefixByte:
 536     return;
 537   case X86Local::RawFrmSrc:
 538     HANDLE_OPERAND(relocation);
 539     return;
 540   case X86Local::RawFrmDst:
 541     HANDLE_OPERAND(relocation);
 542     return;
 543   case X86Local::RawFrmDstSrc:
 544     HANDLE_OPERAND(relocation);
 545     HANDLE_OPERAND(relocation);
 546     return;
 547   case X86Local::RawFrm:
 548     // Operand 1 (optional) is an address or immediate.
 549     assert(numPhysicalOperands <= 1 &&
 550            "Unexpected number of operands for RawFrm");
 551     HANDLE_OPTIONAL(relocation)
 552     break;
 553   case X86Local::RawFrmMemOffs:
 554     // Operand 1 is an address.
 555     HANDLE_OPERAND(relocation);
 556     break;
 557   case X86Local::AddRegFrm:
 558     // Operand 1 is added to the opcode.
 559     // Operand 2 (optional) is an address.
 560     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
 561            "Unexpected number of operands for AddRegFrm");
 562     HANDLE_OPERAND(opcodeModifier)
 563     HANDLE_OPTIONAL(relocation)
 564     break;
 565   case X86Local::AddCCFrm:
 566     // Operand 1 (optional) is an address or immediate.
 567     assert(numPhysicalOperands == 2 &&
 568            "Unexpected number of operands for AddCCFrm");
 569     HANDLE_OPERAND(relocation)
 570     HANDLE_OPERAND(opcodeModifier)
 571     break;
 572   case X86Local::MRMDestRegCC:
 573     assert(numPhysicalOperands == 3 &&
 574            "Unexpected number of operands for MRMDestRegCC");
 575     HANDLE_OPERAND(rmRegister)
 576     HANDLE_OPERAND(roRegister)
 577     HANDLE_OPERAND(opcodeModifier)
 578     break;
 579   case X86Local::MRMDestReg:
 580     // Operand 1 is a register operand in the R/M field.
 581     // - In AVX512 there may be a mask operand here -
 582     // Operand 2 is a register operand in the Reg/Opcode field.
 583     // - In AVX, there is a register operand in the VEX.vvvv field here -
 584     // Operand 3 (optional) is an immediate.
 585     assert(numPhysicalOperands >= 2 + additionalOperands &&
 586            numPhysicalOperands <= 3 + additionalOperands &&
 587            "Unexpected number of operands for MRMDestReg");
 588
 589     if (IsND)
 590       HANDLE_OPERAND(vvvvRegister)
 591
 592     HANDLE_OPERAND(rmRegister)
 593     if (HasEVEX_K)
 594       HANDLE_OPERAND(writemaskRegister)
 595
 596     if (!IsND && HasVEX_4V)
 597       // FIXME: In AVX, the register below becomes the one encoded
 598       // in ModRMVEX and the one above the one in the VEX.VVVV field
 599       HANDLE_OPERAND(vvvvRegister)
 600
 601     HANDLE_OPERAND(roRegister)
 602     HANDLE_OPTIONAL(immediate)
 603     HANDLE_OPTIONAL(immediate)
 604     break;
 605   case X86Local::MRMDestMemCC:
 606     assert(numPhysicalOperands == 3 &&
 607            "Unexpected number of operands for MRMDestMemCC");
 608     HANDLE_OPERAND(memory)
 609     HANDLE_OPERAND(roRegister)
 610     HANDLE_OPERAND(opcodeModifier)
 611     break;
 612   case X86Local::MRMDestMem4VOp3CC:
 613     // Operand 1 is a register operand in the Reg/Opcode field.
 614     // Operand 2 is a register operand in the R/M field.
 615     // Operand 3 is VEX.vvvv
 616     // Operand 4 is condition code.
 617     assert(numPhysicalOperands == 4 &&
 618            "Unexpected number of operands for MRMDestMem4VOp3CC");
 619     HANDLE_OPERAND(roRegister)
 620     HANDLE_OPERAND(memory)
 621     HANDLE_OPERAND(vvvvRegister)
 622     HANDLE_OPERAND(opcodeModifier)
 623     break;
 624   case X86Local::MRMDestMem:
 625   case X86Local::MRMDestMemFSIB:
 626     // Operand 1 is a memory operand (possibly SIB-extended)
 627     // Operand 2 is a register operand in the Reg/Opcode field.
 628     // - In AVX, there is a register operand in the VEX.vvvv field here -
 629     // Operand 3 (optional) is an immediate.
 630     assert(numPhysicalOperands >= 2 + additionalOperands &&
 631            numPhysicalOperands <= 3 + additionalOperands &&
 632            "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
 633
 634     if (IsND)
 635       HANDLE_OPERAND(vvvvRegister)
 636
 637     HANDLE_OPERAND(memory)
 638
 639     if (HasEVEX_K)
 640       HANDLE_OPERAND(writemaskRegister)
 641
 642     if (!IsND && HasVEX_4V)
 643       // FIXME: In AVX, the register below becomes the one encoded
 644       // in ModRMVEX and the one above the one in the VEX.VVVV field
 645       HANDLE_OPERAND(vvvvRegister)
 646
 647     HANDLE_OPERAND(roRegister)
 648     HANDLE_OPTIONAL(immediate)
 649     HANDLE_OPTIONAL(immediate)
 650     break;
 651   case X86Local::MRMSrcReg:
 652     // Operand 1 is a register operand in the Reg/Opcode field.
 653     // Operand 2 is a register operand in the R/M field.
 654     // - In AVX, there is a register operand in the VEX.vvvv field here -
 655     // Operand 3 (optional) is an immediate.
 656     // Operand 4 (optional) is an immediate.
 657
 658     assert(numPhysicalOperands >= 2 + additionalOperands &&
 659            numPhysicalOperands <= 4 + additionalOperands &&
 660            "Unexpected number of operands for MRMSrcRegFrm");
 661
 662     if (IsND)
 663       HANDLE_OPERAND(vvvvRegister)
 664
 665     HANDLE_OPERAND(roRegister)
 666
 667     if (HasEVEX_K)
 668       HANDLE_OPERAND(writemaskRegister)
 669
 670     if (!IsND && HasVEX_4V)
 671       // FIXME: In AVX, the register below becomes the one encoded
 672       // in ModRMVEX and the one above the one in the VEX.VVVV field
 673       HANDLE_OPERAND(vvvvRegister)
 674
 675     HANDLE_OPERAND(rmRegister)
 676     HANDLE_OPTIONAL(immediate)
 677     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
 678     break;
 679   case X86Local::MRMSrcReg4VOp3:
 680     assert(numPhysicalOperands == 3 &&
 681            "Unexpected number of operands for MRMSrcReg4VOp3Frm");
 682     HANDLE_OPERAND(roRegister)
 683     HANDLE_OPERAND(rmRegister)
 684     HANDLE_OPERAND(vvvvRegister)
 685     break;
 686   case X86Local::MRMSrcRegOp4:
 687     assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
 688            "Unexpected number of operands for MRMSrcRegOp4Frm");
 689     HANDLE_OPERAND(roRegister)
 690     HANDLE_OPERAND(vvvvRegister)
 691     HANDLE_OPERAND(immediate) // Register in imm[7:4]
 692     HANDLE_OPERAND(rmRegister)
 693     HANDLE_OPTIONAL(immediate)
 694     break;
 695   case X86Local::MRMSrcRegCC:
 696     assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
 697            "Unexpected number of operands for MRMSrcRegCC");
 698     if (IsND)
 699       HANDLE_OPERAND(vvvvRegister)
 700     HANDLE_OPERAND(roRegister)
 701     HANDLE_OPERAND(rmRegister)
 702     HANDLE_OPERAND(opcodeModifier)
 703     break;
 704   case X86Local::MRMSrcMem:
 705   case X86Local::MRMSrcMemFSIB:
 706     // Operand 1 is a register operand in the Reg/Opcode field.
 707     // Operand 2 is a memory operand (possibly SIB-extended)
 708     // - In AVX, there is a register operand in the VEX.vvvv field here -
 709     // Operand 3 (optional) is an immediate.
 710
 711     assert(numPhysicalOperands >= 2 + additionalOperands &&
 712            numPhysicalOperands <= 4 + additionalOperands &&
 713            "Unexpected number of operands for MRMSrcMemFrm");
 714     if (IsND)
 715       HANDLE_OPERAND(vvvvRegister)
 716
 717     HANDLE_OPERAND(roRegister)
 718
 719     if (HasEVEX_K)
 720       HANDLE_OPERAND(writemaskRegister)
 721
 722     if (!IsND && HasVEX_4V)
 723       // FIXME: In AVX, the register below becomes the one encoded
 724       // in ModRMVEX and the one above the one in the VEX.VVVV field
 725       HANDLE_OPERAND(vvvvRegister)
 726
 727     HANDLE_OPERAND(memory)
 728     HANDLE_OPTIONAL(immediate)
 729     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
 730     break;
 731   case X86Local::MRMSrcMem4VOp3:
 732     assert(numPhysicalOperands == 3 &&
 733            "Unexpected number of operands for MRMSrcMem4VOp3Frm");
 734     HANDLE_OPERAND(roRegister)
 735     HANDLE_OPERAND(memory)
 736     HANDLE_OPERAND(vvvvRegister)
 737     break;
 738   case X86Local::MRMSrcMemOp4:
 739     assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
 740            "Unexpected number of operands for MRMSrcMemOp4Frm");
 741     HANDLE_OPERAND(roRegister)
 742     HANDLE_OPERAND(vvvvRegister)
 743     HANDLE_OPERAND(immediate) // Register in imm[7:4]
 744     HANDLE_OPERAND(memory)
 745     HANDLE_OPTIONAL(immediate)
 746     break;
 747   case X86Local::MRMSrcMemCC:
 748     assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
 749            "Unexpected number of operands for MRMSrcMemCC");
 750     if (IsND)
 751       HANDLE_OPERAND(vvvvRegister)
 752     HANDLE_OPERAND(roRegister)
 753     HANDLE_OPERAND(memory)
 754     HANDLE_OPERAND(opcodeModifier)
 755     break;
 756   case X86Local::MRMXrCC:
 757     assert(numPhysicalOperands == 2 &&
 758            "Unexpected number of operands for MRMXrCC");
 759     HANDLE_OPERAND(rmRegister)
 760     HANDLE_OPERAND(opcodeModifier)
 761     break;
 762   case X86Local::MRMr0:
 763     // Operand 1 is a register operand in the R/M field.
 764     HANDLE_OPERAND(roRegister)
 765     break;
 766   case X86Local::MRMXr:
 767   case X86Local::MRM0r:
 768   case X86Local::MRM1r:
 769   case X86Local::MRM2r:
 770   case X86Local::MRM3r:
 771   case X86Local::MRM4r:
 772   case X86Local::MRM5r:
 773   case X86Local::MRM6r:
 774   case X86Local::MRM7r:
 775     // Operand 1 is a register operand in the R/M field.
 776     // Operand 2 (optional) is an immediate or relocation.
 777     // Operand 3 (optional) is an immediate.
 778     assert(numPhysicalOperands >= 0 + additionalOperands &&
 779            numPhysicalOperands <= 3 + additionalOperands &&
 780            "Unexpected number of operands for MRMnr");
 781
 782     if (HasVEX_4V)
 783       HANDLE_OPERAND(vvvvRegister)
 784
 785     if (HasEVEX_K)
 786       HANDLE_OPERAND(writemaskRegister)
 787     HANDLE_OPTIONAL(rmRegister)
 788     HANDLE_OPTIONAL(relocation)
 789     HANDLE_OPTIONAL(immediate)
 790     HANDLE_OPTIONAL(immediate)
 791     break;
 792   case X86Local::MRMXmCC:
 793     assert(numPhysicalOperands == 2 &&
 794            "Unexpected number of operands for MRMXm");
 795     HANDLE_OPERAND(memory)
 796     HANDLE_OPERAND(opcodeModifier)
 797     break;
 798   case X86Local::MRMXm:
 799   case X86Local::MRM0m:
 800   case X86Local::MRM1m:
 801   case X86Local::MRM2m:
 802   case X86Local::MRM3m:
 803   case X86Local::MRM4m:
 804   case X86Local::MRM5m:
 805   case X86Local::MRM6m:
 806   case X86Local::MRM7m:
 807     // Operand 1 is a memory operand (possibly SIB-extended)
 808     // Operand 2 (optional) is an immediate or relocation.
 809     assert(numPhysicalOperands >= 1 + additionalOperands &&
 810            numPhysicalOperands <= 2 + additionalOperands &&
 811            "Unexpected number of operands for MRMnm");
 812
 813     if (HasVEX_4V)
 814       HANDLE_OPERAND(vvvvRegister)
 815     if (HasEVEX_K)
 816       HANDLE_OPERAND(writemaskRegister)
 817     HANDLE_OPERAND(memory)
 818     HANDLE_OPTIONAL(relocation)
 819     HANDLE_OPTIONAL(immediate)
 820     HANDLE_OPTIONAL(immediate)
 821     break;
 822   case X86Local::RawFrmImm8:
 823     // operand 1 is a 16-bit immediate
 824     // operand 2 is an 8-bit immediate
 825     assert(numPhysicalOperands == 2 &&
 826            "Unexpected number of operands for X86Local::RawFrmImm8");
 827     HANDLE_OPERAND(immediate)
 828     HANDLE_OPERAND(immediate)
 829     break;
 830   case X86Local::RawFrmImm16:
 831     // operand 1 is a 16-bit immediate
 832     // operand 2 is a 16-bit immediate
 833     HANDLE_OPERAND(immediate)
 834     HANDLE_OPERAND(immediate)
 835     break;
 836   case X86Local::MRM0X:
 837   case X86Local::MRM1X:
 838   case X86Local::MRM2X:
 839   case X86Local::MRM3X:
 840   case X86Local::MRM4X:
 841   case X86Local::MRM5X:
 842   case X86Local::MRM6X:
 843   case X86Local::MRM7X:
 844 #define MAP(from, to) case X86Local::MRM_##from:
 845     X86_INSTR_MRM_MAPPING
 846 #undef MAP
 847     HANDLE_OPTIONAL(relocation)
 848     break;
 849   }
 850
 851 #undef HANDLE_OPERAND
 852 #undef HANDLE_OPTIONAL
 853 }
 854
 855 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
 856   // Special cases where the LLVM tables are not complete
 857
 858 #define MAP(from, to) case X86Local::MRM_##from:
 859
 860   std::optional<OpcodeType> opcodeType;
 861   switch (OpMap) {
 862   default:
 863     llvm_unreachable("Invalid map!");
 864   case X86Local::OB:
 865     opcodeType = ONEBYTE;
 866     break;
 867   case X86Local::TB:
 868     opcodeType = TWOBYTE;
 869     break;
 870   case X86Local::T8:
 871     opcodeType = THREEBYTE_38;
 872     break;
 873   case X86Local::TA:
 874     opcodeType = THREEBYTE_3A;
 875     break;
 876   case X86Local::XOP8:
 877     opcodeType = XOP8_MAP;
 878     break;
 879   case X86Local::XOP9:
 880     opcodeType = XOP9_MAP;
 881     break;
 882   case X86Local::XOPA:
 883     opcodeType = XOPA_MAP;
 884     break;
 885   case X86Local::ThreeDNow:
 886     opcodeType = THREEDNOW_MAP;
 887     break;
 888   case X86Local::T_MAP4:
 889     opcodeType = MAP4;
 890     break;
 891   case X86Local::T_MAP5:
 892     opcodeType = MAP5;
 893     break;
 894   case X86Local::T_MAP6:
 895     opcodeType = MAP6;
 896     break;
 897   case X86Local::T_MAP7:
 898     opcodeType = MAP7;
 899     break;
 900   }
 901
 902   std::unique_ptr<ModRMFilter> filter;
 903   switch (Form) {
 904   default:
 905     llvm_unreachable("Invalid form!");
 906   case X86Local::Pseudo:
 907     llvm_unreachable("Pseudo should not be emitted!");
 908   case X86Local::RawFrm:
 909   case X86Local::AddRegFrm:
 910   case X86Local::RawFrmMemOffs:
 911   case X86Local::RawFrmSrc:
 912   case X86Local::RawFrmDst:
 913   case X86Local::RawFrmDstSrc:
 914   case X86Local::RawFrmImm8:
 915   case X86Local::RawFrmImm16:
 916   case X86Local::AddCCFrm:
 917   case X86Local::PrefixByte:
 918     filter = std::make_unique<DumbFilter>();
 919     break;
 920   case X86Local::MRMDestReg:
 921   case X86Local::MRMDestRegCC:
 922   case X86Local::MRMSrcReg:
 923   case X86Local::MRMSrcReg4VOp3:
 924   case X86Local::MRMSrcRegOp4:
 925   case X86Local::MRMSrcRegCC:
 926   case X86Local::MRMXrCC:
 927   case X86Local::MRMXr:
 928     filter = std::make_unique<ModFilter>(true);
 929     break;
 930   case X86Local::MRMDestMem:
 931   case X86Local::MRMDestMemCC:
 932   case X86Local::MRMDestMem4VOp3CC:
 933   case X86Local::MRMDestMemFSIB:
 934   case X86Local::MRMSrcMem:
 935   case X86Local::MRMSrcMemFSIB:
 936   case X86Local::MRMSrcMem4VOp3:
 937   case X86Local::MRMSrcMemOp4:
 938   case X86Local::MRMSrcMemCC:
 939   case X86Local::MRMXmCC:
 940   case X86Local::MRMXm:
 941     filter = std::make_unique<ModFilter>(false);
 942     break;
 943   case X86Local::MRM0r:
 944   case X86Local::MRM1r:
 945   case X86Local::MRM2r:
 946   case X86Local::MRM3r:
 947   case X86Local::MRM4r:
 948   case X86Local::MRM5r:
 949   case X86Local::MRM6r:
 950   case X86Local::MRM7r:
 951     filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r);
 952     break;
 953   case X86Local::MRM0X:
 954   case X86Local::MRM1X:
 955   case X86Local::MRM2X:
 956   case X86Local::MRM3X:
 957   case X86Local::MRM4X:
 958   case X86Local::MRM5X:
 959   case X86Local::MRM6X:
 960   case X86Local::MRM7X:
 961     filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X);
 962     break;
 963   case X86Local::MRMr0:
 964     filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0);
 965     break;
 966   case X86Local::MRM0m:
 967   case X86Local::MRM1m:
 968   case X86Local::MRM2m:
 969   case X86Local::MRM3m:
 970   case X86Local::MRM4m:
 971   case X86Local::MRM5m:
 972   case X86Local::MRM6m:
 973   case X86Local::MRM7m:
 974     filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m);
 975     break;
 976     X86_INSTR_MRM_MAPPING
 977     filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0);
 978     break;
 979   } // switch (Form)
 980
 981   uint8_t opcodeToSet = Opcode;
 982
 983   unsigned AddressSize = 0;
 984   switch (AdSize) {
 985   case X86Local::AdSize16:
 986     AddressSize = 16;
 987     break;
 988   case X86Local::AdSize32:
 989     AddressSize = 32;
 990     break;
 991   case X86Local::AdSize64:
 992     AddressSize = 64;
 993     break;
 994   }
 995
 996   assert(opcodeType && "Opcode type not set");
 997   assert(filter && "Filter not set");
 998
 999   if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC ||
1000       Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC ||
1001       Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm ||
1002       Form == X86Local::MRMDestRegCC || Form == X86Local::MRMDestMemCC ||
1003       Form == X86Local::MRMDestMem4VOp3CC) {
1004     uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16;
1005     assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned");
1006
1007     uint8_t currentOpcode;
1008
1009     for (currentOpcode = opcodeToSet;
1010          currentOpcode < (uint8_t)(opcodeToSet + Count); ++currentOpcode)
1011       tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter,
1012                             UID, Is32Bit, OpPrefix == 0,
1013                             IgnoresVEX_L || EncodeRC, IgnoresW, AddressSize);
1014   } else {
1015     tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID,
1016                           Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC,
1017                           IgnoresW, AddressSize);
1018   }
1019
1020 #undef MAP
1021 }
1022
1023 #define TYPE(str, type)                                                        \
1024   if (s == str)                                                                \
1025     return type;
1026 OperandType RecognizableInstr::typeFromString(const std::string &s,
1027                                               bool hasREX_W, uint8_t OpSize) {
1028   if (hasREX_W) {
1029     // For instructions with a REX_W prefix, a declared 32-bit register encoding
1030     // is special.
1031     TYPE("GR32", TYPE_R32)
1032   }
1033   if (OpSize == X86Local::OpSize16) {
1034     // For OpSize16 instructions, a declared 16-bit register or
1035     // immediate encoding is special.
1036     TYPE("GR16", TYPE_Rv)
1037   } else if (OpSize == X86Local::OpSize32) {
1038     // For OpSize32 instructions, a declared 32-bit register or
1039     // immediate encoding is special.
1040     TYPE("GR32", TYPE_Rv)
1041   }
1042   TYPE("i16mem", TYPE_M)
1043   TYPE("i16imm", TYPE_IMM)
1044   TYPE("i16i8imm", TYPE_IMM)
1045   TYPE("GR16", TYPE_R16)
1046   TYPE("GR16orGR32orGR64", TYPE_R16)
1047   TYPE("i32mem", TYPE_M)
1048   TYPE("i32imm", TYPE_IMM)
1049   TYPE("i32i8imm", TYPE_IMM)
1050   TYPE("GR32", TYPE_R32)
1051   TYPE("GR32orGR64", TYPE_R32)
1052   TYPE("i64mem", TYPE_M)
1053   TYPE("i64i32imm", TYPE_IMM)
1054   TYPE("i64i8imm", TYPE_IMM)
1055   TYPE("GR64", TYPE_R64)
1056   TYPE("i8mem", TYPE_M)
1057   TYPE("i8imm", TYPE_IMM)
1058   TYPE("u4imm", TYPE_UIMM8)
1059   TYPE("u8imm", TYPE_UIMM8)
1060   TYPE("i16u8imm", TYPE_UIMM8)
1061   TYPE("i32u8imm", TYPE_UIMM8)
1062   TYPE("i64u8imm", TYPE_UIMM8)
1063   TYPE("GR8", TYPE_R8)
1064   TYPE("VR128", TYPE_XMM)
1065   TYPE("VR128X", TYPE_XMM)
1066   TYPE("f128mem", TYPE_M)
1067   TYPE("f256mem", TYPE_M)
1068   TYPE("f512mem", TYPE_M)
1069   TYPE("FR128", TYPE_XMM)
1070   TYPE("FR64", TYPE_XMM)
1071   TYPE("FR64X", TYPE_XMM)
1072   TYPE("f64mem", TYPE_M)
1073   TYPE("sdmem", TYPE_M)
1074   TYPE("FR16X", TYPE_XMM)
1075   TYPE("FR32", TYPE_XMM)
1076   TYPE("FR32X", TYPE_XMM)
1077   TYPE("f32mem", TYPE_M)
1078   TYPE("f16mem", TYPE_M)
1079   TYPE("ssmem", TYPE_M)
1080   TYPE("shmem", TYPE_M)
1081   TYPE("RST", TYPE_ST)
1082   TYPE("RSTi", TYPE_ST)
1083   TYPE("i128mem", TYPE_M)
1084   TYPE("i256mem", TYPE_M)
1085   TYPE("i512mem", TYPE_M)
1086   TYPE("i512mem_GR16", TYPE_M)
1087   TYPE("i512mem_GR32", TYPE_M)
1088   TYPE("i512mem_GR64", TYPE_M)
1089   TYPE("i64i32imm_brtarget", TYPE_REL)
1090   TYPE("i16imm_brtarget", TYPE_REL)
1091   TYPE("i32imm_brtarget", TYPE_REL)
1092   TYPE("ccode", TYPE_IMM)
1093   TYPE("cflags", TYPE_IMM)
1094   TYPE("AVX512RC", TYPE_IMM)
1095   TYPE("brtarget32", TYPE_REL)
1096   TYPE("brtarget16", TYPE_REL)
1097   TYPE("brtarget8", TYPE_REL)
1098   TYPE("f80mem", TYPE_M)
1099   TYPE("lea64_32mem", TYPE_M)
1100   TYPE("lea64mem", TYPE_M)
1101   TYPE("VR64", TYPE_MM64)
1102   TYPE("i64imm", TYPE_IMM)
1103   TYPE("anymem", TYPE_M)
1104   TYPE("opaquemem", TYPE_M)
1105   TYPE("sibmem", TYPE_MSIB)
1106   TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1107   TYPE("DEBUG_REG", TYPE_DEBUGREG)
1108   TYPE("CONTROL_REG", TYPE_CONTROLREG)
1109   TYPE("srcidx8", TYPE_SRCIDX)
1110   TYPE("srcidx16", TYPE_SRCIDX)
1111   TYPE("srcidx32", TYPE_SRCIDX)
1112   TYPE("srcidx64", TYPE_SRCIDX)
1113   TYPE("dstidx8", TYPE_DSTIDX)
1114   TYPE("dstidx16", TYPE_DSTIDX)
1115   TYPE("dstidx32", TYPE_DSTIDX)
1116   TYPE("dstidx64", TYPE_DSTIDX)
1117   TYPE("offset16_8", TYPE_MOFFS)
1118   TYPE("offset16_16", TYPE_MOFFS)
1119   TYPE("offset16_32", TYPE_MOFFS)
1120   TYPE("offset32_8", TYPE_MOFFS)
1121   TYPE("offset32_16", TYPE_MOFFS)
1122   TYPE("offset32_32", TYPE_MOFFS)
1123   TYPE("offset32_64", TYPE_MOFFS)
1124   TYPE("offset64_8", TYPE_MOFFS)
1125   TYPE("offset64_16", TYPE_MOFFS)
1126   TYPE("offset64_32", TYPE_MOFFS)
1127   TYPE("offset64_64", TYPE_MOFFS)
1128   TYPE("VR256", TYPE_YMM)
1129   TYPE("VR256X", TYPE_YMM)
1130   TYPE("VR512", TYPE_ZMM)
1131   TYPE("VK1", TYPE_VK)
1132   TYPE("VK1WM", TYPE_VK)
1133   TYPE("VK2", TYPE_VK)
1134   TYPE("VK2WM", TYPE_VK)
1135   TYPE("VK4", TYPE_VK)
1136   TYPE("VK4WM", TYPE_VK)
1137   TYPE("VK8", TYPE_VK)
1138   TYPE("VK8WM", TYPE_VK)
1139   TYPE("VK16", TYPE_VK)
1140   TYPE("VK16WM", TYPE_VK)
1141   TYPE("VK32", TYPE_VK)
1142   TYPE("VK32WM", TYPE_VK)
1143   TYPE("VK64", TYPE_VK)
1144   TYPE("VK64WM", TYPE_VK)
1145   TYPE("VK1Pair", TYPE_VK_PAIR)
1146   TYPE("VK2Pair", TYPE_VK_PAIR)
1147   TYPE("VK4Pair", TYPE_VK_PAIR)
1148   TYPE("VK8Pair", TYPE_VK_PAIR)
1149   TYPE("VK16Pair", TYPE_VK_PAIR)
1150   TYPE("vx64mem", TYPE_MVSIBX)
1151   TYPE("vx128mem", TYPE_MVSIBX)
1152   TYPE("vx256mem", TYPE_MVSIBX)
1153   TYPE("vy128mem", TYPE_MVSIBY)
1154   TYPE("vy256mem", TYPE_MVSIBY)
1155   TYPE("vx64xmem", TYPE_MVSIBX)
1156   TYPE("vx128xmem", TYPE_MVSIBX)
1157   TYPE("vx256xmem", TYPE_MVSIBX)
1158   TYPE("vy128xmem", TYPE_MVSIBY)
1159   TYPE("vy256xmem", TYPE_MVSIBY)
1160   TYPE("vy512xmem", TYPE_MVSIBY)
1161   TYPE("vz256mem", TYPE_MVSIBZ)
1162   TYPE("vz512mem", TYPE_MVSIBZ)
1163   TYPE("BNDR", TYPE_BNDR)
1164   TYPE("TILE", TYPE_TMM)
1165   TYPE("TILEPair", TYPE_TMM_PAIR)
1166   errs() << "Unhandled type string " << s << "\n";
1167   llvm_unreachable("Unhandled type string");
1168 }
1169 #undef TYPE
1170
1171 #define ENCODING(str, encoding)                                                \
1172   if (s == str)                                                                \
1173     return encoding;
1174 OperandEncoding
1175 RecognizableInstr::immediateEncodingFromString(const std::string &s,
1176                                                uint8_t OpSize) {
1177   if (OpSize != X86Local::OpSize16) {
1178     // For instructions without an OpSize prefix, a declared 16-bit register or
1179     // immediate encoding is special.
1180     ENCODING("i16imm", ENCODING_IW)
1181   }
1182   ENCODING("i32i8imm", ENCODING_IB)
1183   ENCODING("AVX512RC", ENCODING_IRC)
1184   ENCODING("i16imm", ENCODING_Iv)
1185   ENCODING("i16i8imm", ENCODING_IB)
1186   ENCODING("i32imm", ENCODING_Iv)
1187   ENCODING("i64i32imm", ENCODING_ID)
1188   ENCODING("i64i8imm", ENCODING_IB)
1189   ENCODING("i8imm", ENCODING_IB)
1190   ENCODING("ccode", ENCODING_CC)
1191   ENCODING("cflags", ENCODING_CF)
1192   ENCODING("u4imm", ENCODING_IB)
1193   ENCODING("u8imm", ENCODING_IB)
1194   ENCODING("i16u8imm", ENCODING_IB)
1195   ENCODING("i32u8imm", ENCODING_IB)
1196   ENCODING("i64u8imm", ENCODING_IB)
1197   // This is not a typo.  Instructions like BLENDVPD put
1198   // register IDs in 8-bit immediates nowadays.
1199   ENCODING("FR32", ENCODING_IB)
1200   ENCODING("FR64", ENCODING_IB)
1201   ENCODING("FR128", ENCODING_IB)
1202   ENCODING("VR128", ENCODING_IB)
1203   ENCODING("VR256", ENCODING_IB)
1204   ENCODING("FR16X", ENCODING_IB)
1205   ENCODING("FR32X", ENCODING_IB)
1206   ENCODING("FR64X", ENCODING_IB)
1207   ENCODING("VR128X", ENCODING_IB)
1208   ENCODING("VR256X", ENCODING_IB)
1209   ENCODING("VR512", ENCODING_IB)
1210   ENCODING("TILE", ENCODING_IB)
1211   errs() << "Unhandled immediate encoding " << s << "\n";
1212   llvm_unreachable("Unhandled immediate encoding");
1213 }
1214
1215 OperandEncoding
1216 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1217                                                 uint8_t OpSize) {
1218   ENCODING("RST", ENCODING_FP)
1219   ENCODING("RSTi", ENCODING_FP)
1220   ENCODING("GR16", ENCODING_RM)
1221   ENCODING("GR16orGR32orGR64", ENCODING_RM)
1222   ENCODING("GR32", ENCODING_RM)
1223   ENCODING("GR32orGR64", ENCODING_RM)
1224   ENCODING("GR64", ENCODING_RM)
1225   ENCODING("GR8", ENCODING_RM)
1226   ENCODING("VR128", ENCODING_RM)
1227   ENCODING("VR128X", ENCODING_RM)
1228   ENCODING("FR128", ENCODING_RM)
1229   ENCODING("FR64", ENCODING_RM)
1230   ENCODING("FR32", ENCODING_RM)
1231   ENCODING("FR64X", ENCODING_RM)
1232   ENCODING("FR32X", ENCODING_RM)
1233   ENCODING("FR16X", ENCODING_RM)
1234   ENCODING("VR64", ENCODING_RM)
1235   ENCODING("VR256", ENCODING_RM)
1236   ENCODING("VR256X", ENCODING_RM)
1237   ENCODING("VR512", ENCODING_RM)
1238   ENCODING("VK1", ENCODING_RM)
1239   ENCODING("VK2", ENCODING_RM)
1240   ENCODING("VK4", ENCODING_RM)
1241   ENCODING("VK8", ENCODING_RM)
1242   ENCODING("VK16", ENCODING_RM)
1243   ENCODING("VK32", ENCODING_RM)
1244   ENCODING("VK64", ENCODING_RM)
1245   ENCODING("BNDR", ENCODING_RM)
1246   ENCODING("TILE", ENCODING_RM)
1247   ENCODING("TILEPair", ENCODING_RM)
1248   errs() << "Unhandled R/M register encoding " << s << "\n";
1249   llvm_unreachable("Unhandled R/M register encoding");
1250 }
1251
1252 OperandEncoding
1253 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1254                                                 uint8_t OpSize) {
1255   ENCODING("GR16", ENCODING_REG)
1256   ENCODING("GR16orGR32orGR64", ENCODING_REG)
1257   ENCODING("GR32", ENCODING_REG)
1258   ENCODING("GR32orGR64", ENCODING_REG)
1259   ENCODING("GR64", ENCODING_REG)
1260   ENCODING("GR8", ENCODING_REG)
1261   ENCODING("VR128", ENCODING_REG)
1262   ENCODING("FR128", ENCODING_REG)
1263   ENCODING("FR64", ENCODING_REG)
1264   ENCODING("FR32", ENCODING_REG)
1265   ENCODING("VR64", ENCODING_REG)
1266   ENCODING("SEGMENT_REG", ENCODING_REG)
1267   ENCODING("DEBUG_REG", ENCODING_REG)
1268   ENCODING("CONTROL_REG", ENCODING_REG)
1269   ENCODING("VR256", ENCODING_REG)
1270   ENCODING("VR256X", ENCODING_REG)
1271   ENCODING("VR128X", ENCODING_REG)
1272   ENCODING("FR64X", ENCODING_REG)
1273   ENCODING("FR32X", ENCODING_REG)
1274   ENCODING("FR16X", ENCODING_REG)
1275   ENCODING("VR512", ENCODING_REG)
1276   ENCODING("VK1", ENCODING_REG)
1277   ENCODING("VK2", ENCODING_REG)
1278   ENCODING("VK4", ENCODING_REG)
1279   ENCODING("VK8", ENCODING_REG)
1280   ENCODING("VK16", ENCODING_REG)
1281   ENCODING("VK32", ENCODING_REG)
1282   ENCODING("VK64", ENCODING_REG)
1283   ENCODING("VK1Pair", ENCODING_REG)
1284   ENCODING("VK2Pair", ENCODING_REG)
1285   ENCODING("VK4Pair", ENCODING_REG)
1286   ENCODING("VK8Pair", ENCODING_REG)
1287   ENCODING("VK16Pair", ENCODING_REG)
1288   ENCODING("VK1WM", ENCODING_REG)
1289   ENCODING("VK2WM", ENCODING_REG)
1290   ENCODING("VK4WM", ENCODING_REG)
1291   ENCODING("VK8WM", ENCODING_REG)
1292   ENCODING("VK16WM", ENCODING_REG)
1293   ENCODING("VK32WM", ENCODING_REG)
1294   ENCODING("VK64WM", ENCODING_REG)
1295   ENCODING("BNDR", ENCODING_REG)
1296   ENCODING("TILE", ENCODING_REG)
1297   ENCODING("TILEPair", ENCODING_REG)
1298   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1299   llvm_unreachable("Unhandled reg/opcode register encoding");
1300 }
1301
1302 OperandEncoding
1303 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1304                                                   uint8_t OpSize) {
1305   ENCODING("GR8", ENCODING_VVVV)
1306   ENCODING("GR16", ENCODING_VVVV)
1307   ENCODING("GR32", ENCODING_VVVV)
1308   ENCODING("GR64", ENCODING_VVVV)
1309   ENCODING("FR32", ENCODING_VVVV)
1310   ENCODING("FR128", ENCODING_VVVV)
1311   ENCODING("FR64", ENCODING_VVVV)
1312   ENCODING("VR128", ENCODING_VVVV)
1313   ENCODING("VR256", ENCODING_VVVV)
1314   ENCODING("FR16X", ENCODING_VVVV)
1315   ENCODING("FR32X", ENCODING_VVVV)
1316   ENCODING("FR64X", ENCODING_VVVV)
1317   ENCODING("VR128X", ENCODING_VVVV)
1318   ENCODING("VR256X", ENCODING_VVVV)
1319   ENCODING("VR512", ENCODING_VVVV)
1320   ENCODING("VK1", ENCODING_VVVV)
1321   ENCODING("VK2", ENCODING_VVVV)
1322   ENCODING("VK4", ENCODING_VVVV)
1323   ENCODING("VK8", ENCODING_VVVV)
1324   ENCODING("VK16", ENCODING_VVVV)
1325   ENCODING("VK32", ENCODING_VVVV)
1326   ENCODING("VK64", ENCODING_VVVV)
1327   ENCODING("TILE", ENCODING_VVVV)
1328   ENCODING("TILEPair", ENCODING_VVVV)
1329   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1330   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1331 }
1332
1333 OperandEncoding
1334 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1335                                                        uint8_t OpSize) {
1336   ENCODING("VK1WM", ENCODING_WRITEMASK)
1337   ENCODING("VK2WM", ENCODING_WRITEMASK)
1338   ENCODING("VK4WM", ENCODING_WRITEMASK)
1339   ENCODING("VK8WM", ENCODING_WRITEMASK)
1340   ENCODING("VK16WM", ENCODING_WRITEMASK)
1341   ENCODING("VK32WM", ENCODING_WRITEMASK)
1342   ENCODING("VK64WM", ENCODING_WRITEMASK)
1343   errs() << "Unhandled mask register encoding " << s << "\n";
1344   llvm_unreachable("Unhandled mask register encoding");
1345 }
1346
1347 OperandEncoding
1348 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1349                                             uint8_t OpSize) {
1350   ENCODING("i16mem", ENCODING_RM)
1351   ENCODING("i32mem", ENCODING_RM)
1352   ENCODING("i64mem", ENCODING_RM)
1353   ENCODING("i8mem", ENCODING_RM)
1354   ENCODING("shmem", ENCODING_RM)
1355   ENCODING("ssmem", ENCODING_RM)
1356   ENCODING("sdmem", ENCODING_RM)
1357   ENCODING("f128mem", ENCODING_RM)
1358   ENCODING("f256mem", ENCODING_RM)
1359   ENCODING("f512mem", ENCODING_RM)
1360   ENCODING("f64mem", ENCODING_RM)
1361   ENCODING("f32mem", ENCODING_RM)
1362   ENCODING("f16mem", ENCODING_RM)
1363   ENCODING("i128mem", ENCODING_RM)
1364   ENCODING("i256mem", ENCODING_RM)
1365   ENCODING("i512mem", ENCODING_RM)
1366   ENCODING("i512mem_GR16", ENCODING_RM)
1367   ENCODING("i512mem_GR32", ENCODING_RM)
1368   ENCODING("i512mem_GR64", ENCODING_RM)
1369   ENCODING("f80mem", ENCODING_RM)
1370   ENCODING("lea64_32mem", ENCODING_RM)
1371   ENCODING("lea64mem", ENCODING_RM)
1372   ENCODING("anymem", ENCODING_RM)
1373   ENCODING("opaquemem", ENCODING_RM)
1374   ENCODING("sibmem", ENCODING_SIB)
1375   ENCODING("vx64mem", ENCODING_VSIB)
1376   ENCODING("vx128mem", ENCODING_VSIB)
1377   ENCODING("vx256mem", ENCODING_VSIB)
1378   ENCODING("vy128mem", ENCODING_VSIB)
1379   ENCODING("vy256mem", ENCODING_VSIB)
1380   ENCODING("vx64xmem", ENCODING_VSIB)
1381   ENCODING("vx128xmem", ENCODING_VSIB)
1382   ENCODING("vx256xmem", ENCODING_VSIB)
1383   ENCODING("vy128xmem", ENCODING_VSIB)
1384   ENCODING("vy256xmem", ENCODING_VSIB)
1385   ENCODING("vy512xmem", ENCODING_VSIB)
1386   ENCODING("vz256mem", ENCODING_VSIB)
1387   ENCODING("vz512mem", ENCODING_VSIB)
1388   errs() << "Unhandled memory encoding " << s << "\n";
1389   llvm_unreachable("Unhandled memory encoding");
1390 }
1391
1392 OperandEncoding
1393 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1394                                                 uint8_t OpSize) {
1395   if (OpSize != X86Local::OpSize16) {
1396     // For instructions without an OpSize prefix, a declared 16-bit register or
1397     // immediate encoding is special.
1398     ENCODING("i16imm", ENCODING_IW)
1399   }
1400   ENCODING("i16imm", ENCODING_Iv)
1401   ENCODING("i16i8imm", ENCODING_IB)
1402   ENCODING("i32imm", ENCODING_Iv)
1403   ENCODING("i32i8imm", ENCODING_IB)
1404   ENCODING("i64i32imm", ENCODING_ID)
1405   ENCODING("i64i8imm", ENCODING_IB)
1406   ENCODING("i8imm", ENCODING_IB)
1407   ENCODING("u8imm", ENCODING_IB)
1408   ENCODING("i16u8imm", ENCODING_IB)
1409   ENCODING("i32u8imm", ENCODING_IB)
1410   ENCODING("i64u8imm", ENCODING_IB)
1411   ENCODING("i64i32imm_brtarget", ENCODING_ID)
1412   ENCODING("i16imm_brtarget", ENCODING_IW)
1413   ENCODING("i32imm_brtarget", ENCODING_ID)
1414   ENCODING("brtarget32", ENCODING_ID)
1415   ENCODING("brtarget16", ENCODING_IW)
1416   ENCODING("brtarget8", ENCODING_IB)
1417   ENCODING("i64imm", ENCODING_IO)
1418   ENCODING("offset16_8", ENCODING_Ia)
1419   ENCODING("offset16_16", ENCODING_Ia)
1420   ENCODING("offset16_32", ENCODING_Ia)
1421   ENCODING("offset32_8", ENCODING_Ia)
1422   ENCODING("offset32_16", ENCODING_Ia)
1423   ENCODING("offset32_32", ENCODING_Ia)
1424   ENCODING("offset32_64", ENCODING_Ia)
1425   ENCODING("offset64_8", ENCODING_Ia)
1426   ENCODING("offset64_16", ENCODING_Ia)
1427   ENCODING("offset64_32", ENCODING_Ia)
1428   ENCODING("offset64_64", ENCODING_Ia)
1429   ENCODING("srcidx8", ENCODING_SI)
1430   ENCODING("srcidx16", ENCODING_SI)
1431   ENCODING("srcidx32", ENCODING_SI)
1432   ENCODING("srcidx64", ENCODING_SI)
1433   ENCODING("dstidx8", ENCODING_DI)
1434   ENCODING("dstidx16", ENCODING_DI)
1435   ENCODING("dstidx32", ENCODING_DI)
1436   ENCODING("dstidx64", ENCODING_DI)
1437   errs() << "Unhandled relocation encoding " << s << "\n";
1438   llvm_unreachable("Unhandled relocation encoding");
1439 }
1440
1441 OperandEncoding
1442 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1443                                                     uint8_t OpSize) {
1444   ENCODING("GR32", ENCODING_Rv)
1445   ENCODING("GR64", ENCODING_RO)
1446   ENCODING("GR16", ENCODING_Rv)
1447   ENCODING("GR8", ENCODING_RB)
1448   ENCODING("ccode", ENCODING_CC)
1449   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1450   llvm_unreachable("Unhandled opcode modifier encoding");
1451 }
1452 #undef ENCODING