| blob | 595991e86a91c70fee565d2b1223f7909ccd0002 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
4 define i1 @test_srem_odd(i29 %X) nounwind {
5 ; CHECK-LABEL: test_srem_odd:
6 ; CHECK: // %bb.0:
7 ; CHECK-NEXT: mov w8, #33099 // =0x814b
8 ; CHECK-NEXT: mov w9, #24493 // =0x5fad
9 ; CHECK-NEXT: movk w8, #8026, lsl #16
10 ; CHECK-NEXT: movk w9, #41, lsl #16
11 ; CHECK-NEXT: madd w8, w0, w8, w9
12 ; CHECK-NEXT: mov w9, #48987 // =0xbf5b
13 ; CHECK-NEXT: movk w9, #82, lsl #16
14 ; CHECK-NEXT: and w8, w8, #0x1fffffff
15 ; CHECK-NEXT: cmp w8, w9
16 ; CHECK-NEXT: cset w0, lo
17 ; CHECK-NEXT: ret
18 %srem = srem i29 %X, 99
19 %cmp = icmp eq i29 %srem, 0
20 ret i1 %cmp
21 }
23 define i1 @test_srem_even(i4 %X) nounwind {
24 ; CHECK-LABEL: test_srem_even:
25 ; CHECK: // %bb.0:
26 ; CHECK-NEXT: sbfx w8, w0, #0, #4
27 ; CHECK-NEXT: add w8, w8, w8, lsl #1
28 ; CHECK-NEXT: ubfx w9, w8, #7, #1
29 ; CHECK-NEXT: add w8, w9, w8, lsr #4
30 ; CHECK-NEXT: mov w9, #6 // =0x6
31 ; CHECK-NEXT: msub w8, w8, w9, w0
32 ; CHECK-NEXT: and w8, w8, #0xf
33 ; CHECK-NEXT: cmp w8, #1
34 ; CHECK-NEXT: cset w0, eq
35 ; CHECK-NEXT: ret
36 %srem = srem i4 %X, 6
37 %cmp = icmp eq i4 %srem, 1
38 ret i1 %cmp
39 }
41 define i1 @test_srem_pow2_setne(i6 %X) nounwind {
42 ; CHECK-LABEL: test_srem_pow2_setne:
43 ; CHECK: // %bb.0:
44 ; CHECK-NEXT: sbfx w8, w0, #0, #6
45 ; CHECK-NEXT: ubfx w8, w8, #9, #2
46 ; CHECK-NEXT: add w8, w0, w8
47 ; CHECK-NEXT: and w8, w8, #0x3c
48 ; CHECK-NEXT: sub w8, w0, w8
49 ; CHECK-NEXT: tst w8, #0x3f
50 ; CHECK-NEXT: cset w0, ne
51 ; CHECK-NEXT: ret
52 %srem = srem i6 %X, 4
53 %cmp = icmp ne i6 %srem, 0
54 ret i1 %cmp
55 }
57 define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
58 ; CHECK-LABEL: test_srem_vec:
59 ; CHECK: // %bb.0:
60 ; CHECK-NEXT: mov x9, #7282 // =0x1c72
61 ; CHECK-NEXT: sbfx x8, x0, #0, #33
62 ; CHECK-NEXT: sbfx x10, x1, #0, #33
63 ; CHECK-NEXT: movk x9, #29127, lsl #16
64 ; CHECK-NEXT: mov x13, #7281 // =0x1c71
65 ; CHECK-NEXT: sbfx x12, x2, #0, #33
66 ; CHECK-NEXT: movk x9, #50972, lsl #32
67 ; CHECK-NEXT: movk x13, #29127, lsl #16
68 ; CHECK-NEXT: movk x9, #7281, lsl #48
69 ; CHECK-NEXT: movk x13, #50972, lsl #32
70 ; CHECK-NEXT: smulh x11, x8, x9
71 ; CHECK-NEXT: movk x13, #7281, lsl #48
72 ; CHECK-NEXT: smulh x9, x10, x9
73 ; CHECK-NEXT: smulh x13, x12, x13
74 ; CHECK-NEXT: add x11, x11, x11, lsr #63
75 ; CHECK-NEXT: add x9, x9, x9, lsr #63
76 ; CHECK-NEXT: add x11, x11, x11, lsl #3
77 ; CHECK-NEXT: add x9, x9, x9, lsl #3
78 ; CHECK-NEXT: sub x8, x8, x11
79 ; CHECK-NEXT: sub x11, x13, x12
80 ; CHECK-NEXT: fmov d0, x8
81 ; CHECK-NEXT: mov x8, #8589934591 // =0x1ffffffff
82 ; CHECK-NEXT: sub x9, x10, x9
83 ; CHECK-NEXT: asr x10, x11, #3
84 ; CHECK-NEXT: dup v1.2d, x8
85 ; CHECK-NEXT: mov v0.d[1], x9
86 ; CHECK-NEXT: add x9, x10, x11, lsr #63
87 ; CHECK-NEXT: add x8, x9, x9, lsl #3
88 ; CHECK-NEXT: adrp x9, .LCPI3_0
89 ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI3_0]
90 ; CHECK-NEXT: add x8, x12, x8
91 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
92 ; CHECK-NEXT: fmov d3, x8
93 ; CHECK-NEXT: adrp x8, .LCPI3_1
94 ; CHECK-NEXT: cmeq v0.2d, v0.2d, v2.2d
95 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_1]
96 ; CHECK-NEXT: and v1.16b, v3.16b, v1.16b
97 ; CHECK-NEXT: mvn v0.16b, v0.16b
98 ; CHECK-NEXT: cmeq v1.2d, v1.2d, v2.2d
99 ; CHECK-NEXT: xtn v0.2s, v0.2d
100 ; CHECK-NEXT: mvn v1.16b, v1.16b
101 ; CHECK-NEXT: xtn v1.2s, v1.2d
102 ; CHECK-NEXT: mov w1, v0.s[1]
103 ; CHECK-NEXT: fmov w0, s0
104 ; CHECK-NEXT: fmov w2, s1
105 ; CHECK-NEXT: ret
106 %srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9>
107 %cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3>
108 ret <3 x i1> %cmp
109 }