| blob | b05b46a75b698dc69573089f50aa29e97511358e |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s | FileCheck %s --check-prefixes=CHECK
4 ; Should codegen to a nop, since idx is zero.
5 define <2 x i64> @extract_v2i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind {
6 ; CHECK-LABEL: extract_v2i64_nxv2i64:
7 ; CHECK: // %bb.0:
8 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
9 ; CHECK-NEXT: ret
10 %retval = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 0)
11 ret <2 x i64> %retval
12 }
14 ; Goes through memory currently; idx != 0.
15 define <2 x i64> @extract_v2i64_nxv2i64_idx2(<vscale x 2 x i64> %vec) nounwind {
16 ; CHECK-LABEL: extract_v2i64_nxv2i64_idx2:
17 ; CHECK: // %bb.0:
18 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16
19 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
20 ; CHECK-NEXT: ret
21 %retval = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 2)
22 ret <2 x i64> %retval
23 }
25 ; Should codegen to a nop, since idx is zero.
26 define <4 x i32> @extract_v4i32_nxv4i32(<vscale x 4 x i32> %vec) nounwind {
27 ; CHECK-LABEL: extract_v4i32_nxv4i32:
28 ; CHECK: // %bb.0:
29 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
30 ; CHECK-NEXT: ret
31 %retval = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0)
32 ret <4 x i32> %retval
33 }
35 ; Goes through memory currently; idx != 0.
36 define <4 x i32> @extract_v4i32_nxv4i32_idx4(<vscale x 4 x i32> %vec) nounwind {
37 ; CHECK-LABEL: extract_v4i32_nxv4i32_idx4:
38 ; CHECK: // %bb.0:
39 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16
40 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
41 ; CHECK-NEXT: ret
42 %retval = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 4)
43 ret <4 x i32> %retval
44 }
46 ; Should codegen to uzps, since idx is zero and type is illegal.
47 define <4 x i32> @extract_v4i32_nxv2i32(<vscale x 2 x i32> %vec) nounwind #1 {
48 ; CHECK-LABEL: extract_v4i32_nxv2i32:
49 ; CHECK: // %bb.0:
50 ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
51 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
52 ; CHECK-NEXT: ret
53 %retval = call <4 x i32> @llvm.vector.extract.v4i32.nxv2i32(<vscale x 2 x i32> %vec, i64 0)
54 ret <4 x i32> %retval
55 }
57 ; Goes through memory currently; idx != 0.
58 define <4 x i32> @extract_v4i32_nxv2i32_idx4(<vscale x 2 x i32> %vec) nounwind #1 {
59 ; CHECK-LABEL: extract_v4i32_nxv2i32_idx4:
60 ; CHECK: // %bb.0:
61 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #32
62 ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
63 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
64 ; CHECK-NEXT: ret
65 %retval = call <4 x i32> @llvm.vector.extract.v4i32.nxv2i32(<vscale x 2 x i32> %vec, i64 4)
66 ret <4 x i32> %retval
67 }
69 ; Should codegen to a nop, since idx is zero.
70 define <8 x i16> @extract_v8i16_nxv8i16(<vscale x 8 x i16> %vec) nounwind {
71 ; CHECK-LABEL: extract_v8i16_nxv8i16:
72 ; CHECK: // %bb.0:
73 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
74 ; CHECK-NEXT: ret
75 %retval = call <8 x i16> @llvm.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> %vec, i64 0)
76 ret <8 x i16> %retval
77 }
79 ; Goes through memory currently; idx != 0.
80 define <8 x i16> @extract_v8i16_nxv8i16_idx8(<vscale x 8 x i16> %vec) nounwind {
81 ; CHECK-LABEL: extract_v8i16_nxv8i16_idx8:
82 ; CHECK: // %bb.0:
83 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16
84 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
85 ; CHECK-NEXT: ret
86 %retval = call <8 x i16> @llvm.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> %vec, i64 8)
87 ret <8 x i16> %retval
88 }
90 ; Should codegen to uzps, since idx is zero and type is illegal.
91 define <8 x i16> @extract_v8i16_nxv4i16(<vscale x 4 x i16> %vec) nounwind #1 {
92 ; CHECK-LABEL: extract_v8i16_nxv4i16:
93 ; CHECK: // %bb.0:
94 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
95 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
96 ; CHECK-NEXT: ret
97 %retval = call <8 x i16> @llvm.vector.extract.v8i16.nxv4i16(<vscale x 4 x i16> %vec, i64 0)
98 ret <8 x i16> %retval
99 }
101 ; Goes through memory currently; idx != 0.
102 define <8 x i16> @extract_v8i16_nxv4i16_idx8(<vscale x 4 x i16> %vec) nounwind #1 {
103 ; CHECK-LABEL: extract_v8i16_nxv4i16_idx8:
104 ; CHECK: // %bb.0:
105 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #32
106 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
107 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
108 ; CHECK-NEXT: ret
109 %retval = call <8 x i16> @llvm.vector.extract.v8i16.nxv4i16(<vscale x 4 x i16> %vec, i64 8)
110 ret <8 x i16> %retval
111 }
113 ; Should codegen to uzps, since idx is zero and type is illegal.
114 define <8 x i16> @extract_v8i16_nxv2i16(<vscale x 2 x i16> %vec) nounwind #1 {
115 ; CHECK-LABEL: extract_v8i16_nxv2i16:
116 ; CHECK: // %bb.0:
117 ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
118 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
119 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
120 ; CHECK-NEXT: ret
121 %retval = call <8 x i16> @llvm.vector.extract.v8i16.nxv2i16(<vscale x 2 x i16> %vec, i64 0)
122 ret <8 x i16> %retval
123 }
125 ; Goes through memory currently; idx != 0.
126 define <8 x i16> @extract_v8i16_nxv2i16_idx8(<vscale x 2 x i16> %vec) nounwind #1 {
127 ; CHECK-LABEL: extract_v8i16_nxv2i16_idx8:
128 ; CHECK: // %bb.0:
129 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64
130 ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
131 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
132 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
133 ; CHECK-NEXT: ret
134 %retval = call <8 x i16> @llvm.vector.extract.v8i16.nxv2i16(<vscale x 2 x i16> %vec, i64 8)
135 ret <8 x i16> %retval
136 }
138 ; Should codegen to a nop, since idx is zero.
139 define <16 x i8> @extract_v16i8_nxv16i8(<vscale x 16 x i8> %vec) nounwind {
140 ; CHECK-LABEL: extract_v16i8_nxv16i8:
141 ; CHECK: // %bb.0:
142 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
143 ; CHECK-NEXT: ret
144 %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> %vec, i64 0)
145 ret <16 x i8> %retval
146 }
148 ; Goes through memory currently; idx != 0.
149 define <16 x i8> @extract_v16i8_nxv16i8_idx16(<vscale x 16 x i8> %vec) nounwind {
150 ; CHECK-LABEL: extract_v16i8_nxv16i8_idx16:
151 ; CHECK: // %bb.0:
152 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16
153 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
154 ; CHECK-NEXT: ret
155 %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> %vec, i64 16)
156 ret <16 x i8> %retval
157 }
159 ; Should codegen to uzps, since idx is zero and type is illegal.
160 define <16 x i8> @extract_v16i8_nxv8i8(<vscale x 8 x i8> %vec) nounwind #1 {
161 ; CHECK-LABEL: extract_v16i8_nxv8i8:
162 ; CHECK: // %bb.0:
163 ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
164 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
165 ; CHECK-NEXT: ret
166 %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8> %vec, i64 0)
167 ret <16 x i8> %retval
168 }
170 ; Goes through memory currently; idx != 0.
171 define <16 x i8> @extract_v16i8_nxv8i8_idx16(<vscale x 8 x i8> %vec) nounwind #1 {
172 ; CHECK-LABEL: extract_v16i8_nxv8i8_idx16:
173 ; CHECK: // %bb.0:
174 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #32
175 ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
176 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
177 ; CHECK-NEXT: ret
178 %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8> %vec, i64 16)
179 ret <16 x i8> %retval
180 }
182 ; Should codegen to uzps, since idx is zero and type is illegal.
183 define <16 x i8> @extract_v16i8_nxv4i8(<vscale x 4 x i8> %vec) nounwind #1 {
184 ; CHECK-LABEL: extract_v16i8_nxv4i8:
185 ; CHECK: // %bb.0:
186 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
187 ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
188 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
189 ; CHECK-NEXT: ret
190 %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv4i8(<vscale x 4 x i8> %vec, i64 0)
191 ret <16 x i8> %retval
192 }
194 ; Goes through memory currently; idx != 0.
195 define <16 x i8> @extract_v16i8_nxv4i8_idx16(<vscale x 4 x i8> %vec) nounwind #1 {
196 ; CHECK-LABEL: extract_v16i8_nxv4i8_idx16:
197 ; CHECK: // %bb.0:
198 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #64
199 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
200 ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
201 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
202 ; CHECK-NEXT: ret
203 %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv4i8(<vscale x 4 x i8> %vec, i64 16)
204 ret <16 x i8> %retval
205 }
207 ; Should codegen to uzps, since idx is zero and type is illegal.
208 define <16 x i8> @extract_v16i8_nxv2i8(<vscale x 2 x i8> %vec) nounwind #1 {
209 ; CHECK-LABEL: extract_v16i8_nxv2i8:
210 ; CHECK: // %bb.0:
211 ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
212 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
213 ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
214 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
215 ; CHECK-NEXT: ret
216 %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv2i8(<vscale x 2 x i8> %vec, i64 0)
217 ret <16 x i8> %retval
218 }
220 ; Goes through memory currently; idx != 0.
221 define <16 x i8> @extract_v16i8_nxv2i8_idx16(<vscale x 2 x i8> %vec) nounwind #1 {
222 ; CHECK-LABEL: extract_v16i8_nxv2i8_idx16:
223 ; CHECK: // %bb.0:
224 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #128
225 ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
226 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
227 ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
228 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
229 ; CHECK-NEXT: ret
230 %retval = call <16 x i8> @llvm.vector.extract.v16i8.nxv2i8(<vscale x 2 x i8> %vec, i64 16)
231 ret <16 x i8> %retval
232 }
235 ; Predicates
237 define <2 x i1> @extract_v2i1_nxv2i1(<vscale x 2 x i1> %inmask) {
238 ; CHECK-LABEL: extract_v2i1_nxv2i1:
239 ; CHECK: // %bb.0:
240 ; CHECK-NEXT: mov z0.d, p0/z, #1 // =0x1
241 ; CHECK-NEXT: fmov x0, d0
242 ; CHECK-NEXT: mov x8, v0.d[1]
243 ; CHECK-NEXT: fmov s0, w0
244 ; CHECK-NEXT: mov v0.s[1], w8
245 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
246 ; CHECK-NEXT: ret
247 %mask = call <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %inmask, i64 0)
248 ret <2 x i1> %mask
249 }
251 define <4 x i1> @extract_v4i1_nxv4i1(<vscale x 4 x i1> %inmask) {
252 ; CHECK-LABEL: extract_v4i1_nxv4i1:
253 ; CHECK: // %bb.0:
254 ; CHECK-NEXT: mov z1.s, p0/z, #1 // =0x1
255 ; CHECK-NEXT: mov w8, v1.s[1]
256 ; CHECK-NEXT: mov v0.16b, v1.16b
257 ; CHECK-NEXT: mov w9, v1.s[2]
258 ; CHECK-NEXT: mov v0.h[1], w8
259 ; CHECK-NEXT: mov w8, v1.s[3]
260 ; CHECK-NEXT: mov v0.h[2], w9
261 ; CHECK-NEXT: mov v0.h[3], w8
262 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
263 ; CHECK-NEXT: ret
264 %mask = call <4 x i1> @llvm.vector.extract.v4i1.nxv4i1(<vscale x 4 x i1> %inmask, i64 0)
265 ret <4 x i1> %mask
266 }
268 define <8 x i1> @extract_v8i1_nxv8i1(<vscale x 8 x i1> %inmask) {
269 ; CHECK-LABEL: extract_v8i1_nxv8i1:
270 ; CHECK: // %bb.0:
271 ; CHECK-NEXT: mov z1.h, p0/z, #1 // =0x1
272 ; CHECK-NEXT: umov w8, v1.h[1]
273 ; CHECK-NEXT: mov v0.16b, v1.16b
274 ; CHECK-NEXT: umov w9, v1.h[2]
275 ; CHECK-NEXT: mov v0.b[1], w8
276 ; CHECK-NEXT: umov w8, v1.h[3]
277 ; CHECK-NEXT: mov v0.b[2], w9
278 ; CHECK-NEXT: umov w9, v1.h[4]
279 ; CHECK-NEXT: mov v0.b[3], w8
280 ; CHECK-NEXT: umov w8, v1.h[5]
281 ; CHECK-NEXT: mov v0.b[4], w9
282 ; CHECK-NEXT: umov w9, v1.h[6]
283 ; CHECK-NEXT: mov v0.b[5], w8
284 ; CHECK-NEXT: umov w8, v1.h[7]
285 ; CHECK-NEXT: mov v0.b[6], w9
286 ; CHECK-NEXT: mov v0.b[7], w8
287 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
288 ; CHECK-NEXT: ret
289 %mask = call <8 x i1> @llvm.vector.extract.v8i1.nxv8i1(<vscale x 8 x i1> %inmask, i64 0)
290 ret <8 x i1> %mask
291 }
293 define <16 x i1> @extract_v16i1_nxv16i1(<vscale x 16 x i1> %inmask) {
294 ; CHECK-LABEL: extract_v16i1_nxv16i1:
295 ; CHECK: // %bb.0:
296 ; CHECK-NEXT: mov z1.b, p0/z, #1 // =0x1
297 ; CHECK-NEXT: umov w8, v1.b[1]
298 ; CHECK-NEXT: mov v0.16b, v1.16b
299 ; CHECK-NEXT: umov w9, v1.b[2]
300 ; CHECK-NEXT: mov v0.b[1], w8
301 ; CHECK-NEXT: umov w8, v1.b[3]
302 ; CHECK-NEXT: mov v0.b[2], w9
303 ; CHECK-NEXT: umov w9, v1.b[4]
304 ; CHECK-NEXT: mov v0.b[3], w8
305 ; CHECK-NEXT: umov w8, v1.b[5]
306 ; CHECK-NEXT: mov v0.b[4], w9
307 ; CHECK-NEXT: umov w9, v1.b[6]
308 ; CHECK-NEXT: mov v0.b[5], w8
309 ; CHECK-NEXT: umov w8, v1.b[7]
310 ; CHECK-NEXT: mov v0.b[6], w9
311 ; CHECK-NEXT: umov w9, v1.b[8]
312 ; CHECK-NEXT: mov v0.b[7], w8
313 ; CHECK-NEXT: umov w8, v1.b[9]
314 ; CHECK-NEXT: mov v0.b[8], w9
315 ; CHECK-NEXT: umov w9, v1.b[10]
316 ; CHECK-NEXT: mov v0.b[9], w8
317 ; CHECK-NEXT: umov w8, v1.b[11]
318 ; CHECK-NEXT: mov v0.b[10], w9
319 ; CHECK-NEXT: umov w9, v1.b[12]
320 ; CHECK-NEXT: mov v0.b[11], w8
321 ; CHECK-NEXT: umov w8, v1.b[13]
322 ; CHECK-NEXT: mov v0.b[12], w9
323 ; CHECK-NEXT: umov w9, v1.b[14]
324 ; CHECK-NEXT: mov v0.b[13], w8
325 ; CHECK-NEXT: umov w8, v1.b[15]
326 ; CHECK-NEXT: mov v0.b[14], w9
327 ; CHECK-NEXT: mov v0.b[15], w8
328 ; CHECK-NEXT: ret
329 %mask = call <16 x i1> @llvm.vector.extract.v16i1.nxv16i1(<vscale x 16 x i1> %inmask, i64 0)
330 ret <16 x i1> %mask
331 }
334 ; Fixed length clamping
336 define <2 x i64> @extract_fixed_v2i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind #0 {
337 ; CHECK-LABEL: extract_fixed_v2i64_nxv2i64:
338 ; CHECK: // %bb.0:
339 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16
340 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
341 ; CHECK-NEXT: ret
342 %retval = call <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 2)
343 ret <2 x i64> %retval
344 }
346 define void @extract_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec, ptr %p) nounwind #0 {
347 ; CHECK-LABEL: extract_fixed_v4i64_nxv2i64:
348 ; CHECK: // %bb.0:
349 ; CHECK-NEXT: ext z0.b, z0.b, z0.b, #32
350 ; CHECK-NEXT: ptrue p0.d
351 ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
352 ; CHECK-NEXT: ret
353 %retval = call <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64> %vec, i64 4)
354 store <4 x i64> %retval, ptr %p
355 ret void
356 }
358 ; Check that extract from load via bitcast-gep-of-scalar-ptr does not crash.
359 define <4 x i32> @typesize_regression_test_v4i32(ptr %addr, i64 %idx) {
360 ; CHECK-LABEL: typesize_regression_test_v4i32:
361 ; CHECK: // %bb.0: // %entry
362 ; CHECK-NEXT: ptrue p0.s
363 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x1, lsl #2]
364 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
365 ; CHECK-NEXT: ret
366 entry:
367 %ptr = getelementptr inbounds i32, ptr %addr, i64 %idx
368 %bc = bitcast ptr %ptr to ptr
369 %ld = load volatile <vscale x 4 x i32>, ptr %bc, align 16
370 %out = call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %ld, i64 0)
371 ret <4 x i32> %out
372 }
374 ;
375 ; Extract fixed-width vector from a scalable vector splat.
376 ;
378 define <2 x float> @extract_v2f32_nxv4f32_splat(float %f) {
379 ; CHECK-LABEL: extract_v2f32_nxv4f32_splat:
380 ; CHECK: // %bb.0:
381 ; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
382 ; CHECK-NEXT: dup v0.2s, v0.s[0]
383 ; CHECK-NEXT: ret
384 %ins = insertelement <vscale x 4 x float> poison, float %f, i32 0
385 %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
386 %ext = call <2 x float> @llvm.vector.extract.v2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0)
387 ret <2 x float> %ext
388 }
390 define <2 x float> @extract_v2f32_nxv4f32_splat_const() {
391 ; CHECK-LABEL: extract_v2f32_nxv4f32_splat_const:
392 ; CHECK: // %bb.0:
393 ; CHECK-NEXT: fmov v0.2s, #1.00000000
394 ; CHECK-NEXT: ret
395 %ins = insertelement <vscale x 4 x float> poison, float 1.0, i32 0
396 %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
397 %ext = call <2 x float> @llvm.vector.extract.v2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0)
398 ret <2 x float> %ext
399 }
401 define <4 x i32> @extract_v4i32_nxv8i32_splat_const() {
402 ; CHECK-LABEL: extract_v4i32_nxv8i32_splat_const:
403 ; CHECK: // %bb.0:
404 ; CHECK-NEXT: movi v0.4s, #1
405 ; CHECK-NEXT: ret
406 %ins = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
407 %splat = shufflevector <vscale x 8 x i32> %ins, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
408 %ext = call <4 x i32> @llvm.vector.extract.v4i32.nxv8i32(<vscale x 8 x i32> %splat, i64 0)
409 ret <4 x i32> %ext
410 }
412 attributes #0 = { vscale_range(2,2) }
413 attributes #1 = { vscale_range(8,8) }
415 declare <2 x i64> @llvm.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64>, i64)
417 declare <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32>, i64)
418 declare <4 x i32> @llvm.vector.extract.v4i32.nxv2i32(<vscale x 2 x i32>, i64)
420 declare <8 x i16> @llvm.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16>, i64)
421 declare <8 x i16> @llvm.vector.extract.v8i16.nxv4i16(<vscale x 4 x i16>, i64)
422 declare <8 x i16> @llvm.vector.extract.v8i16.nxv2i16(<vscale x 2 x i16>, i64)
424 declare <16 x i8> @llvm.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8>, i64)
425 declare <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(<vscale x 8 x i8>, i64)
426 declare <16 x i8> @llvm.vector.extract.v16i8.nxv4i8(<vscale x 4 x i8>, i64)
427 declare <16 x i8> @llvm.vector.extract.v16i8.nxv2i8(<vscale x 2 x i8>, i64)
429 declare <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1>, i64)
430 declare <4 x i1> @llvm.vector.extract.v4i1.nxv4i1(<vscale x 4 x i1>, i64)
431 declare <8 x i1> @llvm.vector.extract.v8i1.nxv8i1(<vscale x 8 x i1>, i64)
432 declare <16 x i1> @llvm.vector.extract.v16i1.nxv16i1(<vscale x 16 x i1>, i64)
434 declare <4 x i64> @llvm.vector.extract.v4i64.nxv2i64(<vscale x 2 x i64>, i64)
435 declare <2 x float> @llvm.vector.extract.v2f32.nxv4f32(<vscale x 4 x float>, i64)
436 declare <4 x i32> @llvm.vector.extract.v4i32.nxv8i32(<vscale x 8 x i32>, i64)