1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+f64mm < %s | FileCheck %s
8 define <vscale x 16 x i8> @ld1rob_i8(<vscale x 16 x i1> %pg, ptr %a) {
9 ; CHECK-LABEL: ld1rob_i8:
11 ; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, #32]
13 %base = getelementptr i8, ptr %a, i64 32
14 %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, ptr %base)
15 ret <vscale x 16 x i8> %load
22 define <vscale x 8 x i16> @ld1roh_i16(<vscale x 8 x i1> %pg, ptr %a) {
23 ; CHECK-LABEL: ld1roh_i16:
25 ; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, #64]
27 %base = getelementptr i16, ptr %a, i64 32
28 %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1> %pg, ptr %base)
29 ret <vscale x 8 x i16> %load
32 define <vscale x 8 x half> @ld1roh_f16(<vscale x 8 x i1> %pg, ptr %a) {
33 ; CHECK-LABEL: ld1roh_f16:
35 ; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, #64]
37 %base = getelementptr half, ptr %a, i64 32
38 %load = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1> %pg, ptr %base)
39 ret <vscale x 8 x half> %load
42 define <vscale x 8 x bfloat> @ld1roh_bf16(<vscale x 8 x i1> %pg, ptr %a) #0 {
43 ; CHECK-LABEL: ld1roh_bf16:
45 ; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, #64]
47 %base = getelementptr bfloat, ptr %a, i64 32
48 %load = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1ro.nxv8bf16(<vscale x 8 x i1> %pg, ptr %base)
49 ret <vscale x 8 x bfloat> %load
56 define <vscale x 4 x i32> @ld1row_i32(<vscale x 4 x i1> %pg, ptr %a) {
57 ; CHECK-LABEL: ld1row_i32:
59 ; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, #128]
61 %base = getelementptr i32, ptr %a, i64 32
62 %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1> %pg, ptr %base)
63 ret <vscale x 4 x i32> %load
66 define <vscale x 4 x float> @ld1row_f32(<vscale x 4 x i1> %pg, ptr %a) {
67 ; CHECK-LABEL: ld1row_f32:
69 ; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, #128]
71 %base = getelementptr float, ptr %a, i64 32
72 %load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1> %pg, ptr %base)
73 ret <vscale x 4 x float> %load
80 define <vscale x 2 x i64> @ld1rod_i64(<vscale x 2 x i1> %pg, ptr %a) {
81 ; CHECK-LABEL: ld1rod_i64:
83 ; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, #-64]
85 %base = getelementptr i64, ptr %a, i64 -8
86 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1> %pg, ptr %base)
87 ret <vscale x 2 x i64> %load
90 define <vscale x 2 x double> @ld1rod_f64(<vscale x 2 x i1> %pg, ptr %a) {
91 ; CHECK-LABEL: ld1rod_f64:
93 ; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, #-128]
95 %base = getelementptr double, ptr %a, i64 -16
96 %load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1> %pg, ptr %base)
97 ret <vscale x 2 x double> %load
102 ; range checks: immediate must be a multiple of 32 in the range -256, ..., 224
105 define <vscale x 16 x i8> @ld1rob_i8_lower_bound(<vscale x 16 x i1> %pg, ptr %a) {
106 ; CHECK-LABEL: ld1rob_i8_lower_bound:
108 ; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, #-256]
110 %base = getelementptr i8, ptr %a, i64 -256
111 %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, ptr %base)
112 ret <vscale x 16 x i8> %load
116 define <vscale x 8 x i16> @ld1roh_i16_below_lower_bound(<vscale x 8 x i1> %pg, ptr %a) {
117 ; CHECK-LABEL: ld1roh_i16_below_lower_bound:
119 ; CHECK-NEXT: mov x8, #-129
120 ; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0, x8, lsl #1]
122 %base = getelementptr i16, ptr %a, i64 -129
123 %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1> %pg, ptr %base)
124 ret <vscale x 8 x i16> %load
127 define <vscale x 16 x i8> @ld1rob_i8_below_lower_bound_01(<vscale x 16 x i1> %pg, ptr %a) {
128 ; CHECK-LABEL: ld1rob_i8_below_lower_bound_01:
130 ; CHECK-NEXT: mov x8, #-257
131 ; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, x8]
133 %base = getelementptr i8, ptr %a, i64 -257
134 %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, ptr %base)
135 ret <vscale x 16 x i8> %load
138 ; not a multiple of 32
139 define <vscale x 4 x i32> @ld1row_i32_not_multiple(<vscale x 4 x i1> %pg, ptr %a) {
140 ; CHECK-LABEL: ld1row_i32_not_multiple:
142 ; CHECK-NEXT: mov x8, #3
143 ; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0, x8, lsl #2]
145 %base = getelementptr i32, ptr %a, i64 3
146 %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1> %pg, ptr %base)
147 ret <vscale x 4 x i32> %load
151 define <vscale x 2 x i64> @ld1rod_i64_upper_bound(<vscale x 2 x i1> %pg, ptr %a) {
152 ; CHECK-LABEL: ld1rod_i64_upper_bound:
154 ; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0, #224]
156 %base = getelementptr i64, ptr %a, i64 28
157 %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1> %pg, ptr %base)
158 ret <vscale x 2 x i64> %load
161 define <vscale x 16 x i8> @ld1rob_i8_beyond_upper_bound(<vscale x 16 x i1> %pg, ptr %a) {
162 ; CHECK-LABEL: ld1rob_i8_beyond_upper_bound:
164 ; CHECK-NEXT: mov w8, #225
165 ; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0, x8]
167 %base = getelementptr i8, ptr %a, i64 225
168 %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pg, ptr %base)
169 ret <vscale x 16 x i8> %load
172 declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1>, ptr)
174 declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1>, ptr)
175 declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1>, ptr)
176 declare <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1ro.nxv8bf16(<vscale x 8 x i1>, ptr)
178 declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1>, ptr)
179 declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1>, ptr)
181 declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1>, ptr)
182 declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1>, ptr)
185 ; +bf16 is required for the bfloat version.
186 attributes #0 = { "target-features"="+sve,+f64mm,+bf16" }