1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
7 define <vscale x 16 x i8> @addhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
8 ; CHECK-LABEL: addhnb_h:
10 ; CHECK-NEXT: addhnb z0.b, z0.h, z1.h
12 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.addhnb.nxv8i16(<vscale x 8 x i16> %a,
13 <vscale x 8 x i16> %b)
14 ret <vscale x 16 x i8> %out
17 define <vscale x 8 x i16> @addhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
18 ; CHECK-LABEL: addhnb_s:
20 ; CHECK-NEXT: addhnb z0.h, z0.s, z1.s
22 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.addhnb.nxv4i32(<vscale x 4 x i32> %a,
23 <vscale x 4 x i32> %b)
24 ret <vscale x 8 x i16> %out
27 define <vscale x 4 x i32> @addhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
28 ; CHECK-LABEL: addhnb_d:
30 ; CHECK-NEXT: addhnb z0.s, z0.d, z1.d
32 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.addhnb.nxv2i64(<vscale x 2 x i64> %a,
33 <vscale x 2 x i64> %b)
34 ret <vscale x 4 x i32> %out
39 define <vscale x 16 x i8> @addhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
40 ; CHECK-LABEL: addhnt_h:
42 ; CHECK-NEXT: addhnt z0.b, z1.h, z2.h
44 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.addhnt.nxv8i16(<vscale x 16 x i8> %a,
45 <vscale x 8 x i16> %b,
46 <vscale x 8 x i16> %c)
47 ret <vscale x 16 x i8> %out
50 define <vscale x 8 x i16> @addhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
51 ; CHECK-LABEL: addhnt_s:
53 ; CHECK-NEXT: addhnt z0.h, z1.s, z2.s
55 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.addhnt.nxv4i32(<vscale x 8 x i16> %a,
56 <vscale x 4 x i32> %b,
57 <vscale x 4 x i32> %c)
58 ret <vscale x 8 x i16> %out
61 define <vscale x 4 x i32> @addhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
62 ; CHECK-LABEL: addhnt_d:
64 ; CHECK-NEXT: addhnt z0.s, z1.d, z2.d
66 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.addhnt.nxv2i64(<vscale x 4 x i32> %a,
67 <vscale x 2 x i64> %b,
68 <vscale x 2 x i64> %c)
69 ret <vscale x 4 x i32> %out
74 define <vscale x 16 x i8> @raddhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
75 ; CHECK-LABEL: raddhnb_h:
77 ; CHECK-NEXT: raddhnb z0.b, z0.h, z1.h
79 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.raddhnb.nxv8i16(<vscale x 8 x i16> %a,
80 <vscale x 8 x i16> %b)
81 ret <vscale x 16 x i8> %out
84 define <vscale x 8 x i16> @raddhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
85 ; CHECK-LABEL: raddhnb_s:
87 ; CHECK-NEXT: raddhnb z0.h, z0.s, z1.s
89 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.raddhnb.nxv4i32(<vscale x 4 x i32> %a,
90 <vscale x 4 x i32> %b)
91 ret <vscale x 8 x i16> %out
94 define <vscale x 4 x i32> @raddhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
95 ; CHECK-LABEL: raddhnb_d:
97 ; CHECK-NEXT: raddhnb z0.s, z0.d, z1.d
99 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.raddhnb.nxv2i64(<vscale x 2 x i64> %a,
100 <vscale x 2 x i64> %b)
101 ret <vscale x 4 x i32> %out
106 define <vscale x 16 x i8> @raddhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
107 ; CHECK-LABEL: raddhnt_h:
109 ; CHECK-NEXT: raddhnt z0.b, z1.h, z2.h
111 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.raddhnt.nxv8i16(<vscale x 16 x i8> %a,
112 <vscale x 8 x i16> %b,
113 <vscale x 8 x i16> %c)
114 ret <vscale x 16 x i8> %out
117 define <vscale x 8 x i16> @raddhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
118 ; CHECK-LABEL: raddhnt_s:
120 ; CHECK-NEXT: raddhnt z0.h, z1.s, z2.s
122 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.raddhnt.nxv4i32(<vscale x 8 x i16> %a,
123 <vscale x 4 x i32> %b,
124 <vscale x 4 x i32> %c)
125 ret <vscale x 8 x i16> %out
128 define <vscale x 4 x i32> @raddhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
129 ; CHECK-LABEL: raddhnt_d:
131 ; CHECK-NEXT: raddhnt z0.s, z1.d, z2.d
133 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.raddhnt.nxv2i64(<vscale x 4 x i32> %a,
134 <vscale x 2 x i64> %b,
135 <vscale x 2 x i64> %c)
136 ret <vscale x 4 x i32> %out
141 define <vscale x 16 x i8> @rsubhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
142 ; CHECK-LABEL: rsubhnb_h:
144 ; CHECK-NEXT: rsubhnb z0.b, z0.h, z1.h
146 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnb.nxv8i16(<vscale x 8 x i16> %a,
147 <vscale x 8 x i16> %b)
148 ret <vscale x 16 x i8> %out
151 define <vscale x 8 x i16> @rsubhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
152 ; CHECK-LABEL: rsubhnb_s:
154 ; CHECK-NEXT: rsubhnb z0.h, z0.s, z1.s
156 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnb.nxv4i32(<vscale x 4 x i32> %a,
157 <vscale x 4 x i32> %b)
158 ret <vscale x 8 x i16> %out
161 define <vscale x 4 x i32> @rsubhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
162 ; CHECK-LABEL: rsubhnb_d:
164 ; CHECK-NEXT: rsubhnb z0.s, z0.d, z1.d
166 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnb.nxv2i64(<vscale x 2 x i64> %a,
167 <vscale x 2 x i64> %b)
168 ret <vscale x 4 x i32> %out
173 define <vscale x 16 x i8> @rsubhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
174 ; CHECK-LABEL: rsubhnt_h:
176 ; CHECK-NEXT: rsubhnt z0.b, z1.h, z2.h
178 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnt.nxv8i16(<vscale x 16 x i8> %a,
179 <vscale x 8 x i16> %b,
180 <vscale x 8 x i16> %c)
181 ret <vscale x 16 x i8> %out
184 define <vscale x 8 x i16> @rsubhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
185 ; CHECK-LABEL: rsubhnt_s:
187 ; CHECK-NEXT: rsubhnt z0.h, z1.s, z2.s
189 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnt.nxv4i32(<vscale x 8 x i16> %a,
190 <vscale x 4 x i32> %b,
191 <vscale x 4 x i32> %c)
192 ret <vscale x 8 x i16> %out
195 define <vscale x 4 x i32> @rsubhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
196 ; CHECK-LABEL: rsubhnt_d:
198 ; CHECK-NEXT: rsubhnt z0.s, z1.d, z2.d
200 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnt.nxv2i64(<vscale x 4 x i32> %a,
201 <vscale x 2 x i64> %b,
202 <vscale x 2 x i64> %c)
203 ret <vscale x 4 x i32> %out
208 define <vscale x 16 x i8> @subhnb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
209 ; CHECK-LABEL: subhnb_h:
211 ; CHECK-NEXT: subhnb z0.b, z0.h, z1.h
213 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.subhnb.nxv8i16(<vscale x 8 x i16> %a,
214 <vscale x 8 x i16> %b)
215 ret <vscale x 16 x i8> %out
218 define <vscale x 8 x i16> @subhnb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
219 ; CHECK-LABEL: subhnb_s:
221 ; CHECK-NEXT: subhnb z0.h, z0.s, z1.s
223 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.subhnb.nxv4i32(<vscale x 4 x i32> %a,
224 <vscale x 4 x i32> %b)
225 ret <vscale x 8 x i16> %out
228 define <vscale x 4 x i32> @subhnb_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
229 ; CHECK-LABEL: subhnb_d:
231 ; CHECK-NEXT: subhnb z0.s, z0.d, z1.d
233 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.subhnb.nxv2i64(<vscale x 2 x i64> %a,
234 <vscale x 2 x i64> %b)
235 ret <vscale x 4 x i32> %out
240 define <vscale x 16 x i8> @subhnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
241 ; CHECK-LABEL: subhnt_h:
243 ; CHECK-NEXT: subhnt z0.b, z1.h, z2.h
245 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.subhnt.nxv8i16(<vscale x 16 x i8> %a,
246 <vscale x 8 x i16> %b,
247 <vscale x 8 x i16> %c)
248 ret <vscale x 16 x i8> %out
251 define <vscale x 8 x i16> @subhnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
252 ; CHECK-LABEL: subhnt_s:
254 ; CHECK-NEXT: subhnt z0.h, z1.s, z2.s
256 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.subhnt.nxv4i32(<vscale x 8 x i16> %a,
257 <vscale x 4 x i32> %b,
258 <vscale x 4 x i32> %c)
259 ret <vscale x 8 x i16> %out
262 define <vscale x 4 x i32> @subhnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
263 ; CHECK-LABEL: subhnt_d:
265 ; CHECK-NEXT: subhnt z0.s, z1.d, z2.d
267 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.subhnt.nxv2i64(<vscale x 4 x i32> %a,
268 <vscale x 2 x i64> %b,
269 <vscale x 2 x i64> %c)
270 ret <vscale x 4 x i32> %out
274 declare <vscale x 16 x i8> @llvm.aarch64.sve.addhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
275 declare <vscale x 8 x i16> @llvm.aarch64.sve.addhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
276 declare <vscale x 4 x i32> @llvm.aarch64.sve.addhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
278 declare <vscale x 16 x i8> @llvm.aarch64.sve.addhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>)
279 declare <vscale x 8 x i16> @llvm.aarch64.sve.addhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>)
280 declare <vscale x 4 x i32> @llvm.aarch64.sve.addhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>)
282 declare <vscale x 16 x i8> @llvm.aarch64.sve.raddhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
283 declare <vscale x 8 x i16> @llvm.aarch64.sve.raddhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
284 declare <vscale x 4 x i32> @llvm.aarch64.sve.raddhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
286 declare <vscale x 16 x i8> @llvm.aarch64.sve.raddhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>)
287 declare <vscale x 8 x i16> @llvm.aarch64.sve.raddhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>)
288 declare <vscale x 4 x i32> @llvm.aarch64.sve.raddhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>)
290 declare <vscale x 16 x i8> @llvm.aarch64.sve.subhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
291 declare <vscale x 8 x i16> @llvm.aarch64.sve.subhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
292 declare <vscale x 4 x i32> @llvm.aarch64.sve.subhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
294 declare <vscale x 16 x i8> @llvm.aarch64.sve.subhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>)
295 declare <vscale x 8 x i16> @llvm.aarch64.sve.subhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>)
296 declare <vscale x 4 x i32> @llvm.aarch64.sve.subhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>)
298 declare <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
299 declare <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
300 declare <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
302 declare <vscale x 16 x i8> @llvm.aarch64.sve.rsubhnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, <vscale x 8 x i16>)
303 declare <vscale x 8 x i16> @llvm.aarch64.sve.rsubhnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, <vscale x 4 x i32>)
304 declare <vscale x 4 x i32> @llvm.aarch64.sve.rsubhnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, <vscale x 2 x i64>)