llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o - 2> %t | FileCheck -check-prefix=GCN %s
   3 # RUN: FileCheck -check-prefix=ERR %s < %t
   4
   5 # ERR: remark: <unknown>:0:0: cannot select: %1:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %0:sgpr(s32) (in function: readfirstlane_s)
   6
   7 ---
   8 name: readfirstlane_v
   9 legalized: true
  10 regBankSelected: true
  11 tracksRegLiveness: true
  12
  13 body: |
  14   bb.0:
  15     liveins: $vgpr0
  16     ; GCN-LABEL: name: readfirstlane_v
  17     ; GCN: liveins: $vgpr0
  18     ; GCN-NEXT: {{  $}}
  19     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  20     ; GCN-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY]], implicit $exec
  21     ; GCN-NEXT: S_ENDPGM 0, implicit [[V_READFIRSTLANE_B32_]]
  22     %0:vgpr(s32) = COPY $vgpr0
  23     %1:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %0
  24     S_ENDPGM 0, implicit %1
  25 ...
  26
  27 ---
  28 name: readfirstlane_v_imm
  29 legalized: true
  30 regBankSelected: true
  31 tracksRegLiveness: true
  32
  33 body: |
  34   bb.0:
  35
  36     ; GCN-LABEL: name: readfirstlane_v_imm
  37     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
  38     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[V_MOV_B32_e32_]]
  39     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 [[COPY]]
  40     ; GCN-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
  41     %0:vgpr(s32) = G_CONSTANT i32 123
  42     %1:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %0
  43     S_ENDPGM 0, implicit %1
  44 ...
  45
  46 # Make sure this fails to select
  47 ---
  48 name: readfirstlane_s
  49 legalized: true
  50 regBankSelected: true
  51 tracksRegLiveness: true
  52
  53 body: |
  54   bb.0:
  55     liveins: $sgpr0
  56     ; GCN-LABEL: name: readfirstlane_s
  57     ; GCN: liveins: $sgpr0
  58     ; GCN-NEXT: {{  $}}
  59     ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
  60     ; GCN-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY]](s32)
  61     ; GCN-NEXT: S_ENDPGM 0, implicit [[INT]](s32)
  62     %0:sgpr(s32) = COPY $sgpr0
  63     %1:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %0
  64     S_ENDPGM 0, implicit %1
  65 ...