llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
   3
   4 ---
   5 name: sffbh_s32_ss
   6 legalized: true
   7 regBankSelected: true
   8 tracksRegLiveness: true
   9
  10 body: |
  11   bb.0:
  12     liveins: $sgpr0
  13
  14     ; CHECK-LABEL: name: sffbh_s32_ss
  15     ; CHECK: liveins: $sgpr0
  16     ; CHECK-NEXT: {{  $}}
  17     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  18     ; CHECK-NEXT: [[S_FLBIT_I32_:%[0-9]+]]:sreg_32 = S_FLBIT_I32 [[COPY]]
  19     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FLBIT_I32_]]
  20     %0:sgpr(s32) = COPY $sgpr0
  21     %1:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sffbh), %0
  22     S_ENDPGM 0, implicit %1
  23 ...
  24
  25 ---
  26 name: sffbh_s32_vs
  27 legalized: true
  28 regBankSelected: true
  29 tracksRegLiveness: true
  30
  31 body: |
  32   bb.0:
  33     liveins: $sgpr0
  34
  35     ; CHECK-LABEL: name: sffbh_s32_vs
  36     ; CHECK: liveins: $sgpr0
  37     ; CHECK-NEXT: {{  $}}
  38     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  39     ; CHECK-NEXT: [[V_FFBH_I32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_I32_e64 [[COPY]], implicit $exec
  40     ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBH_I32_e64_]]
  41     %0:sgpr(s32) = COPY $sgpr0
  42     %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sffbh), %0
  43     S_ENDPGM 0, implicit %1
  44 ...
  45
  46 ---
  47 name: sffbh_s32_vv
  48 legalized: true
  49 regBankSelected: true
  50 tracksRegLiveness: true
  51
  52 body: |
  53   bb.0:
  54     liveins: $vgpr0
  55
  56     ; CHECK-LABEL: name: sffbh_s32_vv
  57     ; CHECK: liveins: $vgpr0
  58     ; CHECK-NEXT: {{  $}}
  59     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  60     ; CHECK-NEXT: [[V_FFBH_I32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_I32_e64 [[COPY]], implicit $exec
  61     ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBH_I32_e64_]]
  62     %0:vgpr(s32) = COPY $vgpr0
  63     %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sffbh), %0
  64     S_ENDPGM 0, implicit %1
  65 ...