Bump version to 19.1.0-rc3
[llvm-project.git] / llvm / test / CodeGen / AMDGPU / GlobalISel / inst-select-amdgpu-ffbl-b32.mir
blobbf2f9367ae8e942b757d893f8f1390cc85e61744
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
4 ---
6 name:            ffbl_b32_s32_s_s
7 legalized:       true
8 regBankSelected: true
9 tracksRegLiveness: true
11 body: |
12   bb.0:
13     liveins: $sgpr0
15     ; CHECK-LABEL: name: ffbl_b32_s32_s_s
16     ; CHECK: liveins: $sgpr0
17     ; CHECK-NEXT: {{  $}}
18     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
19     ; CHECK-NEXT: [[S_FF1_I32_B32_:%[0-9]+]]:sreg_32 = S_FF1_I32_B32 [[COPY]]
20     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FF1_I32_B32_]]
21   %0:sgpr(s32) = COPY $sgpr0
22   %1:sgpr(s32) = G_AMDGPU_FFBL_B32 %0
23   S_ENDPGM 0, implicit %1
25 ...
27 ---
29 name:            ffbl_b32_s32_v_v
30 legalized:       true
31 regBankSelected: true
32 tracksRegLiveness: true
34 body: |
35   bb.0:
36     liveins: $vgpr0
38     ; CHECK-LABEL: name: ffbl_b32_s32_v_v
39     ; CHECK: liveins: $vgpr0
40     ; CHECK-NEXT: {{  $}}
41     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
42     ; CHECK-NEXT: [[V_FFBL_B32_e64_:%[0-9]+]]:vgpr_32 = V_FFBL_B32_e64 [[COPY]], implicit $exec
43     ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBL_B32_e64_]]
44   %0:vgpr(s32) = COPY $vgpr0
45   %1:vgpr(s32) = G_AMDGPU_FFBL_B32 %0
46   S_ENDPGM 0, implicit %1
48 ...
50 ---
52 name:            ffbl_b32_v_s
53 legalized:       true
54 regBankSelected: true
55 tracksRegLiveness: true
57 body: |
58   bb.0:
59     liveins: $sgpr0
61     ; CHECK-LABEL: name: ffbl_b32_v_s
62     ; CHECK: liveins: $sgpr0
63     ; CHECK-NEXT: {{  $}}
64     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
65     ; CHECK-NEXT: [[V_FFBL_B32_e64_:%[0-9]+]]:vgpr_32 = V_FFBL_B32_e64 [[COPY]], implicit $exec
66     ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBL_B32_e64_]]
67   %0:sgpr(s32) = COPY $sgpr0
68   %1:vgpr(s32) = G_AMDGPU_FFBL_B32 %0
69   S_ENDPGM 0, implicit %1
71 ...