1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
3 # RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
4 # RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
8 name: anyext_sgpr_s16_to_sgpr_s32
15 ; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32
16 ; GCN: liveins: $sgpr0
18 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
19 ; GCN-NEXT: $sgpr0 = COPY [[COPY]]
20 %0:sgpr(s32) = COPY $sgpr0
21 %1:sgpr(s16) = G_TRUNC %0
22 %2:sgpr(s32) = G_ANYEXT %1
28 name: anyext_sgpr_s32_to_sgpr_s64
31 tracksRegLiveness: true
36 ; GCN-LABEL: name: anyext_sgpr_s32_to_sgpr_s64
37 ; GCN: liveins: $sgpr0
39 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY $sgpr0
40 ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
41 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
42 ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
43 %0:sgpr(s32) = COPY $sgpr0
44 %1:sgpr(s64) = G_ANYEXT %0
45 S_ENDPGM 0, implicit %1
50 name: anyext_sgpr_s16_to_sgpr_s64
53 tracksRegLiveness: true
58 ; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64
59 ; GCN: liveins: $sgpr0
61 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
62 ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
63 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
64 ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
65 %0:sgpr(s32) = COPY $sgpr0
66 %1:sgpr(s16) = G_TRUNC %0
67 %2:sgpr(s64) = G_ANYEXT %1
68 S_ENDPGM 0, implicit %2
73 name: anyext_vgpr_s32_to_vgpr_s64
76 tracksRegLiveness: true
81 ; GCN-LABEL: name: anyext_vgpr_s32_to_vgpr_s64
82 ; GCN: liveins: $vgpr0
84 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
85 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
86 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
87 ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
88 %0:vgpr(s32) = COPY $vgpr0
89 %1:vgpr(s64) = G_ANYEXT %0
90 S_ENDPGM 0, implicit %1
95 name: anyext_vgpr_s16_to_vgpr_s64
98 tracksRegLiveness: true
103 %0:vgpr(s32) = COPY $vgpr0
104 %1:vgpr(s16) = G_TRUNC %0
105 %2:vgpr(s64) = G_ANYEXT %1
106 S_ENDPGM 0, implicit %2
110 # vcc is an invalid extension source
113 # name: anyext_vcc_s1_to_vgpr_s32
115 # regBankSelected: true
120 # %0:vgpr(s32) = COPY $vgpr0
121 # %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
122 # %2:vgpr(s32) = G_ANYEXT %1
128 name: anyext_sgpr_s1_to_sgpr_s16
130 regBankSelected: true
135 ; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s16
136 ; GCN: liveins: $sgpr0
138 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
139 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
140 ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def dead $scc
141 ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
142 %0:sgpr(s32) = COPY $sgpr0
143 %1:sgpr(s1) = G_TRUNC %0
144 %2:sgpr(s16) = G_ANYEXT %1
145 %3:sgpr(s32) = G_ZEXT %2
151 name: anyext_sgpr_s1_to_sgpr_s32
153 regBankSelected: true
158 ; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32
159 ; GCN: liveins: $sgpr0
161 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
162 ; GCN-NEXT: $sgpr0 = COPY [[COPY]]
163 %0:sgpr(s32) = COPY $sgpr0
164 %1:sgpr(s1) = G_TRUNC %0
165 %2:sgpr(s32) = G_ANYEXT %1
171 name: anyext_sgpr_s1_to_sgpr_s64
173 regBankSelected: true
178 ; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s64
179 ; GCN: liveins: $sgpr0
181 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
182 ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
183 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
184 ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
185 %0:sgpr(s32) = COPY $sgpr0
186 %1:sgpr(s1) = G_TRUNC %0
187 %2:sgpr(s64) = G_ANYEXT %1
188 $sgpr0_sgpr1 = COPY %2
193 name: anyext_vgpr_s1_to_vgpr_s16
195 regBankSelected: true
200 ; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s16
201 ; GCN: liveins: $vgpr0
203 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
204 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
205 ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
206 ; GCN-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
207 %0:vgpr(s32) = COPY $vgpr0
208 %1:vgpr(s1) = G_TRUNC %0
209 %2:vgpr(s16) = G_ANYEXT %1
210 %3:vgpr(s32) = G_ZEXT %2
216 name: anyext_vgpr_s1_to_vgpr_s32
218 regBankSelected: true
223 ; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
224 ; GCN: liveins: $vgpr0
226 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
227 ; GCN-NEXT: $vgpr0 = COPY [[COPY]]
228 %0:vgpr(s32) = COPY $vgpr0
229 %1:vgpr(s1) = G_TRUNC %0
230 %2:vgpr(s32) = G_ANYEXT %1
236 name: anyext_sgpr_s1_to_vgpr_s32
238 regBankSelected: true
243 ; GCN-LABEL: name: anyext_sgpr_s1_to_vgpr_s32
244 ; GCN: liveins: $sgpr0
246 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
247 ; GCN-NEXT: $sgpr0 = COPY [[COPY]]
248 %0:sgpr(s32) = COPY $sgpr0
249 %1:sgpr(s1) = G_TRUNC %0
250 %2:sgpr(s32) = G_ANYEXT %1
256 name: anyext_vgpr_s16_to_vgpr_s32
258 regBankSelected: true
263 ; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
264 ; GCN: liveins: $vgpr0
266 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
267 ; GCN-NEXT: $vgpr0 = COPY [[COPY]]
268 %0:vgpr(s32) = COPY $vgpr0
269 %1:vgpr(s16) = G_TRUNC %0
270 %2:vgpr(s32) = G_ANYEXT %1
275 # The source register already has an assigned register class that
276 # should not be interpreted as vcc.
279 name: anyext_regclass_sgpr_s1_to_sgpr_s32
281 regBankSelected: true
286 ; GCN-LABEL: name: anyext_regclass_sgpr_s1_to_sgpr_s32
287 ; GCN: liveins: $sgpr0
289 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
290 ; GCN-NEXT: $sgpr0 = COPY [[COPY]]
291 %0:sgpr(s32) = COPY $sgpr0
292 %1:sreg_32(s1) = G_TRUNC %0
293 %2:sgpr(s32) = G_ANYEXT %1