llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX7 %s
   3 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX8 %s
   4
   5 ---
   6 name: bswap_i32_vv
   7 legalized: true
   8 regBankSelected: true
   9
  10 body: |
  11   bb.0:
  12     liveins: $vgpr0
  13     ; GFX7-LABEL: name: bswap_i32_vv
  14     ; GFX7: liveins: $vgpr0
  15     ; GFX7-NEXT: {{  $}}
  16     ; GFX7-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  17     ; GFX7-NEXT: [[V_ALIGNBIT_B32_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_e64 [[COPY]], [[COPY]], 8, implicit $exec
  18     ; GFX7-NEXT: [[V_ALIGNBIT_B32_e64_1:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_e64 [[COPY]], [[COPY]], 24, implicit $exec
  19     ; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16711935
  20     ; GFX7-NEXT: [[V_BFI_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFI_B32_e64 [[S_MOV_B32_]], [[V_ALIGNBIT_B32_e64_1]], [[V_ALIGNBIT_B32_e64_]], implicit $exec
  21     ; GFX7-NEXT: S_ENDPGM 0, implicit [[V_BFI_B32_e64_]]
  22     ; GFX8-LABEL: name: bswap_i32_vv
  23     ; GFX8: liveins: $vgpr0
  24     ; GFX8-NEXT: {{  $}}
  25     ; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  26     ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 66051
  27     ; GFX8-NEXT: [[V_PERM_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERM_B32_e64 0, [[COPY]], [[S_MOV_B32_]], implicit $exec
  28     ; GFX8-NEXT: S_ENDPGM 0, implicit [[V_PERM_B32_e64_]]
  29     %0:vgpr(s32) = COPY $vgpr0
  30     %1:vgpr(s32) = G_BSWAP %0
  31     S_ENDPGM 0, implicit %1
  32 ...