llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs  -o - %s | FileCheck -check-prefix=GCN  %s
   3
   4 ---
   5 name: test_build_vector_v_v2s32_v_s32_v_s32
   6 legalized:       true
   7 regBankSelected: true
   8 tracksRegLiveness: true
   9
  10 body: |
  11   bb.0:
  12     liveins: $vgpr0, $vgpr1
  13
  14     ; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_v_s32
  15     ; GCN: liveins: $vgpr0, $vgpr1
  16     ; GCN-NEXT: {{  $}}
  17     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  18     ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  19     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  20     ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  21     %0:vgpr(s32) = COPY $vgpr0
  22     %1:vgpr(s32) = COPY $vgpr1
  23     %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
  24     S_ENDPGM 0, implicit %2
  25 ...
  26
  27 ---
  28 name: test_build_vector_v_v2s32_s_s32_v_s32
  29 legalized:       true
  30 regBankSelected: true
  31 tracksRegLiveness: true
  32
  33 body: |
  34   bb.0:
  35     liveins: $sgpr0, $vgpr0
  36
  37     ; GCN-LABEL: name: test_build_vector_v_v2s32_s_s32_v_s32
  38     ; GCN: liveins: $sgpr0, $vgpr0
  39     ; GCN-NEXT: {{  $}}
  40     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  41     ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  42     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  43     ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  44     %0:sgpr(s32) = COPY $sgpr0
  45     %1:vgpr(s32) = COPY $vgpr0
  46     %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
  47     S_ENDPGM 0, implicit %2
  48 ...
  49
  50 ---
  51 name: test_build_vector_v_v2s32_v_s32_s_s32
  52 legalized:       true
  53 regBankSelected: true
  54 tracksRegLiveness: true
  55
  56 body: |
  57   bb.0:
  58     liveins: $sgpr0, $vgpr0
  59
  60     ; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_s_s32
  61     ; GCN: liveins: $sgpr0, $vgpr0
  62     ; GCN-NEXT: {{  $}}
  63     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  64     ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
  65     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  66     ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  67     %0:vgpr(s32) = COPY $vgpr0
  68     %1:sgpr(s32) = COPY $sgpr0
  69     %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
  70     S_ENDPGM 0, implicit %2
  71 ...
  72
  73 ---
  74 name: test_build_vector_s_v2s32_s_s32_s_s32
  75 legalized:       true
  76 regBankSelected: true
  77 tracksRegLiveness: true
  78
  79 body: |
  80   bb.0:
  81     liveins: $sgpr0, $sgpr1
  82
  83     ; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_s_s32
  84     ; GCN: liveins: $sgpr0, $sgpr1
  85     ; GCN-NEXT: {{  $}}
  86     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  87     ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  88     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  89     ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  90     %0:sgpr(s32) = COPY $sgpr0
  91     %1:sgpr(s32) = COPY $sgpr1
  92     %2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
  93     S_ENDPGM 0, implicit %2
  94 ...
  95
  96 ---
  97 name: test_build_vector_s_v2s64_s_s64_s_s64
  98 legalized:       true
  99 regBankSelected: true
 100 tracksRegLiveness: true
 101
 102 body: |
 103   bb.0:
 104     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 105
 106     ; GCN-LABEL: name: test_build_vector_s_v2s64_s_s64_s_s64
 107     ; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 108     ; GCN-NEXT: {{  $}}
 109     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 110     ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 111     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
 112     ; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
 113     %0:sgpr(s64) = COPY $sgpr0_sgpr1
 114     %1:sgpr(s64) = COPY $sgpr2_sgpr3
 115     %4:sgpr(<2 x s64>) = G_BUILD_VECTOR %0, %1
 116     $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4
 117 ...