llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck %s
   3
   4 ---
   5 name:  ptrmask_p3_s32_sgpr_sgpr_sgpr
   6 legalized:       true
   7 regBankSelected: true
   8
   9 body: |
  10   bb.0:
  11     liveins: $sgpr0, $sgpr1
  12
  13     ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_sgpr
  14     ; CHECK: liveins: $sgpr0, $sgpr1
  15     ; CHECK-NEXT: {{  $}}
  16     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  17     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  18     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
  19     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
  20     %0:sgpr(p3) = COPY $sgpr0
  21     %1:sgpr(s32) = COPY $sgpr1
  22     %2:sgpr(p3) = G_PTRMASK %0, %1
  23     S_ENDPGM 0, implicit %2
  24
  25 ...
  26
  27 ---
  28 name:  ptrmask_p3_s32_sgpr_sgpr_0xf0f0f0f0
  29 legalized:       true
  30 regBankSelected: true
  31
  32 body: |
  33   bb.0:
  34     liveins: $sgpr0
  35
  36     ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0xf0f0f0f0
  37     ; CHECK: liveins: $sgpr0
  38     ; CHECK-NEXT: {{  $}}
  39     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  40     ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -252645136
  41     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def dead $scc
  42     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
  43     %0:sgpr(p3) = COPY $sgpr0
  44     %const:sgpr(s32) = G_CONSTANT i32 -252645136
  45     %1:sgpr(p3) = G_PTRMASK %0, %const
  46     S_ENDPGM 0, implicit %1
  47
  48 ...
  49
  50 ---
  51 name:  ptrmask_p3_s32_sgpr_sgpr_0xffffffff
  52 legalized:       true
  53 regBankSelected: true
  54
  55 body: |
  56   bb.0:
  57     liveins: $sgpr0
  58
  59     ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0xffffffff
  60     ; CHECK: liveins: $sgpr0
  61     ; CHECK-NEXT: {{  $}}
  62     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  63     ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -1
  64     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def dead $scc
  65     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
  66     %0:sgpr(p3) = COPY $sgpr0
  67     %const:sgpr(s32) = G_CONSTANT i32 -1
  68     %1:sgpr(p3) = G_PTRMASK %0, %const
  69     S_ENDPGM 0, implicit %1
  70
  71 ...
  72
  73 ---
  74 name:  ptrmask_p3_s32_sgpr_sgpr_0x00000000
  75 legalized:       true
  76 regBankSelected: true
  77
  78 body: |
  79   bb.0:
  80     liveins: $sgpr0
  81
  82     ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0x00000000
  83     ; CHECK: liveins: $sgpr0
  84     ; CHECK-NEXT: {{  $}}
  85     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  86     ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 0
  87     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def dead $scc
  88     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
  89     %0:sgpr(p3) = COPY $sgpr0
  90     %const:sgpr(s32) = G_CONSTANT i32 0
  91     %1:sgpr(p3) = G_PTRMASK %0, %const
  92     S_ENDPGM 0, implicit %1
  93
  94 ...
  95
  96 ---
  97 name:  ptrmask_p3_s32_sgpr_sgpr_clearhi1
  98 legalized:       true
  99 regBankSelected: true
 100
 101 body: |
 102   bb.0:
 103     liveins: $sgpr0
 104
 105     ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearhi1
 106     ; CHECK: liveins: $sgpr0
 107     ; CHECK-NEXT: {{  $}}
 108     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 109     ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -2147483648
 110     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def dead $scc
 111     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
 112     %0:sgpr(p3) = COPY $sgpr0
 113     %const:sgpr(s32) = G_CONSTANT i32  -2147483648
 114     %1:sgpr(p3) = G_PTRMASK %0, %const
 115     S_ENDPGM 0, implicit %1
 116
 117 ...
 118
 119 ---
 120 name:  ptrmask_p3_s32_sgpr_sgpr_clearhi2
 121 legalized:       true
 122 regBankSelected: true
 123
 124 body: |
 125   bb.0:
 126     liveins: $sgpr0
 127
 128     ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearhi2
 129     ; CHECK: liveins: $sgpr0
 130     ; CHECK-NEXT: {{  $}}
 131     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 132     ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -1073741824
 133     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def dead $scc
 134     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
 135     %0:sgpr(p3) = COPY $sgpr0
 136     %const:sgpr(s32) = G_CONSTANT i32  -1073741824
 137     %1:sgpr(p3) = G_PTRMASK %0, %const
 138     S_ENDPGM 0, implicit %1
 139
 140 ...
 141
 142 ---
 143 name:  ptrmask_p3_s32_sgpr_sgpr_clearlo1
 144 legalized:       true
 145 regBankSelected: true
 146
 147 body: |
 148   bb.0:
 149     liveins: $sgpr0
 150
 151     ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo1
 152     ; CHECK: liveins: $sgpr0
 153     ; CHECK-NEXT: {{  $}}
 154     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 155     ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -2
 156     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def dead $scc
 157     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
 158     %0:sgpr(p3) = COPY $sgpr0
 159     %const:sgpr(s32) = G_CONSTANT i32 -2
 160     %1:sgpr(p3) = G_PTRMASK %0, %const
 161     S_ENDPGM 0, implicit %1
 162
 163 ...
 164
 165 ---
 166 name:  ptrmask_p3_s32_sgpr_sgpr_clearlo2
 167 legalized:       true
 168 regBankSelected: true
 169
 170 body: |
 171   bb.0:
 172     liveins: $sgpr0
 173
 174     ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo2
 175     ; CHECK: liveins: $sgpr0
 176     ; CHECK-NEXT: {{  $}}
 177     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 178     ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -4
 179     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def dead $scc
 180     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
 181     %0:sgpr(p3) = COPY $sgpr0
 182     %const:sgpr(s32) = G_CONSTANT i32 -4
 183     %1:sgpr(p3) = G_PTRMASK %0, %const
 184     S_ENDPGM 0, implicit %1
 185
 186 ...
 187
 188 ---
 189 name:  ptrmask_p3_s32_sgpr_sgpr_clearlo3
 190 legalized:       true
 191 regBankSelected: true
 192
 193 body: |
 194   bb.0:
 195     liveins: $sgpr0
 196
 197     ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo3
 198     ; CHECK: liveins: $sgpr0
 199     ; CHECK-NEXT: {{  $}}
 200     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 201     ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -8
 202     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def dead $scc
 203     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
 204     %0:sgpr(p3) = COPY $sgpr0
 205     %const:sgpr(s32) = G_CONSTANT i32 -8
 206     %1:sgpr(p3) = G_PTRMASK %0, %const
 207     S_ENDPGM 0, implicit %1
 208
 209 ...
 210
 211 ---
 212 name:  ptrmask_p3_s32_sgpr_sgpr_clearlo4
 213 legalized:       true
 214 regBankSelected: true
 215
 216 body: |
 217   bb.0:
 218     liveins: $sgpr0
 219
 220     ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo4
 221     ; CHECK: liveins: $sgpr0
 222     ; CHECK-NEXT: {{  $}}
 223     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 224     ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -16
 225     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def dead $scc
 226     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
 227     %0:sgpr(p3) = COPY $sgpr0
 228     %const:sgpr(s32) = G_CONSTANT i32 -16
 229     %1:sgpr(p3) = G_PTRMASK %0, %const
 230     S_ENDPGM 0, implicit %1
 231
 232 ...
 233
 234 ---
 235 name:  ptrmask_p3_s32_sgpr_sgpr_clearlo29
 236 legalized:       true
 237 regBankSelected: true
 238
 239 body: |
 240   bb.0:
 241     liveins: $sgpr0
 242
 243     ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo29
 244     ; CHECK: liveins: $sgpr0
 245     ; CHECK-NEXT: {{  $}}
 246     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 247     ; CHECK-NEXT: %const:sreg_32 = S_MOV_B32 -536870912
 248     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def dead $scc
 249     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]
 250     %0:sgpr(p3) = COPY $sgpr0
 251     %const:sgpr(s32) = G_CONSTANT i32 -536870912
 252     %1:sgpr(p3) = G_PTRMASK %0, %const
 253     S_ENDPGM 0, implicit %1
 254
 255 ...
 256
 257 ---
 258 name:  ptrmask_p0_s64_sgpr_sgpr_sgpr
 259 legalized:       true
 260 regBankSelected: true
 261
 262 body: |
 263   bb.0:
 264     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 265
 266     ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr
 267     ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 268     ; CHECK-NEXT: {{  $}}
 269     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 270     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 271     ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
 272     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]
 273     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 274     %1:sgpr(s64) = COPY $sgpr2_sgpr3
 275     %2:sgpr(p0) = G_PTRMASK %0, %1
 276     S_ENDPGM 0, implicit %2
 277
 278 ...
 279
 280 ---
 281 name:  ptrmask_p0_s64_sgpr_sgpr_sgpr_0xffffffffffffffff
 282 legalized:       true
 283 regBankSelected: true
 284
 285 body: |
 286   bb.0:
 287     liveins: $sgpr0_sgpr1
 288
 289     ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xffffffffffffffff
 290     ; CHECK: liveins: $sgpr0_sgpr1
 291     ; CHECK-NEXT: {{  $}}
 292     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 293     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 294     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 295     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
 296     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 297     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 298     %1:sgpr(s64) = G_CONSTANT i64 -1
 299     %2:sgpr(p0) = G_PTRMASK %0, %1
 300     S_ENDPGM 0, implicit %2
 301
 302 ...
 303
 304 ---
 305 name:  ptrmask_p0_s64_sgpr_sgpr_sgpr_0x0000000000000000
 306 legalized:       true
 307 regBankSelected: true
 308
 309 body: |
 310   bb.0:
 311     liveins: $sgpr0_sgpr1
 312
 313     ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0x0000000000000000
 314     ; CHECK: liveins: $sgpr0_sgpr1
 315     ; CHECK-NEXT: {{  $}}
 316     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 317     ; CHECK-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
 318     ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[S_MOV_B]], implicit-def dead $scc
 319     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]
 320     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 321     %1:sgpr(s64) = G_CONSTANT i64 0
 322     %2:sgpr(p0) = G_PTRMASK %0, %1
 323     S_ENDPGM 0, implicit %2
 324
 325 ...
 326
 327 ---
 328 name:  ptrmask_p0_s64_sgpr_sgpr_sgpr_0xf0f0f0f0f0f0f0f0
 329 legalized:       true
 330 regBankSelected: true
 331
 332 body: |
 333   bb.0:
 334     liveins: $sgpr0_sgpr1
 335
 336     ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xf0f0f0f0f0f0f0f0
 337     ; CHECK: liveins: $sgpr0_sgpr1
 338     ; CHECK-NEXT: {{  $}}
 339     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 340     ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4042322160
 341     ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -252645136
 342     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
 343     ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[REG_SEQUENCE]], implicit-def dead $scc
 344     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]
 345     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 346     %1:sgpr(s64) = G_CONSTANT i64 -1085102592571150096
 347     %2:sgpr(p0) = G_PTRMASK %0, %1
 348     S_ENDPGM 0, implicit %2
 349
 350 ...
 351
 352 ---
 353 name:  ptrmask_p0_s64_sgpr_sgpr_clearhi1
 354 legalized:       true
 355 regBankSelected: true
 356
 357 body: |
 358   bb.0:
 359     liveins: $sgpr0_sgpr1
 360
 361     ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearhi1
 362     ; CHECK: liveins: $sgpr0_sgpr1
 363     ; CHECK-NEXT: {{  $}}
 364     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 365     ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
 366     ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648
 367     ; CHECK-NEXT: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
 368     ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], %const, implicit-def dead $scc
 369     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]
 370     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 371     %const:sgpr(s64) = G_CONSTANT i64 -9223372036854775808
 372     %1:sgpr(p0) = G_PTRMASK %0, %const
 373     S_ENDPGM 0, implicit %1
 374
 375 ...
 376
 377 ---
 378 name:  ptrmask_p0_s64_sgpr_sgpr_clearhi32
 379 legalized:       true
 380 regBankSelected: true
 381
 382 body: |
 383   bb.0:
 384     liveins: $sgpr0_sgpr1
 385
 386     ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearhi32
 387     ; CHECK: liveins: $sgpr0_sgpr1
 388     ; CHECK-NEXT: {{  $}}
 389     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 390     ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
 391     ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
 392     ; CHECK-NEXT: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
 393     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 394     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 395     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
 396     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
 397     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
 398     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 399     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 400     %const:sgpr(s64) = G_CONSTANT i64 -4294967296
 401     %1:sgpr(p0) = G_PTRMASK %0, %const
 402     S_ENDPGM 0, implicit %1
 403
 404 ...
 405
 406 ---
 407 name:  ptrmask_p0_s64_sgpr_sgpr_clear_32
 408 legalized:       true
 409 regBankSelected: true
 410
 411 body: |
 412   bb.0:
 413     liveins: $sgpr0_sgpr1
 414
 415     ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clear_32
 416     ; CHECK: liveins: $sgpr0_sgpr1
 417     ; CHECK-NEXT: {{  $}}
 418     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 419     ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
 420     ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
 421     ; CHECK-NEXT: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
 422     ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], %const, implicit-def dead $scc
 423     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]
 424     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 425     %const:sgpr(s64) = G_CONSTANT i64 4294967296
 426     %1:sgpr(p0) = G_PTRMASK %0, %const
 427     S_ENDPGM 0, implicit %1
 428
 429 ...
 430
 431 ---
 432 name:  ptrmask_p0_s64_sgpr_sgpr_clearlo1
 433 legalized:       true
 434 regBankSelected: true
 435
 436 body: |
 437   bb.0:
 438     liveins: $sgpr0_sgpr1
 439
 440     ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo1
 441     ; CHECK: liveins: $sgpr0_sgpr1
 442     ; CHECK-NEXT: {{  $}}
 443     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 444     ; CHECK-NEXT: %const:sreg_64 = S_MOV_B64_IMM_PSEUDO -2
 445     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 446     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 447     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
 448     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
 449     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
 450     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 451     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 452     %const:sgpr(s64) = G_CONSTANT i64 -2
 453     %1:sgpr(p0) = G_PTRMASK %0, %const
 454     S_ENDPGM 0, implicit %1
 455
 456 ...
 457
 458 ---
 459 name:  ptrmask_p0_s64_sgpr_sgpr_clearlo2
 460 legalized:       true
 461 regBankSelected: true
 462
 463 body: |
 464   bb.0:
 465     liveins: $sgpr0_sgpr1
 466
 467     ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo2
 468     ; CHECK: liveins: $sgpr0_sgpr1
 469     ; CHECK-NEXT: {{  $}}
 470     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 471     ; CHECK-NEXT: %const:sreg_64 = S_MOV_B64_IMM_PSEUDO -4
 472     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 473     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 474     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
 475     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
 476     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
 477     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 478     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 479     %const:sgpr(s64) = G_CONSTANT i64 -4
 480     %1:sgpr(p0) = G_PTRMASK %0, %const
 481     S_ENDPGM 0, implicit %1
 482
 483 ...
 484
 485 ---
 486 name:  ptrmask_p0_s64_sgpr_sgpr_clearlo3
 487 legalized:       true
 488 regBankSelected: true
 489
 490 body: |
 491   bb.0:
 492     liveins: $sgpr0_sgpr1
 493
 494     ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo3
 495     ; CHECK: liveins: $sgpr0_sgpr1
 496     ; CHECK-NEXT: {{  $}}
 497     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 498     ; CHECK-NEXT: %const:sreg_64 = S_MOV_B64_IMM_PSEUDO -8
 499     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 500     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 501     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
 502     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
 503     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
 504     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 505     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 506     %const:sgpr(s64) = G_CONSTANT i64 -8
 507     %1:sgpr(p0) = G_PTRMASK %0, %const
 508     S_ENDPGM 0, implicit %1
 509
 510 ...
 511
 512 ---
 513 name:  ptrmask_p0_s64_sgpr_sgpr_clearlo4
 514 legalized:       true
 515 regBankSelected: true
 516
 517 body: |
 518   bb.0:
 519     liveins: $sgpr0_sgpr1
 520
 521     ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo4
 522     ; CHECK: liveins: $sgpr0_sgpr1
 523     ; CHECK-NEXT: {{  $}}
 524     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 525     ; CHECK-NEXT: %const:sreg_64 = S_MOV_B64_IMM_PSEUDO -16
 526     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 527     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 528     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
 529     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
 530     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
 531     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 532     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 533     %const:sgpr(s64) = G_CONSTANT i64 -16
 534     %1:sgpr(p0) = G_PTRMASK %0, %const
 535     S_ENDPGM 0, implicit %1
 536
 537 ...
 538
 539 ---
 540 name:  ptrmask_p0_s64_sgpr_sgpr_clearlo29
 541 legalized:       true
 542 regBankSelected: true
 543
 544 body: |
 545   bb.0:
 546     liveins: $sgpr0_sgpr1
 547
 548     ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo29
 549     ; CHECK: liveins: $sgpr0_sgpr1
 550     ; CHECK-NEXT: {{  $}}
 551     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 552     ; CHECK-NEXT: %const:sreg_64 = S_MOV_B64_IMM_PSEUDO -536870912
 553     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 554     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 555     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
 556     ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
 557     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
 558     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 559     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 560     %const:sgpr(s64) = G_CONSTANT i64 -536870912
 561     %1:sgpr(p0) = G_PTRMASK %0, %const
 562     S_ENDPGM 0, implicit %1
 563
 564 ...
 565
 566 ---
 567 name:  ptrmask_p3_vgpr_vgpr_0xf0f0f0f0
 568 legalized:       true
 569 regBankSelected: true
 570
 571 body: |
 572   bb.0:
 573     liveins: $vgpr0
 574
 575     ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_0xf0f0f0f0
 576     ; CHECK: liveins: $vgpr0
 577     ; CHECK-NEXT: {{  $}}
 578     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 579     ; CHECK-NEXT: %const:vgpr_32 = V_MOV_B32_e32 -252645136, implicit $exec
 580     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
 581     ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
 582     %0:vgpr(p3) = COPY $vgpr0
 583     %const:vgpr(s32) = G_CONSTANT i32 -252645136
 584     %1:vgpr(p3) = G_PTRMASK %0, %const
 585     S_ENDPGM 0, implicit %1
 586
 587 ...
 588
 589 ---
 590 name:  ptrmask_p3_vgpr_vgpr_clearlo1
 591 legalized:       true
 592 regBankSelected: true
 593
 594 body: |
 595   bb.0:
 596     liveins: $vgpr0
 597
 598     ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo1
 599     ; CHECK: liveins: $vgpr0
 600     ; CHECK-NEXT: {{  $}}
 601     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 602     ; CHECK-NEXT: %const:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
 603     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
 604     ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
 605     %0:vgpr(p3) = COPY $vgpr0
 606     %const:vgpr(s32) = G_CONSTANT i32 -2
 607     %1:vgpr(p3) = G_PTRMASK %0, %const
 608     S_ENDPGM 0, implicit %1
 609
 610 ...
 611
 612 ---
 613 name:  ptrmask_p3_vgpr_vgpr_clearlo2
 614 legalized:       true
 615 regBankSelected: true
 616
 617 body: |
 618   bb.0:
 619     liveins: $vgpr0
 620
 621     ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo2
 622     ; CHECK: liveins: $vgpr0
 623     ; CHECK-NEXT: {{  $}}
 624     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 625     ; CHECK-NEXT: %const:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
 626     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
 627     ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
 628     %0:vgpr(p3) = COPY $vgpr0
 629     %const:vgpr(s32) = G_CONSTANT i32 -4
 630     %1:vgpr(p3) = G_PTRMASK %0, %const
 631     S_ENDPGM 0, implicit %1
 632
 633 ...
 634
 635 ---
 636 name:  ptrmask_p3_vgpr_vgpr_clearlo3
 637 legalized:       true
 638 regBankSelected: true
 639
 640 body: |
 641   bb.0:
 642     liveins: $vgpr0
 643
 644     ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo3
 645     ; CHECK: liveins: $vgpr0
 646     ; CHECK-NEXT: {{  $}}
 647     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 648     ; CHECK-NEXT: %const:vgpr_32 = V_MOV_B32_e32 -8, implicit $exec
 649     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
 650     ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
 651     %0:vgpr(p3) = COPY $vgpr0
 652     %const:vgpr(s32) = G_CONSTANT i32 -8
 653     %1:vgpr(p3) = G_PTRMASK %0, %const
 654     S_ENDPGM 0, implicit %1
 655
 656 ...
 657
 658 ---
 659 name:  ptrmask_p3_vgpr_vgpr_clearlo4
 660 legalized:       true
 661 regBankSelected: true
 662
 663 body: |
 664   bb.0:
 665     liveins: $vgpr0
 666
 667     ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo4
 668     ; CHECK: liveins: $vgpr0
 669     ; CHECK-NEXT: {{  $}}
 670     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 671     ; CHECK-NEXT: %const:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec
 672     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
 673     ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
 674     %0:vgpr(p3) = COPY $vgpr0
 675     %const:vgpr(s32) = G_CONSTANT i32 -16
 676     %1:vgpr(p3) = G_PTRMASK %0, %const
 677     S_ENDPGM 0, implicit %1
 678
 679 ...
 680
 681 ---
 682 name:  ptrmask_p3_vgpr_vgpr_clearlo29
 683 legalized:       true
 684 regBankSelected: true
 685
 686 body: |
 687   bb.0:
 688     liveins: $vgpr0
 689
 690     ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo29
 691     ; CHECK: liveins: $vgpr0
 692     ; CHECK-NEXT: {{  $}}
 693     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 694     ; CHECK-NEXT: %const:vgpr_32 = V_MOV_B32_e32 -536870912, implicit $exec
 695     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
 696     ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
 697     %0:vgpr(p3) = COPY $vgpr0
 698     %const:vgpr(s32) = G_CONSTANT i32 -536870912
 699     %1:vgpr(p3) = G_PTRMASK %0, %const
 700     S_ENDPGM 0, implicit %1
 701
 702 ...
 703
 704 ---
 705 name:  ptrmask_p0_s64_vgpr_vgpr_vgpr
 706 legalized:       true
 707 regBankSelected: true
 708
 709 body: |
 710   bb.0:
 711     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 712
 713     ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_vgpr
 714     ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 715     ; CHECK-NEXT: {{  $}}
 716     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 717     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
 718     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 719     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 720     ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 721     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], [[COPY4]], implicit $exec
 722     ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 723     ; CHECK-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY3]], [[COPY5]], implicit $exec
 724     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
 725     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 726     %0:vgpr(p0) = COPY $vgpr0_vgpr1
 727     %1:vgpr(s64) = COPY $vgpr2_vgpr3
 728     %2:vgpr(p0) = G_PTRMASK %0, %1
 729     S_ENDPGM 0, implicit %2
 730
 731 ...
 732
 733 ---
 734 name:  ptrmask_p0_s64_vgpr_vgpr_vgpr_0xf0f0f0f0f0f0f0f0
 735 legalized:       true
 736 regBankSelected: true
 737
 738 body: |
 739   bb.0:
 740     liveins: $vgpr0_vgpr1
 741
 742     ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_vgpr_0xf0f0f0f0f0f0f0f0
 743     ; CHECK: liveins: $vgpr0_vgpr1
 744     ; CHECK-NEXT: {{  $}}
 745     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 746     ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4042322160, implicit $exec
 747     ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -252645136, implicit $exec
 748     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
 749     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 750     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 751     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
 752     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
 753     ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
 754     ; CHECK-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], [[COPY4]], implicit $exec
 755     ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
 756     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]
 757     %0:vgpr(p0) = COPY $vgpr0_vgpr1
 758     %1:vgpr(s64) = G_CONSTANT i64 -1085102592571150096
 759     %2:vgpr(p0) = G_PTRMASK %0, %1
 760     S_ENDPGM 0, implicit %2
 761
 762 ...
 763
 764 ---
 765 name:  ptrmask_p0_s64_vgpr_vgpr_clearlo1
 766 legalized:       true
 767 regBankSelected: true
 768
 769 body: |
 770   bb.0:
 771     liveins: $vgpr0_vgpr1
 772
 773     ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo1
 774     ; CHECK: liveins: $vgpr0_vgpr1
 775     ; CHECK-NEXT: {{  $}}
 776     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 777     ; CHECK-NEXT: %const:vreg_64 = V_MOV_B64_PSEUDO -2, implicit $exec
 778     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 779     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 780     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
 781     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
 782     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
 783     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 784     %0:vgpr(p0) = COPY $vgpr0_vgpr1
 785     %const:vgpr(s64) = G_CONSTANT i64 -2
 786     %1:vgpr(p0) = G_PTRMASK %0, %const
 787     S_ENDPGM 0, implicit %1
 788
 789 ...
 790
 791 ---
 792 name:  ptrmask_p0_s64_vgpr_vgpr_clearlo2
 793 legalized:       true
 794 regBankSelected: true
 795
 796 body: |
 797   bb.0:
 798     liveins: $vgpr0_vgpr1
 799
 800     ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo2
 801     ; CHECK: liveins: $vgpr0_vgpr1
 802     ; CHECK-NEXT: {{  $}}
 803     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 804     ; CHECK-NEXT: %const:vreg_64 = V_MOV_B64_PSEUDO -4, implicit $exec
 805     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 806     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 807     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
 808     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
 809     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
 810     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 811     %0:vgpr(p0) = COPY $vgpr0_vgpr1
 812     %const:vgpr(s64) = G_CONSTANT i64 -4
 813     %1:vgpr(p0) = G_PTRMASK %0, %const
 814     S_ENDPGM 0, implicit %1
 815
 816 ...
 817
 818 ---
 819 name:  ptrmask_p0_s64_vgpr_vgpr_clearlo3
 820 legalized:       true
 821 regBankSelected: true
 822
 823 body: |
 824   bb.0:
 825     liveins: $vgpr0_vgpr1
 826
 827     ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo3
 828     ; CHECK: liveins: $vgpr0_vgpr1
 829     ; CHECK-NEXT: {{  $}}
 830     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 831     ; CHECK-NEXT: %const:vreg_64 = V_MOV_B64_PSEUDO -4, implicit $exec
 832     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 833     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 834     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
 835     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
 836     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
 837     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 838     %0:vgpr(p0) = COPY $vgpr0_vgpr1
 839     %const:vgpr(s64) = G_CONSTANT i64 -4
 840     %1:vgpr(p0) = G_PTRMASK %0, %const
 841     S_ENDPGM 0, implicit %1
 842
 843 ...
 844
 845 ---
 846 name:  ptrmask_p0_s64_vgpr_vgpr_clearlo4
 847 legalized:       true
 848 regBankSelected: true
 849
 850 body: |
 851   bb.0:
 852     liveins: $vgpr0_vgpr1
 853
 854     ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo4
 855     ; CHECK: liveins: $vgpr0_vgpr1
 856     ; CHECK-NEXT: {{  $}}
 857     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 858     ; CHECK-NEXT: %const:vreg_64 = V_MOV_B64_PSEUDO -16, implicit $exec
 859     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 860     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 861     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
 862     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
 863     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
 864     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 865     %0:vgpr(p0) = COPY $vgpr0_vgpr1
 866     %const:vgpr(s64) = G_CONSTANT i64 -16
 867     %1:vgpr(p0) = G_PTRMASK %0, %const
 868     S_ENDPGM 0, implicit %1
 869
 870 ...
 871
 872 ---
 873 name:  ptrmask_p0_s64_vgpr_vgpr_clearlo29
 874 legalized:       true
 875 regBankSelected: true
 876
 877 body: |
 878   bb.0:
 879     liveins: $vgpr0_vgpr1
 880
 881     ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo29
 882     ; CHECK: liveins: $vgpr0_vgpr1
 883     ; CHECK-NEXT: {{  $}}
 884     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 885     ; CHECK-NEXT: %const:vreg_64 = V_MOV_B64_PSEUDO -536870912, implicit $exec
 886     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 887     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 888     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
 889     ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
 890     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
 891     ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 892     %0:vgpr(p0) = COPY $vgpr0_vgpr1
 893     %const:vgpr(s64) = G_CONSTANT i64 -536870912
 894     %1:vgpr(p0) = G_PTRMASK %0, %const
 895     S_ENDPGM 0, implicit %1
 896
 897 ...
 898
 899 ---
 900 name:  ptrmask_p3_vgpr_sgpr_clearlo2
 901 legalized:       true
 902 regBankSelected: true
 903
 904 body: |
 905   bb.0:
 906     liveins: $sgpr0
 907
 908     ; CHECK-LABEL: name: ptrmask_p3_vgpr_sgpr_clearlo2
 909     ; CHECK: liveins: $sgpr0
 910     ; CHECK-NEXT: {{  $}}
 911     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
 912     ; CHECK-NEXT: %const:sgpr(s32) = G_CONSTANT i32 -4
 913     ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:vgpr(p3) = G_PTRMASK [[COPY]], %const(s32)
 914     ; CHECK-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p3)
 915     %0:sgpr(p3) = COPY $sgpr0
 916     %const:sgpr(s32) = G_CONSTANT i32 -4
 917     %1:vgpr(p3) = G_PTRMASK %0, %const
 918     S_ENDPGM 0, implicit %1
 919
 920 ...
 921
 922 ---
 923 name:  ptrmask_p0_s64_vgpr_sgpr_clearlo2
 924 legalized:       true
 925 regBankSelected: true
 926
 927 body: |
 928   bb.0:
 929     liveins: $sgpr0_sgpr1
 930
 931     ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_sgpr_clearlo2
 932     ; CHECK: liveins: $sgpr0_sgpr1
 933     ; CHECK-NEXT: {{  $}}
 934     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
 935     ; CHECK-NEXT: %const:sgpr(s32) = G_CONSTANT i32 -4
 936     ; CHECK-NEXT: [[PTRMASK:%[0-9]+]]:vgpr(p0) = G_PTRMASK [[COPY]], %const(s32)
 937     ; CHECK-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p0)
 938     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 939     %const:sgpr(s32) = G_CONSTANT i32 -4
 940     %1:vgpr(p0) = G_PTRMASK %0, %const
 941     S_ENDPGM 0, implicit %1
 942
 943 ...