Bump version to 19.1.0-rc3
[llvm-project.git] / llvm / test / CodeGen / AMDGPU / GlobalISel / inst-select-returnaddress.mir
blob9e50f4d9fccaf8a3fc92cc2b79e02b5128e0a979
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
4 ---
5 name: return_address_already_live_in_copy
6 legalized: true
7 regBankSelected: true
8 tracksRegLiveness: true
9 liveins:
10   - { reg: '$sgpr30_sgpr31', virtual-reg: '%0' }
12 body: |
13   bb.0:
14     liveins: $sgpr30_sgpr31
15     ; CHECK-LABEL: name: return_address_already_live_in_copy
16     ; CHECK: liveins: $sgpr30_sgpr31
17     ; CHECK-NEXT: {{  $}}
18     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
19     ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY]]
20     %0:sgpr(p0) = COPY $sgpr30_sgpr31
21     %1:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
22     S_ENDPGM 0, implicit %0, implicit %1
23 ...
25 ---
26 name: return_address_already_block_live_in_copy_not_mf_life_in
27 legalized: true
28 regBankSelected: true
29 tracksRegLiveness: true
31 body: |
32   bb.0:
33     liveins: $sgpr30_sgpr31
34     ; CHECK-LABEL: name: return_address_already_block_live_in_copy_not_mf_life_in
35     ; CHECK: liveins: $sgpr30_sgpr31
36     ; CHECK-NEXT: {{  $}}
37     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
38     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
39     ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY]]
40     %0:sgpr(p0) = COPY $sgpr30_sgpr31
41     %1:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
42     S_ENDPGM 0, implicit %0, implicit %1
43 ...
45 ---
46 name: return_address_no_live_in
47 legalized: true
48 regBankSelected: true
49 tracksRegLiveness: true
51 body: |
52   bb.0:
54     ; CHECK-LABEL: name: return_address_no_live_in
55     ; CHECK: liveins: $sgpr30_sgpr31
56     ; CHECK-NEXT: {{  $}}
57     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
58     ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]]
59     %0:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
60     S_ENDPGM 0, implicit %0
61 ...
63 ---
64 name: return_address_no_live_in_non_entry_block
65 legalized: true
66 regBankSelected: true
67 tracksRegLiveness: true
69 body: |
70   ; CHECK-LABEL: name: return_address_no_live_in_non_entry_block
71   ; CHECK: bb.0:
72   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
73   ; CHECK-NEXT:   liveins: $sgpr30_sgpr31
74   ; CHECK-NEXT: {{  $}}
75   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
76   ; CHECK-NEXT:   S_BRANCH %bb.1
77   ; CHECK-NEXT: {{  $}}
78   ; CHECK-NEXT: bb.1:
79   ; CHECK-NEXT:   S_ENDPGM 0, implicit [[COPY]]
80   bb.0:
81     G_BR %bb.1
83   bb.1:
84     %0:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
85     S_ENDPGM 0, implicit %0
86 ...
88 ---
89 name: return_address_multi_use
90 legalized: true
91 regBankSelected: true
92 tracksRegLiveness: true
94 body: |
95   ; CHECK-LABEL: name: return_address_multi_use
96   ; CHECK: bb.0:
97   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
98   ; CHECK-NEXT:   liveins: $sgpr30_sgpr31
99   ; CHECK-NEXT: {{  $}}
100   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
101   ; CHECK-NEXT:   S_BRANCH %bb.1
102   ; CHECK-NEXT: {{  $}}
103   ; CHECK-NEXT: bb.1:
104   ; CHECK-NEXT:   S_ENDPGM 0, implicit [[COPY]], implicit [[COPY]]
105   bb.0:
106     %0:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
107     G_BR %bb.1
109   bb.1:
110     %1:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
111     S_ENDPGM 0, implicit %0, implicit %1
115 name: return_address_kernel_is_null
116 legalized: true
117 regBankSelected: true
118 tracksRegLiveness: true
119 machineFunctionInfo:
120   isEntryFunction: true
122 body: |
123   bb.0:
124     ; CHECK-LABEL: name: return_address_kernel_is_null
125     ; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
126     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_MOV_B64_]]
127     %0:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
128     S_ENDPGM 0, implicit %0