llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
   3
   4 ---
   5
   6 name: zext_sgpr_s1_to_sgpr_s16
   7 legalized:       true
   8 regBankSelected: true
   9 body: |
  10   bb.0:
  11     liveins: $sgpr0
  12
  13     ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s16
  14     ; GCN: liveins: $sgpr0
  15     ; GCN-NEXT: {{  $}}
  16     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  17     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def dead $scc
  18     ; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[S_AND_B32_]]
  19     ; GCN-NEXT: $sgpr0 = COPY [[S_SEXT_I32_I16_]]
  20     %0:sgpr(s32) = COPY $sgpr0
  21     %1:sgpr(s1) = G_TRUNC %0
  22     %2:sgpr(s16) = G_ZEXT %1
  23     %3:sgpr(s32) = G_SEXT %2
  24     $sgpr0 = COPY %3
  25 ...
  26
  27 ---
  28
  29 name: zext_sgpr_s1_to_sgpr_s32
  30 legalized:       true
  31 regBankSelected: true
  32 body: |
  33   bb.0:
  34     liveins: $sgpr0
  35
  36     ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s32
  37     ; GCN: liveins: $sgpr0
  38     ; GCN-NEXT: {{  $}}
  39     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  40     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def dead $scc
  41     ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
  42     %0:sgpr(s32) = COPY $sgpr0
  43     %1:sgpr(s1) = G_TRUNC %0
  44     %2:sgpr(s32) = G_ZEXT %1
  45     $sgpr0 = COPY %2
  46 ...
  47
  48 ---
  49
  50 name: zext_sgpr_s1_to_sgpr_s64
  51 legalized:       true
  52 regBankSelected: true
  53 body: |
  54   bb.0:
  55     liveins: $sgpr0
  56
  57     ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s64
  58     ; GCN: liveins: $sgpr0
  59     ; GCN-NEXT: {{  $}}
  60     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  61     ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  62     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
  63     ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc
  64     ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
  65     %0:sgpr(s32) = COPY $sgpr0
  66     %1:sgpr(s1) = G_TRUNC %0
  67     %2:sgpr(s64) = G_ZEXT %1
  68     $sgpr0_sgpr1 = COPY %2
  69 ...
  70
  71 ---
  72
  73 name: zext_sgpr_s16_to_sgpr_s32
  74 legalized:       true
  75 regBankSelected: true
  76 body: |
  77   bb.0:
  78     liveins: $sgpr0
  79
  80     ; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s32
  81     ; GCN: liveins: $sgpr0
  82     ; GCN-NEXT: {{  $}}
  83     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  84     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  85     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def dead $scc
  86     ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
  87     %0:sgpr(s32) = COPY $sgpr0
  88     %1:sgpr(s16) = G_TRUNC %0
  89     %2:sgpr(s32) = G_ZEXT %1
  90     $sgpr0 = COPY %2
  91
  92 ...
  93
  94 ---
  95
  96 name: zext_sgpr_s16_to_sgpr_s64
  97 legalized:       true
  98 regBankSelected: true
  99 body: |
 100   bb.0:
 101     liveins: $sgpr0
 102
 103     ; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s64
 104     ; GCN: liveins: $sgpr0
 105     ; GCN-NEXT: {{  $}}
 106     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 107     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
 108     ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
 109     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_1]], implicit-def dead $scc
 110     ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[S_AND_B32_]]
 111     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1
 112     ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
 113     %0:sgpr(s32) = COPY $sgpr0
 114     %1:sgpr(s16) = G_TRUNC %0
 115     %2:sgpr(s64) = G_ZEXT %1
 116     $sgpr0_sgpr1 = COPY %2
 117
 118 ...
 119
 120 ---
 121
 122 name: zext_sgpr_s32_to_sgpr_s64
 123 legalized:       true
 124 regBankSelected: true
 125 body: |
 126   bb.0:
 127     liveins: $sgpr0
 128
 129     ; GCN-LABEL: name: zext_sgpr_s32_to_sgpr_s64
 130     ; GCN: liveins: $sgpr0
 131     ; GCN-NEXT: {{  $}}
 132     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY $sgpr0
 133     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
 134     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1
 135     ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
 136     %0:sgpr(s32) = COPY $sgpr0
 137     %1:sgpr(s64) = G_ZEXT %0
 138     $sgpr0_sgpr1 = COPY %1
 139
 140 ...
 141
 142 # ---
 143
 144 # name: zext_vcc_s1_to_vgpr_s32
 145 # legalized:       true
 146 # regBankSelected: true
 147 # body: |
 148 #   bb.0:
 149 #     liveins: $vgpr0
 150
 151 #     %0:vgpr(s32) = COPY $vgpr0
 152 #     %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
 153 #     %2:vgpr(s32) = G_ZEXT %1
 154 #     $vgpr0 = COPY %2
 155 # ...
 156
 157 ---
 158
 159 name: zext_vgpr_s1_to_vgpr_s16
 160 legalized:       true
 161 regBankSelected: true
 162 body: |
 163   bb.0:
 164     liveins: $vgpr0
 165
 166     ; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s16
 167     ; GCN: liveins: $vgpr0
 168     ; GCN-NEXT: {{  $}}
 169     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 170     ; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
 171     ; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[V_AND_B32_e32_]], 0, 16, implicit $exec
 172     ; GCN-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]]
 173     %0:vgpr(s32) = COPY $vgpr0
 174     %1:vgpr(s1) = G_TRUNC %0
 175     %2:vgpr(s16) = G_ZEXT %1
 176     %3:vgpr(s32) = G_SEXT %2
 177     $vgpr0 = COPY %3
 178 ...
 179
 180 ---
 181
 182 name: zext_vgpr_s1_to_vgpr_s32
 183 legalized:       true
 184 regBankSelected: true
 185 body: |
 186   bb.0:
 187     liveins: $vgpr0
 188
 189     ; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s32
 190     ; GCN: liveins: $vgpr0
 191     ; GCN-NEXT: {{  $}}
 192     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 193     ; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
 194     ; GCN-NEXT: $vgpr0 = COPY [[V_AND_B32_e32_]]
 195     %0:vgpr(s32) = COPY $vgpr0
 196     %1:vgpr(s1) = G_TRUNC %0
 197     %2:vgpr(s32) = G_ZEXT %1
 198     $vgpr0 = COPY %2
 199 ...
 200
 201 ---
 202
 203 name: zext_vgpr_s16_to_vgpr_s32
 204 legalized:       true
 205 regBankSelected: true
 206 body: |
 207   bb.0:
 208     liveins: $vgpr0
 209
 210     ; GCN-LABEL: name: zext_vgpr_s16_to_vgpr_s32
 211     ; GCN: liveins: $vgpr0
 212     ; GCN-NEXT: {{  $}}
 213     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 214     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
 215     ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 216     ; GCN-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 217     %0:vgpr(s32) = COPY $vgpr0
 218     %1:vgpr(s16) = G_TRUNC %0
 219     %2:vgpr(s32) = G_ZEXT %1
 220     $vgpr0 = COPY %2
 221
 222 ...
 223
 224 ---
 225
 226 name: zext_sgpr_reg_class_s1_to_sgpr_s32
 227 legalized:       true
 228 regBankSelected: true
 229 body: |
 230   bb.0:
 231     liveins: $sgpr0
 232
 233     ; GCN-LABEL: name: zext_sgpr_reg_class_s1_to_sgpr_s32
 234     ; GCN: liveins: $sgpr0
 235     ; GCN-NEXT: {{  $}}
 236     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 237     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def dead $scc
 238     ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 239     %0:sgpr(s32) = COPY $sgpr0
 240     %1:sreg_32(s1) = G_TRUNC %0
 241     %2:sgpr(s32) = G_ZEXT %1
 242     $sgpr0 = COPY %2
 243 ...