| blob | e2dab03e410aaaaa1a709612d727c4a0b0b56d99 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX906 %s
3 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX908 %s
4 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
5 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
7 define i32 @v_sdot2(<2 x i16> %a, <2 x i16> %b, i32 %c) {
8 ; GFX906-LABEL: v_sdot2:
9 ; GFX906: ; %bb.0:
10 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, v2
12 ; GFX906-NEXT: s_setpc_b64 s[30:31]
13 ;
14 ; GFX908-LABEL: v_sdot2:
15 ; GFX908: ; %bb.0:
16 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
17 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v2, v0, v1
18 ; GFX908-NEXT: v_mov_b32_e32 v0, v2
19 ; GFX908-NEXT: s_setpc_b64 s[30:31]
20 ;
21 ; GFX10-LABEL: v_sdot2:
22 ; GFX10: ; %bb.0:
23 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
24 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2
25 ; GFX10-NEXT: s_setpc_b64 s[30:31]
26 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %b, i32 %c, i1 false)
27 ret i32 %r
28 }
30 define i32 @v_sdot2_clamp(<2 x i16> %a, <2 x i16> %b, i32 %c) {
31 ; GFX906-LABEL: v_sdot2_clamp:
32 ; GFX906: ; %bb.0:
33 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
34 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 clamp
35 ; GFX906-NEXT: s_setpc_b64 s[30:31]
36 ;
37 ; GFX908-LABEL: v_sdot2_clamp:
38 ; GFX908: ; %bb.0:
39 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
40 ; GFX908-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 clamp
41 ; GFX908-NEXT: s_setpc_b64 s[30:31]
42 ;
43 ; GFX10-LABEL: v_sdot2_clamp:
44 ; GFX10: ; %bb.0:
45 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
46 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 clamp
47 ; GFX10-NEXT: s_setpc_b64 s[30:31]
48 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %b, i32 %c, i1 true)
49 ret i32 %r
50 }
52 define amdgpu_ps float @v_sdot2_sgpr_sgpr_sgpr(<2 x i16> inreg %a, <2 x i16> inreg %b, i32 inreg %c) {
53 ; GFX906-LABEL: v_sdot2_sgpr_sgpr_sgpr:
54 ; GFX906: ; %bb.0:
55 ; GFX906-NEXT: v_mov_b32_e32 v0, s1
56 ; GFX906-NEXT: v_mov_b32_e32 v1, s2
57 ; GFX906-NEXT: v_dot2_i32_i16 v0, s0, v0, v1
58 ; GFX906-NEXT: ; return to shader part epilog
59 ;
60 ; GFX908-LABEL: v_sdot2_sgpr_sgpr_sgpr:
61 ; GFX908: ; %bb.0:
62 ; GFX908-NEXT: v_mov_b32_e32 v1, s1
63 ; GFX908-NEXT: v_mov_b32_e32 v0, s2
64 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v0, s0, v1
65 ; GFX908-NEXT: ; return to shader part epilog
66 ;
67 ; GFX10-LABEL: v_sdot2_sgpr_sgpr_sgpr:
68 ; GFX10: ; %bb.0:
69 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
70 ; GFX10-NEXT: v_dot2_i32_i16 v0, s0, s1, v0
71 ; GFX10-NEXT: ; return to shader part epilog
72 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %b, i32 %c, i1 false)
73 %cast = bitcast i32 %r to float
74 ret float %cast
75 }
77 define i32 @v_sdot2_inline_literal_a(<2 x i16> %b, i32 %c) {
78 ; GFX906-LABEL: v_sdot2_inline_literal_a:
79 ; GFX906: ; %bb.0:
80 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
81 ; GFX906-NEXT: v_dot2_i32_i16 v0, 4, v0, v1 op_sel_hi:[0,1,1]
82 ; GFX906-NEXT: s_setpc_b64 s[30:31]
83 ;
84 ; GFX908-LABEL: v_sdot2_inline_literal_a:
85 ; GFX908: ; %bb.0:
86 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
87 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v1, 0x40004, v0
88 ; GFX908-NEXT: v_mov_b32_e32 v0, v1
89 ; GFX908-NEXT: s_setpc_b64 s[30:31]
90 ;
91 ; GFX10-LABEL: v_sdot2_inline_literal_a:
92 ; GFX10: ; %bb.0:
93 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
94 ; GFX10-NEXT: v_dot2_i32_i16 v0, 4, v0, v1 op_sel_hi:[0,1,1]
95 ; GFX10-NEXT: s_setpc_b64 s[30:31]
96 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> <i16 4, i16 4>, <2 x i16> %b, i32 %c, i1 false)
97 ret i32 %r
98 }
100 define i32 @v_sdot2_inline_literal_b(<2 x i16> %a, i32 %c) {
101 ; GFX906-LABEL: v_sdot2_inline_literal_b:
102 ; GFX906: ; %bb.0:
103 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
104 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, 4, v1 op_sel_hi:[1,0,1]
105 ; GFX906-NEXT: s_setpc_b64 s[30:31]
106 ;
107 ; GFX908-LABEL: v_sdot2_inline_literal_b:
108 ; GFX908: ; %bb.0:
109 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
110 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v1, 0x40004, v0
111 ; GFX908-NEXT: v_mov_b32_e32 v0, v1
112 ; GFX908-NEXT: s_setpc_b64 s[30:31]
113 ;
114 ; GFX10-LABEL: v_sdot2_inline_literal_b:
115 ; GFX10: ; %bb.0:
116 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
117 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, 4, v1 op_sel_hi:[1,0,1]
118 ; GFX10-NEXT: s_setpc_b64 s[30:31]
119 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> <i16 4, i16 4>, i32 %c, i1 false)
120 ret i32 %r
121 }
123 define i32 @v_sdot2_inline_literal_a_b(<2 x i16> %a, i32 %c) {
124 ; GFX906-LABEL: v_sdot2_inline_literal_a_b:
125 ; GFX906: ; %bb.0:
126 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
127 ; GFX906-NEXT: v_dot2_i32_i16 v0, 8, 4, v1 op_sel_hi:[0,0,1]
128 ; GFX906-NEXT: s_setpc_b64 s[30:31]
129 ;
130 ; GFX908-LABEL: v_sdot2_inline_literal_a_b:
131 ; GFX908: ; %bb.0:
132 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
133 ; GFX908-NEXT: v_mov_b32_e32 v0, v1
134 ; GFX908-NEXT: v_mov_b32_e32 v1, 0x40004
135 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v0, 0x80008, v1
136 ; GFX908-NEXT: s_setpc_b64 s[30:31]
137 ;
138 ; GFX10-LABEL: v_sdot2_inline_literal_a_b:
139 ; GFX10: ; %bb.0:
140 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
141 ; GFX10-NEXT: v_dot2_i32_i16 v0, 8, 4, v1 op_sel_hi:[0,0,1]
142 ; GFX10-NEXT: s_setpc_b64 s[30:31]
143 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> <i16 8, i16 8>, <2 x i16> <i16 4, i16 4>, i32 %c, i1 false)
144 ret i32 %r
145 }
147 define i32 @v_sdot2_inline_literal_a_b_c() {
148 ; GFX906-LABEL: v_sdot2_inline_literal_a_b_c:
149 ; GFX906: ; %bb.0:
150 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
151 ; GFX906-NEXT: v_dot2_i32_i16 v0, 8, 4, 8 op_sel_hi:[0,0,1]
152 ; GFX906-NEXT: s_setpc_b64 s[30:31]
153 ;
154 ; GFX908-LABEL: v_sdot2_inline_literal_a_b_c:
155 ; GFX908: ; %bb.0:
156 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
157 ; GFX908-NEXT: v_mov_b32_e32 v1, 0x40004
158 ; GFX908-NEXT: v_mov_b32_e32 v0, 8
159 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v0, 0x80008, v1
160 ; GFX908-NEXT: s_setpc_b64 s[30:31]
161 ;
162 ; GFX10-LABEL: v_sdot2_inline_literal_a_b_c:
163 ; GFX10: ; %bb.0:
164 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
165 ; GFX10-NEXT: v_dot2_i32_i16 v0, 8, 4, 8 op_sel_hi:[0,0,1]
166 ; GFX10-NEXT: s_setpc_b64 s[30:31]
167 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> <i16 8, i16 8>, <2 x i16> <i16 4, i16 4>, i32 8, i1 false)
168 ret i32 %r
169 }
171 define i32 @v_sdot2_inline_literal_c(<2 x i16> %a, <2 x i16> %b) {
172 ; GFX906-LABEL: v_sdot2_inline_literal_c:
173 ; GFX906: ; %bb.0:
174 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
175 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, 7
176 ; GFX906-NEXT: s_setpc_b64 s[30:31]
177 ;
178 ; GFX908-LABEL: v_sdot2_inline_literal_c:
179 ; GFX908: ; %bb.0:
180 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
181 ; GFX908-NEXT: v_mov_b32_e32 v2, 7
182 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v2, v0, v1
183 ; GFX908-NEXT: v_mov_b32_e32 v0, v2
184 ; GFX908-NEXT: s_setpc_b64 s[30:31]
185 ;
186 ; GFX10-LABEL: v_sdot2_inline_literal_c:
187 ; GFX10: ; %bb.0:
188 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
189 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, 7
190 ; GFX10-NEXT: s_setpc_b64 s[30:31]
191 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %b, i32 7, i1 false)
192 ret i32 %r
193 }
195 define i32 @v_sdot2_fneg_a(<2 x half> %a, <2 x i16> %b, i32 %c) {
196 ; GFX906-LABEL: v_sdot2_fneg_a:
197 ; GFX906: ; %bb.0:
198 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
199 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
200 ; GFX906-NEXT: s_setpc_b64 s[30:31]
201 ;
202 ; GFX908-LABEL: v_sdot2_fneg_a:
203 ; GFX908: ; %bb.0:
204 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
205 ; GFX908-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
206 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v2, v0, v1
207 ; GFX908-NEXT: v_mov_b32_e32 v0, v2
208 ; GFX908-NEXT: s_setpc_b64 s[30:31]
209 ;
210 ; GFX10-LABEL: v_sdot2_fneg_a:
211 ; GFX10: ; %bb.0:
212 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
213 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
214 ; GFX10-NEXT: s_setpc_b64 s[30:31]
215 %neg.a = fneg <2 x half> %a
216 %cast.neg.a = bitcast <2 x half> %neg.a to <2 x i16>
217 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %cast.neg.a, <2 x i16> %b, i32 %c, i1 false)
218 ret i32 %r
219 }
221 define i32 @v_sdot2_fneg_b(<2 x i16> %a, <2 x half> %b, i32 %c) {
222 ; GFX906-LABEL: v_sdot2_fneg_b:
223 ; GFX906: ; %bb.0:
224 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
225 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
226 ; GFX906-NEXT: s_setpc_b64 s[30:31]
227 ;
228 ; GFX908-LABEL: v_sdot2_fneg_b:
229 ; GFX908: ; %bb.0:
230 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
231 ; GFX908-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
232 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v2, v0, v1
233 ; GFX908-NEXT: v_mov_b32_e32 v0, v2
234 ; GFX908-NEXT: s_setpc_b64 s[30:31]
235 ;
236 ; GFX10-LABEL: v_sdot2_fneg_b:
237 ; GFX10: ; %bb.0:
238 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
239 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
240 ; GFX10-NEXT: s_setpc_b64 s[30:31]
241 %neg.b = fneg <2 x half> %b
242 %cast.neg.b = bitcast <2 x half> %neg.b to <2 x i16>
243 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %cast.neg.b, i32 %c, i1 false)
244 ret i32 %r
245 }
247 define i32 @v_sdot2_fnegf32_c(<2 x i16> %a, <2 x i16> %b, float %c) {
248 ; GFX906-LABEL: v_sdot2_fnegf32_c:
249 ; GFX906: ; %bb.0:
250 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
251 ; GFX906-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
252 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, v2
253 ; GFX906-NEXT: s_setpc_b64 s[30:31]
254 ;
255 ; GFX908-LABEL: v_sdot2_fnegf32_c:
256 ; GFX908: ; %bb.0:
257 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
258 ; GFX908-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
259 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v2, v0, v1
260 ; GFX908-NEXT: v_mov_b32_e32 v0, v2
261 ; GFX908-NEXT: s_setpc_b64 s[30:31]
262 ;
263 ; GFX10-LABEL: v_sdot2_fnegf32_c:
264 ; GFX10: ; %bb.0:
265 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
266 ; GFX10-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
267 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2
268 ; GFX10-NEXT: s_setpc_b64 s[30:31]
269 %neg.c = fneg float %c
270 %cast.neg.c = bitcast float %neg.c to i32
271 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %b, i32 %cast.neg.c, i1 false)
272 ret i32 %r
273 }
275 define i32 @v_sdot2_fnegv2f16_c(<2 x i16> %a, <2 x i16> %b, <2 x half> %c) {
276 ; GFX906-LABEL: v_sdot2_fnegv2f16_c:
277 ; GFX906: ; %bb.0:
278 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
279 ; GFX906-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
280 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, v2
281 ; GFX906-NEXT: s_setpc_b64 s[30:31]
282 ;
283 ; GFX908-LABEL: v_sdot2_fnegv2f16_c:
284 ; GFX908: ; %bb.0:
285 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
286 ; GFX908-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
287 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v2, v0, v1
288 ; GFX908-NEXT: v_mov_b32_e32 v0, v2
289 ; GFX908-NEXT: s_setpc_b64 s[30:31]
290 ;
291 ; GFX10-LABEL: v_sdot2_fnegv2f16_c:
292 ; GFX10: ; %bb.0:
293 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
294 ; GFX10-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
295 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2
296 ; GFX10-NEXT: s_setpc_b64 s[30:31]
297 %neg.c = fneg <2 x half> %c
298 %cast.neg.c = bitcast <2 x half> %neg.c to i32
299 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %b, i32 %cast.neg.c, i1 false)
300 ret i32 %r
301 }
303 define i32 @v_sdot2_shuffle10_a(<2 x i16> %a, <2 x i16> %b, i32 %c) {
304 ; GFX906-LABEL: v_sdot2_shuffle10_a:
305 ; GFX906: ; %bb.0:
306 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
307 ; GFX906-NEXT: v_alignbit_b32 v0, v0, v0, 16
308 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, v2
309 ; GFX906-NEXT: s_setpc_b64 s[30:31]
310 ;
311 ; GFX908-LABEL: v_sdot2_shuffle10_a:
312 ; GFX908: ; %bb.0:
313 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
314 ; GFX908-NEXT: v_alignbit_b32 v0, v0, v0, 16
315 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v2, v0, v1
316 ; GFX908-NEXT: v_mov_b32_e32 v0, v2
317 ; GFX908-NEXT: s_setpc_b64 s[30:31]
318 ;
319 ; GFX10-LABEL: v_sdot2_shuffle10_a:
320 ; GFX10: ; %bb.0:
321 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
322 ; GFX10-NEXT: v_alignbit_b32 v0, v0, v0, 16
323 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2
324 ; GFX10-NEXT: s_setpc_b64 s[30:31]
325 %shuf.a = shufflevector <2 x i16> %a, <2 x i16> undef, <2 x i32> <i32 1, i32 0>
326 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %shuf.a, <2 x i16> %b, i32 %c, i1 false)
327 ret i32 %r
328 }
330 define i32 @v_sdot2_shuffle10_b(<2 x i16> %a, <2 x i16> %b, i32 %c) {
331 ; GFX906-LABEL: v_sdot2_shuffle10_b:
332 ; GFX906: ; %bb.0:
333 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
334 ; GFX906-NEXT: v_alignbit_b32 v1, v1, v1, 16
335 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, v2
336 ; GFX906-NEXT: s_setpc_b64 s[30:31]
337 ;
338 ; GFX908-LABEL: v_sdot2_shuffle10_b:
339 ; GFX908: ; %bb.0:
340 ; GFX908-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
341 ; GFX908-NEXT: v_alignbit_b32 v1, v1, v1, 16
342 ; GFX908-NEXT: v_dot2c_i32_i16_e32 v2, v0, v1
343 ; GFX908-NEXT: v_mov_b32_e32 v0, v2
344 ; GFX908-NEXT: s_setpc_b64 s[30:31]
345 ;
346 ; GFX10-LABEL: v_sdot2_shuffle10_b:
347 ; GFX10: ; %bb.0:
348 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
349 ; GFX10-NEXT: v_alignbit_b32 v1, v1, v1, 16
350 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2
351 ; GFX10-NEXT: s_setpc_b64 s[30:31]
352 %shuf.b = shufflevector <2 x i16> %b, <2 x i16> undef, <2 x i32> <i32 1, i32 0>
353 %r = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %shuf.b, i32 %c, i1 false)
354 ret i32 %r
355 }
357 declare i32 @llvm.amdgcn.sdot2(<2 x i16>, <2 x i16>, i32, i1 immarg) #0
359 attributes #0 = { nounwind readnone speculatable }