1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX906 %s
3 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10PLUS %s
4 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10PLUS %s
5 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10PLUS %s
7 define i32 @v_udot8(i32 %a, i32 %b, i32 %c) {
8 ; GFX906-LABEL: v_udot8:
10 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11 ; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
12 ; GFX906-NEXT: s_setpc_b64 s[30:31]
14 ; GFX10PLUS-LABEL: v_udot8:
16 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
17 ; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
18 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
19 %r = call i32 @llvm.amdgcn.udot8(i32 %a, i32 %b, i32 %c, i1 false)
23 define i32 @v_udot8_clamp(i32 %a, i32 %b, i32 %c) {
24 ; GFX906-LABEL: v_udot8_clamp:
26 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
27 ; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2 clamp
28 ; GFX906-NEXT: s_setpc_b64 s[30:31]
30 ; GFX10PLUS-LABEL: v_udot8_clamp:
32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
33 ; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2 clamp
34 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
35 %r = call i32 @llvm.amdgcn.udot8(i32 %a, i32 %b, i32 %c, i1 true)
39 ; FIXME: Fix argument do not let these casts expand
40 ; define i32 @v_udot8_cast_v8i4(<8 x i4> %a, <8 x i4> %b, i32 %c) {
41 ; %a.cast = bitcast <8 x i4> %a to i32
42 ; %b.cast = bitcast <8 x i4> %b to i32
43 ; %r = call i32 @llvm.amdgcn.udot8(i32 %a.cast, i32 %b.cast, i32 %c, i1 false)
47 define i32 @v_udot8_fnegf32_a(float %a, i32 %b, i32 %c) {
48 ; GFX906-LABEL: v_udot8_fnegf32_a:
50 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
51 ; GFX906-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
52 ; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
53 ; GFX906-NEXT: s_setpc_b64 s[30:31]
55 ; GFX10PLUS-LABEL: v_udot8_fnegf32_a:
57 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
58 ; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
59 ; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
60 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
61 %neg.a = fneg float %a
62 %cast.neg.a = bitcast float %neg.a to i32
63 %r = call i32 @llvm.amdgcn.udot8(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
67 define i32 @v_udot8_fnegv2f16_a(<2 x half> %a, i32 %b, i32 %c) {
68 ; GFX906-LABEL: v_udot8_fnegv2f16_a:
70 ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
71 ; GFX906-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
72 ; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
73 ; GFX906-NEXT: s_setpc_b64 s[30:31]
75 ; GFX10PLUS-LABEL: v_udot8_fnegv2f16_a:
77 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
78 ; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
79 ; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
80 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
81 %neg.a = fneg <2 x half> %a
82 %cast.neg.a = bitcast <2 x half> %neg.a to i32
83 %r = call i32 @llvm.amdgcn.udot8(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
87 declare i32 @llvm.amdgcn.udot8(i32, i32, i32, i1 immarg) #0
89 attributes #0 = { nounwind readnone speculatable }