llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
   3 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
   4
   5 ---
   6 name: class_ss
   7 legalized: true
   8
   9 body: |
  10   bb.0:
  11     liveins: $sgpr0_sgpr1, $sgpr2
  12     ; CHECK-LABEL: name: class_ss
  13     ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
  14     ; CHECK-NEXT: {{  $}}
  15     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
  16     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  17     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
  18     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
  19     ; CHECK-NEXT: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY2]](s64), [[COPY3]](s32)
  20     %0:_(s64) = COPY $sgpr0_sgpr1
  21     %1:_(s32) = COPY $sgpr2
  22     %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
  23 ...
  24
  25 ---
  26 name: class_sv
  27 legalized: true
  28
  29 body: |
  30   bb.0:
  31     liveins: $sgpr0_sgpr1, $vgpr0
  32
  33     ; CHECK-LABEL: name: class_sv
  34     ; CHECK: liveins: $sgpr0_sgpr1, $vgpr0
  35     ; CHECK-NEXT: {{  $}}
  36     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
  37     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  38     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
  39     ; CHECK-NEXT: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY2]](s64), [[COPY1]](s32)
  40     %0:_(s64) = COPY $sgpr0_sgpr1
  41     %1:_(s32) = COPY $vgpr0
  42     %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
  43 ...
  44
  45 ---
  46 name: class_vs
  47 legalized: true
  48
  49 body: |
  50   bb.0:
  51     liveins: $vgpr0_vgpr1, $sgpr0
  52     ; CHECK-LABEL: name: class_vs
  53     ; CHECK: liveins: $vgpr0_vgpr1, $sgpr0
  54     ; CHECK-NEXT: {{  $}}
  55     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
  56     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
  57     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
  58     ; CHECK-NEXT: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY2]](s32)
  59     %0:_(s64) = COPY $vgpr0_vgpr1
  60     %1:_(s32) = COPY $sgpr0
  61     %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
  62 ...
  63
  64 ---
  65 name: class_vv
  66 legalized: true
  67
  68 body: |
  69   bb.0:
  70     liveins: $vgpr0, $vgpr1
  71     ; CHECK-LABEL: name: class_vv
  72     ; CHECK: liveins: $vgpr0, $vgpr1
  73     ; CHECK-NEXT: {{  $}}
  74     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
  75     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
  76     ; CHECK-NEXT: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32)
  77     %0:_(s64) = COPY $vgpr0_vgpr1
  78     %1:_(s32) = COPY $vgpr2
  79     %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
  80 ...