llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast  -verify-machineinstrs %s -o - | FileCheck %s
   3 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy  -verify-machineinstrs %s -o - | FileCheck %s
   4
   5 ---
   6 name: ds_consume_s
   7 legalized: true
   8 tracksRegLiveness: true
   9 body: |
  10   bb.0:
  11     liveins: $sgpr0
  12     ; CHECK-LABEL: name: ds_consume_s
  13     ; CHECK: liveins: $sgpr0
  14     ; CHECK-NEXT: {{  $}}
  15     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
  16     ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.consume), [[COPY]](p3), 0
  17     %0:_(p3) = COPY $sgpr0
  18     %1:_(s32) = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.consume), %0, 0
  19
  20 ...
  21
  22 ---
  23 name: ds_consume_v
  24 legalized: true
  25 tracksRegLiveness: true
  26 body: |
  27   bb.0:
  28     liveins: $vgpr0
  29     ; CHECK-LABEL: name: ds_consume_v
  30     ; CHECK: liveins: $vgpr0
  31     ; CHECK-NEXT: {{  $}}
  32     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(p3) = COPY $vgpr0
  33     ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(p3) = V_READFIRSTLANE_B32 [[COPY]](p3), implicit $exec
  34     ; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.consume), [[V_READFIRSTLANE_B32_]](p3), 0
  35     %0:_(p3) = COPY $vgpr0
  36     %1:_(s32) = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.consume), %0, 0
  37
  38 ...