llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
   3 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
   4
   5 ---
   6 name: ds_gws_init_s
   7 legalized: true
   8 tracksRegLiveness: true
   9
  10 body: |
  11   bb.0:
  12     liveins: $sgpr0
  13     ; CHECK-LABEL: name: ds_gws_init_s
  14     ; CHECK: liveins: $sgpr0
  15     ; CHECK-NEXT: {{  $}}
  16     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
  17     ; CHECK-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.v), [[COPY]](s32)
  18     %0:_(s32) = COPY $sgpr0
  19     G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.v), %0
  20 ...
  21
  22 ---
  23 name: ds_gws_init_v
  24 legalized: true
  25 tracksRegLiveness: true
  26
  27 body: |
  28   bb.0:
  29     liveins: $vgpr0
  30     ; CHECK-LABEL: name: ds_gws_init_v
  31     ; CHECK: liveins: $vgpr0
  32     ; CHECK-NEXT: {{  $}}
  33     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
  34     ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
  35     ; CHECK-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.v), [[V_READFIRSTLANE_B32_]](s32)
  36     %0:_(s32) = COPY $vgpr0
  37     G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.v), %0
  38 ...
  39