llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
   3 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
   4 ---
   5 name: else
   6 legalized: true
   7
   8 body: |
   9   bb.0:
  10     liveins: $sgpr0_sgpr1
  11     ; CHECK-LABEL: name: else
  12     ; CHECK: liveins: $sgpr0_sgpr1
  13     ; CHECK-NEXT: {{  $}}
  14     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
  15     ; CHECK-NEXT: [[INT:%[0-9]+]]:vcc(s1), [[INT1:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.else), [[COPY]](s64)
  16     %0:_(s64) = COPY $sgpr0_sgpr1
  17     %1:_(s1), %2:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.else), %0
  18
  19 ...