llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
   3 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
   4
   5 ---
   6 name: sendmsghalt_s
   7 legalized: true
   8
   9 body: |
  10   bb.0:
  11     liveins: $sgpr0
  12     ; CHECK-LABEL: name: sendmsghalt_s
  13     ; CHECK: liveins: $sgpr0
  14     ; CHECK-NEXT: {{  $}}
  15     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
  16     ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.sendmsghalt), 0, [[COPY]](s32)
  17     %0:_(s32) = COPY $sgpr0
  18     G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.sendmsghalt), 0, %0
  19 ...
  20
  21 ---
  22 name: sendmsghalt_v
  23 legalized: true
  24
  25 body: |
  26   bb.0:
  27     liveins: $vgpr0
  28     ; CHECK-LABEL: name: sendmsghalt_v
  29     ; CHECK: liveins: $vgpr0
  30     ; CHECK-NEXT: {{  $}}
  31     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
  32     ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
  33     ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.sendmsghalt), 0, [[V_READFIRSTLANE_B32_]](s32)
  34     %0:_(s32) = COPY $vgpr0
  35     G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.sendmsghalt), 0, %0
  36 ...