llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck %s
   3 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck %s
   4
   5 # TODO: We could use scalar
   6 ---
   7 name: amdgpu_wave_address
   8 legalized: true
   9 body: |
  10   bb.0:
  11     ; CHECK-LABEL: name: amdgpu_wave_address
  12     ; CHECK: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:sgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
  13     ; CHECK-NEXT: S_ENDPGM 0, implicit [[AMDGPU_WAVE_ADDRESS]](p5)
  14     %0:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
  15     S_ENDPGM 0, implicit %0
  16 ...
  17
  18 # TODO: Should infer v here
  19 ---
  20 name: amdgpu_wave_address_v
  21 legalized: true
  22 body: |
  23   bb.0:
  24     ; CHECK-LABEL: name: amdgpu_wave_address_v
  25     ; CHECK: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
  26     ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:sgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
  27     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p5) = COPY [[AMDGPU_WAVE_ADDRESS]](p5)
  28     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
  29     ; CHECK-NEXT: G_STORE [[COPY]](p5), [[COPY1]](p1) :: (store (p5), addrspace 1)
  30     %0:_(p1) = G_IMPLICIT_DEF
  31     %1:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
  32     G_STORE %1, %0 :: (store (p5), addrspace 1)
  33 ...