| blob | 94d704fa3f92d6c9df4c520a0114913a80de9111 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2 ; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6 %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
4 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
5 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
6 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
7 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s
9 define amdgpu_kernel void @s_add_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
10 ; GFX6-LABEL: s_add_i32:
11 ; GFX6: ; %bb.0:
12 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
13 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
14 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
15 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
16 ; GFX6-NEXT: s_mov_b32 s2, -1
17 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
18 ; GFX6-NEXT: s_add_i32 s4, s4, s5
19 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
20 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
21 ; GFX6-NEXT: s_endpgm
22 ;
23 ; GFX8-LABEL: s_add_i32:
24 ; GFX8: ; %bb.0:
25 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
26 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
27 ; GFX8-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
28 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
29 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
30 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
31 ; GFX8-NEXT: s_add_i32 s0, s2, s3
32 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
33 ; GFX8-NEXT: flat_store_dword v[0:1], v2
34 ; GFX8-NEXT: s_endpgm
35 ;
36 ; GFX9-LABEL: s_add_i32:
37 ; GFX9: ; %bb.0:
38 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
39 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
40 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
41 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
42 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
43 ; GFX9-NEXT: s_add_i32 s0, s0, s1
44 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
45 ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
46 ; GFX9-NEXT: s_endpgm
47 ;
48 ; GFX10-LABEL: s_add_i32:
49 ; GFX10: ; %bb.0:
50 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
51 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
52 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
53 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
54 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
55 ; GFX10-NEXT: s_add_i32 s0, s0, s1
56 ; GFX10-NEXT: v_mov_b32_e32 v1, s0
57 ; GFX10-NEXT: global_store_dword v0, v1, s[4:5]
58 ; GFX10-NEXT: s_endpgm
59 ;
60 ; GFX11-LABEL: s_add_i32:
61 ; GFX11: ; %bb.0:
62 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
63 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
64 ; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
65 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
66 ; GFX11-NEXT: s_add_i32 s2, s2, s3
67 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
68 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
69 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
70 ; GFX11-NEXT: s_nop 0
71 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
72 ; GFX11-NEXT: s_endpgm
73 ;
74 ; GFX12-LABEL: s_add_i32:
75 ; GFX12: ; %bb.0:
76 ; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
77 ; GFX12-NEXT: s_wait_kmcnt 0x0
78 ; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
79 ; GFX12-NEXT: s_wait_kmcnt 0x0
80 ; GFX12-NEXT: s_add_co_i32 s2, s2, s3
81 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
82 ; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
83 ; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
84 ; GFX12-NEXT: s_nop 0
85 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
86 ; GFX12-NEXT: s_endpgm
87 %b_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1
88 %a = load i32, ptr addrspace(1) %in
89 %b = load i32, ptr addrspace(1) %b_ptr
90 %result = add i32 %a, %b
91 store i32 %result, ptr addrspace(1) %out
92 ret void
93 }
95 define amdgpu_kernel void @s_add_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
96 ; GFX6-LABEL: s_add_v2i32:
97 ; GFX6: ; %bb.0:
98 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
99 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
100 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
101 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
102 ; GFX6-NEXT: s_mov_b32 s2, -1
103 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
104 ; GFX6-NEXT: s_add_i32 s5, s5, s7
105 ; GFX6-NEXT: s_add_i32 s4, s4, s6
106 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
107 ; GFX6-NEXT: v_mov_b32_e32 v1, s5
108 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
109 ; GFX6-NEXT: s_endpgm
110 ;
111 ; GFX8-LABEL: s_add_v2i32:
112 ; GFX8: ; %bb.0:
113 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
114 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
115 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
116 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
117 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
118 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
119 ; GFX8-NEXT: s_add_i32 s0, s5, s7
120 ; GFX8-NEXT: s_add_i32 s1, s4, s6
121 ; GFX8-NEXT: v_mov_b32_e32 v2, s1
122 ; GFX8-NEXT: v_mov_b32_e32 v3, s0
123 ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
124 ; GFX8-NEXT: s_endpgm
125 ;
126 ; GFX9-LABEL: s_add_v2i32:
127 ; GFX9: ; %bb.0:
128 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
129 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
130 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
131 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
132 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
133 ; GFX9-NEXT: s_add_i32 s1, s1, s3
134 ; GFX9-NEXT: s_add_i32 s0, s0, s2
135 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
136 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
137 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
138 ; GFX9-NEXT: s_endpgm
139 ;
140 ; GFX10-LABEL: s_add_v2i32:
141 ; GFX10: ; %bb.0:
142 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
143 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
144 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
145 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
146 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
147 ; GFX10-NEXT: s_add_i32 s0, s0, s2
148 ; GFX10-NEXT: s_add_i32 s1, s1, s3
149 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
150 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
151 ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
152 ; GFX10-NEXT: s_endpgm
153 ;
154 ; GFX11-LABEL: s_add_v2i32:
155 ; GFX11: ; %bb.0:
156 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
157 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
158 ; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
159 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
160 ; GFX11-NEXT: s_add_i32 s2, s4, s6
161 ; GFX11-NEXT: s_add_i32 s3, s5, s7
162 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
163 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
164 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
165 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
166 ; GFX11-NEXT: s_nop 0
167 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
168 ; GFX11-NEXT: s_endpgm
169 ;
170 ; GFX12-LABEL: s_add_v2i32:
171 ; GFX12: ; %bb.0:
172 ; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
173 ; GFX12-NEXT: s_wait_kmcnt 0x0
174 ; GFX12-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
175 ; GFX12-NEXT: s_wait_kmcnt 0x0
176 ; GFX12-NEXT: s_add_co_i32 s2, s4, s6
177 ; GFX12-NEXT: s_add_co_i32 s3, s5, s7
178 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
179 ; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
180 ; GFX12-NEXT: v_mov_b32_e32 v0, s2
181 ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
182 ; GFX12-NEXT: s_nop 0
183 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
184 ; GFX12-NEXT: s_endpgm
185 %b_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 1
186 %a = load <2 x i32>, ptr addrspace(1) %in
187 %b = load <2 x i32>, ptr addrspace(1) %b_ptr
188 %result = add <2 x i32> %a, %b
189 store <2 x i32> %result, ptr addrspace(1) %out
190 ret void
191 }
193 define amdgpu_kernel void @s_add_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
194 ; GFX6-LABEL: s_add_v4i32:
195 ; GFX6: ; %bb.0:
196 ; GFX6-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x9
197 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
198 ; GFX6-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
199 ; GFX6-NEXT: s_mov_b32 s11, 0xf000
200 ; GFX6-NEXT: s_mov_b32 s10, -1
201 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
202 ; GFX6-NEXT: s_add_i32 s3, s3, s7
203 ; GFX6-NEXT: s_add_i32 s2, s2, s6
204 ; GFX6-NEXT: s_add_i32 s1, s1, s5
205 ; GFX6-NEXT: s_add_i32 s0, s0, s4
206 ; GFX6-NEXT: v_mov_b32_e32 v0, s0
207 ; GFX6-NEXT: v_mov_b32_e32 v1, s1
208 ; GFX6-NEXT: v_mov_b32_e32 v2, s2
209 ; GFX6-NEXT: v_mov_b32_e32 v3, s3
210 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
211 ; GFX6-NEXT: s_endpgm
212 ;
213 ; GFX8-LABEL: s_add_v4i32:
214 ; GFX8: ; %bb.0:
215 ; GFX8-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x24
216 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
217 ; GFX8-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
218 ; GFX8-NEXT: v_mov_b32_e32 v4, s8
219 ; GFX8-NEXT: v_mov_b32_e32 v5, s9
220 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
221 ; GFX8-NEXT: s_add_i32 s3, s3, s7
222 ; GFX8-NEXT: s_add_i32 s2, s2, s6
223 ; GFX8-NEXT: s_add_i32 s1, s1, s5
224 ; GFX8-NEXT: s_add_i32 s0, s0, s4
225 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
226 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
227 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
228 ; GFX8-NEXT: v_mov_b32_e32 v3, s3
229 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
230 ; GFX8-NEXT: s_endpgm
231 ;
232 ; GFX9-LABEL: s_add_v4i32:
233 ; GFX9: ; %bb.0:
234 ; GFX9-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x24
235 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
236 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
237 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
238 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
239 ; GFX9-NEXT: s_add_i32 s3, s3, s7
240 ; GFX9-NEXT: s_add_i32 s2, s2, s6
241 ; GFX9-NEXT: s_add_i32 s1, s1, s5
242 ; GFX9-NEXT: s_add_i32 s0, s0, s4
243 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
244 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
245 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
246 ; GFX9-NEXT: v_mov_b32_e32 v3, s3
247 ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
248 ; GFX9-NEXT: s_endpgm
249 ;
250 ; GFX10-LABEL: s_add_v4i32:
251 ; GFX10: ; %bb.0:
252 ; GFX10-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x24
253 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
254 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
255 ; GFX10-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
256 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
257 ; GFX10-NEXT: s_add_i32 s3, s3, s7
258 ; GFX10-NEXT: s_add_i32 s2, s2, s6
259 ; GFX10-NEXT: s_add_i32 s0, s0, s4
260 ; GFX10-NEXT: s_add_i32 s1, s1, s5
261 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
262 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
263 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
264 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
265 ; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
266 ; GFX10-NEXT: s_endpgm
267 ;
268 ; GFX11-LABEL: s_add_v4i32:
269 ; GFX11: ; %bb.0:
270 ; GFX11-NEXT: s_load_b128 s[8:11], s[2:3], 0x24
271 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
272 ; GFX11-NEXT: s_load_b256 s[0:7], s[10:11], 0x0
273 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
274 ; GFX11-NEXT: s_add_i32 s3, s3, s7
275 ; GFX11-NEXT: s_add_i32 s2, s2, s6
276 ; GFX11-NEXT: s_add_i32 s0, s0, s4
277 ; GFX11-NEXT: s_add_i32 s1, s1, s5
278 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
279 ; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
280 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
281 ; GFX11-NEXT: v_mov_b32_e32 v2, s2
282 ; GFX11-NEXT: global_store_b128 v4, v[0:3], s[8:9]
283 ; GFX11-NEXT: s_nop 0
284 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
285 ; GFX11-NEXT: s_endpgm
286 ;
287 ; GFX12-LABEL: s_add_v4i32:
288 ; GFX12: ; %bb.0:
289 ; GFX12-NEXT: s_load_b128 s[8:11], s[2:3], 0x24
290 ; GFX12-NEXT: s_wait_kmcnt 0x0
291 ; GFX12-NEXT: s_load_b256 s[0:7], s[10:11], 0x0
292 ; GFX12-NEXT: s_wait_kmcnt 0x0
293 ; GFX12-NEXT: s_add_co_i32 s3, s3, s7
294 ; GFX12-NEXT: s_add_co_i32 s2, s2, s6
295 ; GFX12-NEXT: s_add_co_i32 s0, s0, s4
296 ; GFX12-NEXT: s_add_co_i32 s1, s1, s5
297 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
298 ; GFX12-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
299 ; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
300 ; GFX12-NEXT: v_mov_b32_e32 v2, s2
301 ; GFX12-NEXT: global_store_b128 v4, v[0:3], s[8:9]
302 ; GFX12-NEXT: s_nop 0
303 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
304 ; GFX12-NEXT: s_endpgm
305 %b_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 1
306 %a = load <4 x i32>, ptr addrspace(1) %in
307 %b = load <4 x i32>, ptr addrspace(1) %b_ptr
308 %result = add <4 x i32> %a, %b
309 store <4 x i32> %result, ptr addrspace(1) %out
310 ret void
311 }
313 define amdgpu_kernel void @s_add_v8i32(ptr addrspace(1) %out, <8 x i32> %a, <8 x i32> %b) {
314 ; GFX6-LABEL: s_add_v8i32:
315 ; GFX6: ; %bb.0: ; %entry
316 ; GFX6-NEXT: s_load_dwordx16 s[4:19], s[2:3], 0x11
317 ; GFX6-NEXT: s_load_dwordx2 s[20:21], s[2:3], 0x9
318 ; GFX6-NEXT: s_mov_b32 s23, 0xf000
319 ; GFX6-NEXT: s_mov_b32 s22, -1
320 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
321 ; GFX6-NEXT: s_add_i32 s0, s7, s15
322 ; GFX6-NEXT: s_add_i32 s1, s6, s14
323 ; GFX6-NEXT: s_add_i32 s2, s5, s13
324 ; GFX6-NEXT: s_add_i32 s3, s4, s12
325 ; GFX6-NEXT: s_add_i32 s4, s11, s19
326 ; GFX6-NEXT: s_add_i32 s5, s10, s18
327 ; GFX6-NEXT: s_add_i32 s6, s9, s17
328 ; GFX6-NEXT: s_add_i32 s7, s8, s16
329 ; GFX6-NEXT: v_mov_b32_e32 v0, s7
330 ; GFX6-NEXT: v_mov_b32_e32 v1, s6
331 ; GFX6-NEXT: v_mov_b32_e32 v2, s5
332 ; GFX6-NEXT: v_mov_b32_e32 v3, s4
333 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[20:23], 0 offset:16
334 ; GFX6-NEXT: s_waitcnt expcnt(0)
335 ; GFX6-NEXT: v_mov_b32_e32 v0, s3
336 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
337 ; GFX6-NEXT: v_mov_b32_e32 v2, s1
338 ; GFX6-NEXT: v_mov_b32_e32 v3, s0
339 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[20:23], 0
340 ; GFX6-NEXT: s_endpgm
341 ;
342 ; GFX8-LABEL: s_add_v8i32:
343 ; GFX8: ; %bb.0: ; %entry
344 ; GFX8-NEXT: s_load_dwordx16 s[4:19], s[2:3], 0x44
345 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
346 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
347 ; GFX8-NEXT: s_add_i32 s7, s7, s15
348 ; GFX8-NEXT: s_add_i32 s6, s6, s14
349 ; GFX8-NEXT: s_add_i32 s5, s5, s13
350 ; GFX8-NEXT: s_add_i32 s4, s4, s12
351 ; GFX8-NEXT: s_add_i32 s2, s11, s19
352 ; GFX8-NEXT: s_add_i32 s3, s10, s18
353 ; GFX8-NEXT: s_add_i32 s9, s9, s17
354 ; GFX8-NEXT: s_add_i32 s8, s8, s16
355 ; GFX8-NEXT: v_mov_b32_e32 v3, s2
356 ; GFX8-NEXT: s_add_u32 s2, s0, 16
357 ; GFX8-NEXT: v_mov_b32_e32 v2, s3
358 ; GFX8-NEXT: s_addc_u32 s3, s1, 0
359 ; GFX8-NEXT: v_mov_b32_e32 v5, s3
360 ; GFX8-NEXT: v_mov_b32_e32 v0, s8
361 ; GFX8-NEXT: v_mov_b32_e32 v1, s9
362 ; GFX8-NEXT: v_mov_b32_e32 v4, s2
363 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
364 ; GFX8-NEXT: v_mov_b32_e32 v5, s1
365 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
366 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
367 ; GFX8-NEXT: v_mov_b32_e32 v2, s6
368 ; GFX8-NEXT: v_mov_b32_e32 v3, s7
369 ; GFX8-NEXT: v_mov_b32_e32 v4, s0
370 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
371 ; GFX8-NEXT: s_endpgm
372 ;
373 ; GFX9-LABEL: s_add_v8i32:
374 ; GFX9: ; %bb.0: ; %entry
375 ; GFX9-NEXT: s_load_dwordx16 s[4:19], s[2:3], 0x44
376 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
377 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
378 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
379 ; GFX9-NEXT: s_add_i32 s2, s7, s15
380 ; GFX9-NEXT: s_add_i32 s3, s6, s14
381 ; GFX9-NEXT: s_add_i32 s6, s11, s19
382 ; GFX9-NEXT: s_add_i32 s7, s10, s18
383 ; GFX9-NEXT: s_add_i32 s9, s9, s17
384 ; GFX9-NEXT: s_add_i32 s8, s8, s16
385 ; GFX9-NEXT: s_add_i32 s5, s5, s13
386 ; GFX9-NEXT: s_add_i32 s4, s4, s12
387 ; GFX9-NEXT: v_mov_b32_e32 v0, s8
388 ; GFX9-NEXT: v_mov_b32_e32 v1, s9
389 ; GFX9-NEXT: v_mov_b32_e32 v2, s7
390 ; GFX9-NEXT: v_mov_b32_e32 v3, s6
391 ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:16
392 ; GFX9-NEXT: s_nop 0
393 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
394 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
395 ; GFX9-NEXT: v_mov_b32_e32 v2, s3
396 ; GFX9-NEXT: v_mov_b32_e32 v3, s2
397 ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
398 ; GFX9-NEXT: s_endpgm
399 ;
400 ; GFX10-LABEL: s_add_v8i32:
401 ; GFX10: ; %bb.0: ; %entry
402 ; GFX10-NEXT: s_clause 0x1
403 ; GFX10-NEXT: s_load_dwordx16 s[4:19], s[2:3], 0x44
404 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
405 ; GFX10-NEXT: v_mov_b32_e32 v8, 0
406 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
407 ; GFX10-NEXT: s_add_i32 s2, s7, s15
408 ; GFX10-NEXT: s_add_i32 s3, s6, s14
409 ; GFX10-NEXT: s_add_i32 s6, s11, s19
410 ; GFX10-NEXT: s_add_i32 s7, s10, s18
411 ; GFX10-NEXT: s_add_i32 s8, s8, s16
412 ; GFX10-NEXT: s_add_i32 s9, s9, s17
413 ; GFX10-NEXT: s_add_i32 s5, s5, s13
414 ; GFX10-NEXT: s_add_i32 s4, s4, s12
415 ; GFX10-NEXT: v_mov_b32_e32 v0, s8
416 ; GFX10-NEXT: v_mov_b32_e32 v1, s9
417 ; GFX10-NEXT: v_mov_b32_e32 v2, s7
418 ; GFX10-NEXT: v_mov_b32_e32 v3, s6
419 ; GFX10-NEXT: v_mov_b32_e32 v4, s4
420 ; GFX10-NEXT: v_mov_b32_e32 v5, s5
421 ; GFX10-NEXT: v_mov_b32_e32 v6, s3
422 ; GFX10-NEXT: v_mov_b32_e32 v7, s2
423 ; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:16
424 ; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
425 ; GFX10-NEXT: s_endpgm
426 ;
427 ; GFX11-LABEL: s_add_v8i32:
428 ; GFX11: ; %bb.0: ; %entry
429 ; GFX11-NEXT: s_clause 0x1
430 ; GFX11-NEXT: s_load_b512 s[4:19], s[2:3], 0x44
431 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
432 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
433 ; GFX11-NEXT: s_add_i32 s2, s7, s15
434 ; GFX11-NEXT: s_add_i32 s3, s6, s14
435 ; GFX11-NEXT: s_add_i32 s6, s11, s19
436 ; GFX11-NEXT: s_add_i32 s7, s10, s18
437 ; GFX11-NEXT: s_add_i32 s8, s8, s16
438 ; GFX11-NEXT: s_add_i32 s9, s9, s17
439 ; GFX11-NEXT: s_add_i32 s5, s5, s13
440 ; GFX11-NEXT: s_add_i32 s4, s4, s12
441 ; GFX11-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s9
442 ; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s6
443 ; GFX11-NEXT: v_dual_mov_b32 v2, s7 :: v_dual_mov_b32 v5, s5
444 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s2
445 ; GFX11-NEXT: v_mov_b32_e32 v6, s3
446 ; GFX11-NEXT: s_clause 0x1
447 ; GFX11-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:16
448 ; GFX11-NEXT: global_store_b128 v8, v[4:7], s[0:1]
449 ; GFX11-NEXT: s_nop 0
450 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
451 ; GFX11-NEXT: s_endpgm
452 ;
453 ; GFX12-LABEL: s_add_v8i32:
454 ; GFX12: ; %bb.0: ; %entry
455 ; GFX12-NEXT: s_clause 0x1
456 ; GFX12-NEXT: s_load_b512 s[4:19], s[2:3], 0x44
457 ; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
458 ; GFX12-NEXT: s_wait_kmcnt 0x0
459 ; GFX12-NEXT: s_add_co_i32 s2, s7, s15
460 ; GFX12-NEXT: s_add_co_i32 s3, s6, s14
461 ; GFX12-NEXT: s_add_co_i32 s6, s11, s19
462 ; GFX12-NEXT: s_add_co_i32 s7, s10, s18
463 ; GFX12-NEXT: s_add_co_i32 s8, s8, s16
464 ; GFX12-NEXT: s_add_co_i32 s9, s9, s17
465 ; GFX12-NEXT: s_add_co_i32 s5, s5, s13
466 ; GFX12-NEXT: s_add_co_i32 s4, s4, s12
467 ; GFX12-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v1, s9
468 ; GFX12-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s6
469 ; GFX12-NEXT: v_dual_mov_b32 v2, s7 :: v_dual_mov_b32 v5, s5
470 ; GFX12-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s2
471 ; GFX12-NEXT: v_mov_b32_e32 v6, s3
472 ; GFX12-NEXT: s_clause 0x1
473 ; GFX12-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:16
474 ; GFX12-NEXT: global_store_b128 v8, v[4:7], s[0:1]
475 ; GFX12-NEXT: s_nop 0
476 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
477 ; GFX12-NEXT: s_endpgm
478 entry:
479 %0 = add <8 x i32> %a, %b
480 store <8 x i32> %0, ptr addrspace(1) %out
481 ret void
482 }
484 define amdgpu_kernel void @s_add_v16i32(ptr addrspace(1) %out, <16 x i32> %a, <16 x i32> %b) {
485 ; GFX6-LABEL: s_add_v16i32:
486 ; GFX6: ; %bb.0: ; %entry
487 ; GFX6-NEXT: s_load_dwordx16 s[4:19], s[2:3], 0x19
488 ; GFX6-NEXT: s_load_dwordx16 s[36:51], s[2:3], 0x29
489 ; GFX6-NEXT: s_load_dwordx2 s[20:21], s[2:3], 0x9
490 ; GFX6-NEXT: s_mov_b32 s23, 0xf000
491 ; GFX6-NEXT: s_mov_b32 s22, -1
492 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
493 ; GFX6-NEXT: s_add_i32 s0, s7, s39
494 ; GFX6-NEXT: s_add_i32 s1, s6, s38
495 ; GFX6-NEXT: s_add_i32 s2, s5, s37
496 ; GFX6-NEXT: s_add_i32 s3, s4, s36
497 ; GFX6-NEXT: s_add_i32 s4, s11, s43
498 ; GFX6-NEXT: s_add_i32 s5, s10, s42
499 ; GFX6-NEXT: s_add_i32 s6, s9, s41
500 ; GFX6-NEXT: s_add_i32 s7, s8, s40
501 ; GFX6-NEXT: s_add_i32 s8, s15, s47
502 ; GFX6-NEXT: s_add_i32 s9, s14, s46
503 ; GFX6-NEXT: s_add_i32 s10, s13, s45
504 ; GFX6-NEXT: s_add_i32 s11, s12, s44
505 ; GFX6-NEXT: s_add_i32 s12, s19, s51
506 ; GFX6-NEXT: s_add_i32 s13, s18, s50
507 ; GFX6-NEXT: s_add_i32 s14, s17, s49
508 ; GFX6-NEXT: s_add_i32 s15, s16, s48
509 ; GFX6-NEXT: v_mov_b32_e32 v0, s15
510 ; GFX6-NEXT: v_mov_b32_e32 v1, s14
511 ; GFX6-NEXT: v_mov_b32_e32 v2, s13
512 ; GFX6-NEXT: v_mov_b32_e32 v3, s12
513 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[20:23], 0 offset:48
514 ; GFX6-NEXT: s_waitcnt expcnt(0)
515 ; GFX6-NEXT: v_mov_b32_e32 v0, s11
516 ; GFX6-NEXT: v_mov_b32_e32 v1, s10
517 ; GFX6-NEXT: v_mov_b32_e32 v2, s9
518 ; GFX6-NEXT: v_mov_b32_e32 v3, s8
519 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[20:23], 0 offset:32
520 ; GFX6-NEXT: s_waitcnt expcnt(0)
521 ; GFX6-NEXT: v_mov_b32_e32 v0, s7
522 ; GFX6-NEXT: v_mov_b32_e32 v1, s6
523 ; GFX6-NEXT: v_mov_b32_e32 v2, s5
524 ; GFX6-NEXT: v_mov_b32_e32 v3, s4
525 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[20:23], 0 offset:16
526 ; GFX6-NEXT: s_waitcnt expcnt(0)
527 ; GFX6-NEXT: v_mov_b32_e32 v0, s3
528 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
529 ; GFX6-NEXT: v_mov_b32_e32 v2, s1
530 ; GFX6-NEXT: v_mov_b32_e32 v3, s0
531 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[20:23], 0
532 ; GFX6-NEXT: s_endpgm
533 ;
534 ; GFX8-LABEL: s_add_v16i32:
535 ; GFX8: ; %bb.0: ; %entry
536 ; GFX8-NEXT: s_load_dwordx16 s[4:19], s[2:3], 0x64
537 ; GFX8-NEXT: s_load_dwordx16 s[36:51], s[2:3], 0xa4
538 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
539 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
540 ; GFX8-NEXT: s_add_i32 s7, s7, s39
541 ; GFX8-NEXT: s_add_i32 s6, s6, s38
542 ; GFX8-NEXT: s_add_i32 s5, s5, s37
543 ; GFX8-NEXT: s_add_i32 s4, s4, s36
544 ; GFX8-NEXT: s_add_i32 s11, s11, s43
545 ; GFX8-NEXT: s_add_i32 s10, s10, s42
546 ; GFX8-NEXT: s_add_i32 s9, s9, s41
547 ; GFX8-NEXT: s_add_i32 s8, s8, s40
548 ; GFX8-NEXT: s_add_i32 s15, s15, s47
549 ; GFX8-NEXT: s_add_i32 s14, s14, s46
550 ; GFX8-NEXT: s_add_i32 s13, s13, s45
551 ; GFX8-NEXT: s_add_i32 s12, s12, s44
552 ; GFX8-NEXT: s_add_i32 s2, s19, s51
553 ; GFX8-NEXT: s_add_i32 s3, s18, s50
554 ; GFX8-NEXT: s_add_i32 s17, s17, s49
555 ; GFX8-NEXT: s_add_i32 s16, s16, s48
556 ; GFX8-NEXT: v_mov_b32_e32 v3, s2
557 ; GFX8-NEXT: s_add_u32 s2, s0, 48
558 ; GFX8-NEXT: v_mov_b32_e32 v2, s3
559 ; GFX8-NEXT: s_addc_u32 s3, s1, 0
560 ; GFX8-NEXT: v_mov_b32_e32 v5, s3
561 ; GFX8-NEXT: v_mov_b32_e32 v4, s2
562 ; GFX8-NEXT: s_add_u32 s2, s0, 32
563 ; GFX8-NEXT: v_mov_b32_e32 v0, s16
564 ; GFX8-NEXT: v_mov_b32_e32 v1, s17
565 ; GFX8-NEXT: s_addc_u32 s3, s1, 0
566 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
567 ; GFX8-NEXT: v_mov_b32_e32 v5, s3
568 ; GFX8-NEXT: v_mov_b32_e32 v4, s2
569 ; GFX8-NEXT: s_add_u32 s2, s0, 16
570 ; GFX8-NEXT: v_mov_b32_e32 v0, s12
571 ; GFX8-NEXT: v_mov_b32_e32 v1, s13
572 ; GFX8-NEXT: v_mov_b32_e32 v2, s14
573 ; GFX8-NEXT: v_mov_b32_e32 v3, s15
574 ; GFX8-NEXT: s_addc_u32 s3, s1, 0
575 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
576 ; GFX8-NEXT: v_mov_b32_e32 v5, s3
577 ; GFX8-NEXT: v_mov_b32_e32 v0, s8
578 ; GFX8-NEXT: v_mov_b32_e32 v1, s9
579 ; GFX8-NEXT: v_mov_b32_e32 v2, s10
580 ; GFX8-NEXT: v_mov_b32_e32 v3, s11
581 ; GFX8-NEXT: v_mov_b32_e32 v4, s2
582 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
583 ; GFX8-NEXT: v_mov_b32_e32 v5, s1
584 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
585 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
586 ; GFX8-NEXT: v_mov_b32_e32 v2, s6
587 ; GFX8-NEXT: v_mov_b32_e32 v3, s7
588 ; GFX8-NEXT: v_mov_b32_e32 v4, s0
589 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
590 ; GFX8-NEXT: s_endpgm
591 ;
592 ; GFX9-LABEL: s_add_v16i32:
593 ; GFX9: ; %bb.0: ; %entry
594 ; GFX9-NEXT: s_load_dwordx16 s[4:19], s[2:3], 0x64
595 ; GFX9-NEXT: s_load_dwordx16 s[36:51], s[2:3], 0xa4
596 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
597 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
598 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
599 ; GFX9-NEXT: s_add_i32 s2, s7, s39
600 ; GFX9-NEXT: s_add_i32 s3, s6, s38
601 ; GFX9-NEXT: s_add_i32 s6, s11, s43
602 ; GFX9-NEXT: s_add_i32 s7, s10, s42
603 ; GFX9-NEXT: s_add_i32 s10, s15, s47
604 ; GFX9-NEXT: s_add_i32 s11, s14, s46
605 ; GFX9-NEXT: s_add_i32 s14, s19, s51
606 ; GFX9-NEXT: s_add_i32 s15, s18, s50
607 ; GFX9-NEXT: s_add_i32 s17, s17, s49
608 ; GFX9-NEXT: s_add_i32 s16, s16, s48
609 ; GFX9-NEXT: s_add_i32 s13, s13, s45
610 ; GFX9-NEXT: s_add_i32 s12, s12, s44
611 ; GFX9-NEXT: v_mov_b32_e32 v0, s16
612 ; GFX9-NEXT: v_mov_b32_e32 v1, s17
613 ; GFX9-NEXT: v_mov_b32_e32 v2, s15
614 ; GFX9-NEXT: v_mov_b32_e32 v3, s14
615 ; GFX9-NEXT: s_add_i32 s9, s9, s41
616 ; GFX9-NEXT: s_add_i32 s8, s8, s40
617 ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:48
618 ; GFX9-NEXT: s_add_i32 s5, s5, s37
619 ; GFX9-NEXT: v_mov_b32_e32 v0, s12
620 ; GFX9-NEXT: v_mov_b32_e32 v1, s13
621 ; GFX9-NEXT: v_mov_b32_e32 v2, s11
622 ; GFX9-NEXT: v_mov_b32_e32 v3, s10
623 ; GFX9-NEXT: s_add_i32 s4, s4, s36
624 ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:32
625 ; GFX9-NEXT: s_nop 0
626 ; GFX9-NEXT: v_mov_b32_e32 v0, s8
627 ; GFX9-NEXT: v_mov_b32_e32 v1, s9
628 ; GFX9-NEXT: v_mov_b32_e32 v2, s7
629 ; GFX9-NEXT: v_mov_b32_e32 v3, s6
630 ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:16
631 ; GFX9-NEXT: s_nop 0
632 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
633 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
634 ; GFX9-NEXT: v_mov_b32_e32 v2, s3
635 ; GFX9-NEXT: v_mov_b32_e32 v3, s2
636 ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
637 ; GFX9-NEXT: s_endpgm
638 ;
639 ; GFX10-LABEL: s_add_v16i32:
640 ; GFX10: ; %bb.0: ; %entry
641 ; GFX10-NEXT: s_clause 0x2
642 ; GFX10-NEXT: s_load_dwordx16 s[4:19], s[2:3], 0x64
643 ; GFX10-NEXT: s_load_dwordx16 s[36:51], s[2:3], 0xa4
644 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
645 ; GFX10-NEXT: v_mov_b32_e32 v16, 0
646 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
647 ; GFX10-NEXT: s_add_i32 s2, s7, s39
648 ; GFX10-NEXT: s_add_i32 s3, s6, s38
649 ; GFX10-NEXT: s_add_i32 s6, s11, s43
650 ; GFX10-NEXT: s_add_i32 s7, s10, s42
651 ; GFX10-NEXT: s_add_i32 s10, s15, s47
652 ; GFX10-NEXT: s_add_i32 s11, s14, s46
653 ; GFX10-NEXT: s_add_i32 s14, s19, s51
654 ; GFX10-NEXT: s_add_i32 s15, s18, s50
655 ; GFX10-NEXT: s_add_i32 s16, s16, s48
656 ; GFX10-NEXT: s_add_i32 s17, s17, s49
657 ; GFX10-NEXT: s_add_i32 s13, s13, s45
658 ; GFX10-NEXT: s_add_i32 s12, s12, s44
659 ; GFX10-NEXT: s_add_i32 s9, s9, s41
660 ; GFX10-NEXT: s_add_i32 s8, s8, s40
661 ; GFX10-NEXT: v_mov_b32_e32 v0, s16
662 ; GFX10-NEXT: v_mov_b32_e32 v1, s17
663 ; GFX10-NEXT: v_mov_b32_e32 v2, s15
664 ; GFX10-NEXT: v_mov_b32_e32 v3, s14
665 ; GFX10-NEXT: s_add_i32 s5, s5, s37
666 ; GFX10-NEXT: s_add_i32 s4, s4, s36
667 ; GFX10-NEXT: v_mov_b32_e32 v4, s12
668 ; GFX10-NEXT: v_mov_b32_e32 v5, s13
669 ; GFX10-NEXT: v_mov_b32_e32 v6, s11
670 ; GFX10-NEXT: v_mov_b32_e32 v7, s10
671 ; GFX10-NEXT: v_mov_b32_e32 v8, s8
672 ; GFX10-NEXT: v_mov_b32_e32 v9, s9
673 ; GFX10-NEXT: v_mov_b32_e32 v10, s7
674 ; GFX10-NEXT: v_mov_b32_e32 v11, s6
675 ; GFX10-NEXT: v_mov_b32_e32 v12, s4
676 ; GFX10-NEXT: v_mov_b32_e32 v13, s5
677 ; GFX10-NEXT: v_mov_b32_e32 v14, s3
678 ; GFX10-NEXT: v_mov_b32_e32 v15, s2
679 ; GFX10-NEXT: global_store_dwordx4 v16, v[0:3], s[0:1] offset:48
680 ; GFX10-NEXT: global_store_dwordx4 v16, v[4:7], s[0:1] offset:32
681 ; GFX10-NEXT: global_store_dwordx4 v16, v[8:11], s[0:1] offset:16
682 ; GFX10-NEXT: global_store_dwordx4 v16, v[12:15], s[0:1]
683 ; GFX10-NEXT: s_endpgm
684 ;
685 ; GFX11-LABEL: s_add_v16i32:
686 ; GFX11: ; %bb.0: ; %entry
687 ; GFX11-NEXT: s_clause 0x2
688 ; GFX11-NEXT: s_load_b512 s[4:19], s[2:3], 0x64
689 ; GFX11-NEXT: s_load_b512 s[36:51], s[2:3], 0xa4
690 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
691 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
692 ; GFX11-NEXT: s_add_i32 s2, s7, s39
693 ; GFX11-NEXT: s_add_i32 s3, s6, s38
694 ; GFX11-NEXT: s_add_i32 s6, s11, s43
695 ; GFX11-NEXT: s_add_i32 s7, s10, s42
696 ; GFX11-NEXT: s_add_i32 s10, s15, s47
697 ; GFX11-NEXT: s_add_i32 s11, s14, s46
698 ; GFX11-NEXT: s_add_i32 s14, s19, s51
699 ; GFX11-NEXT: s_add_i32 s15, s18, s50
700 ; GFX11-NEXT: s_add_i32 s16, s16, s48
701 ; GFX11-NEXT: s_add_i32 s17, s17, s49
702 ; GFX11-NEXT: s_add_i32 s13, s13, s45
703 ; GFX11-NEXT: s_add_i32 s12, s12, s44
704 ; GFX11-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s17
705 ; GFX11-NEXT: s_add_i32 s9, s9, s41
706 ; GFX11-NEXT: s_add_i32 s8, s8, s40
707 ; GFX11-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v3, s14
708 ; GFX11-NEXT: v_dual_mov_b32 v2, s15 :: v_dual_mov_b32 v5, s13
709 ; GFX11-NEXT: s_add_i32 s5, s5, s37
710 ; GFX11-NEXT: s_add_i32 s4, s4, s36
711 ; GFX11-NEXT: v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v7, s10
712 ; GFX11-NEXT: v_dual_mov_b32 v6, s11 :: v_dual_mov_b32 v9, s9
713 ; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v11, s6
714 ; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v13, s5
715 ; GFX11-NEXT: v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v15, s2
716 ; GFX11-NEXT: v_mov_b32_e32 v14, s3
717 ; GFX11-NEXT: s_clause 0x3
718 ; GFX11-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
719 ; GFX11-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
720 ; GFX11-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
721 ; GFX11-NEXT: global_store_b128 v16, v[12:15], s[0:1]
722 ; GFX11-NEXT: s_nop 0
723 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
724 ; GFX11-NEXT: s_endpgm
725 ;
726 ; GFX12-LABEL: s_add_v16i32:
727 ; GFX12: ; %bb.0: ; %entry
728 ; GFX12-NEXT: s_clause 0x2
729 ; GFX12-NEXT: s_load_b512 s[4:19], s[2:3], 0x64
730 ; GFX12-NEXT: s_load_b512 s[36:51], s[2:3], 0xa4
731 ; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
732 ; GFX12-NEXT: s_wait_kmcnt 0x0
733 ; GFX12-NEXT: s_add_co_i32 s2, s7, s39
734 ; GFX12-NEXT: s_add_co_i32 s3, s6, s38
735 ; GFX12-NEXT: s_add_co_i32 s6, s11, s43
736 ; GFX12-NEXT: s_add_co_i32 s7, s10, s42
737 ; GFX12-NEXT: s_add_co_i32 s10, s15, s47
738 ; GFX12-NEXT: s_add_co_i32 s11, s14, s46
739 ; GFX12-NEXT: s_add_co_i32 s14, s19, s51
740 ; GFX12-NEXT: s_add_co_i32 s15, s18, s50
741 ; GFX12-NEXT: s_add_co_i32 s16, s16, s48
742 ; GFX12-NEXT: s_add_co_i32 s17, s17, s49
743 ; GFX12-NEXT: s_add_co_i32 s13, s13, s45
744 ; GFX12-NEXT: s_add_co_i32 s12, s12, s44
745 ; GFX12-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s17
746 ; GFX12-NEXT: s_add_co_i32 s9, s9, s41
747 ; GFX12-NEXT: s_add_co_i32 s8, s8, s40
748 ; GFX12-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v3, s14
749 ; GFX12-NEXT: v_dual_mov_b32 v2, s15 :: v_dual_mov_b32 v5, s13
750 ; GFX12-NEXT: s_add_co_i32 s5, s5, s37
751 ; GFX12-NEXT: s_add_co_i32 s4, s4, s36
752 ; GFX12-NEXT: v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v7, s10
753 ; GFX12-NEXT: v_dual_mov_b32 v6, s11 :: v_dual_mov_b32 v9, s9
754 ; GFX12-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v11, s6
755 ; GFX12-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v13, s5
756 ; GFX12-NEXT: v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v15, s2
757 ; GFX12-NEXT: v_mov_b32_e32 v14, s3
758 ; GFX12-NEXT: s_clause 0x3
759 ; GFX12-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
760 ; GFX12-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
761 ; GFX12-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
762 ; GFX12-NEXT: global_store_b128 v16, v[12:15], s[0:1]
763 ; GFX12-NEXT: s_nop 0
764 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
765 ; GFX12-NEXT: s_endpgm
766 entry:
767 %0 = add <16 x i32> %a, %b
768 store <16 x i32> %0, ptr addrspace(1) %out
769 ret void
770 }
772 define amdgpu_kernel void @v_add_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
773 ; GFX6-LABEL: v_add_i32:
774 ; GFX6: ; %bb.0:
775 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
776 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
777 ; GFX6-NEXT: s_mov_b32 s10, 0
778 ; GFX6-NEXT: s_mov_b32 s11, s7
779 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
780 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
781 ; GFX6-NEXT: s_mov_b64 s[8:9], s[2:3]
782 ; GFX6-NEXT: v_mov_b32_e32 v1, 0
783 ; GFX6-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
784 ; GFX6-NEXT: s_waitcnt vmcnt(0)
785 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 offset:4 glc
786 ; GFX6-NEXT: s_waitcnt vmcnt(0)
787 ; GFX6-NEXT: s_mov_b32 s6, -1
788 ; GFX6-NEXT: s_mov_b32 s4, s0
789 ; GFX6-NEXT: s_mov_b32 s5, s1
790 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
791 ; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
792 ; GFX6-NEXT: s_endpgm
793 ;
794 ; GFX8-LABEL: v_add_i32:
795 ; GFX8: ; %bb.0:
796 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
797 ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
798 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
799 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
800 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v0
801 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
802 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
803 ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
804 ; GFX8-NEXT: flat_load_dword v4, v[0:1] glc
805 ; GFX8-NEXT: s_waitcnt vmcnt(0)
806 ; GFX8-NEXT: flat_load_dword v2, v[2:3] glc
807 ; GFX8-NEXT: s_waitcnt vmcnt(0)
808 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
809 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
810 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v4, v2
811 ; GFX8-NEXT: flat_store_dword v[0:1], v2
812 ; GFX8-NEXT: s_endpgm
813 ;
814 ; GFX9-LABEL: v_add_i32:
815 ; GFX9: ; %bb.0:
816 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
817 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
818 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
819 ; GFX9-NEXT: global_load_dword v1, v0, s[6:7] glc
820 ; GFX9-NEXT: s_waitcnt vmcnt(0)
821 ; GFX9-NEXT: global_load_dword v2, v0, s[6:7] offset:4 glc
822 ; GFX9-NEXT: s_waitcnt vmcnt(0)
823 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
824 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
825 ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
826 ; GFX9-NEXT: s_endpgm
827 ;
828 ; GFX10-LABEL: v_add_i32:
829 ; GFX10: ; %bb.0:
830 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
831 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
832 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
833 ; GFX10-NEXT: global_load_dword v1, v0, s[6:7] glc dlc
834 ; GFX10-NEXT: s_waitcnt vmcnt(0)
835 ; GFX10-NEXT: global_load_dword v2, v0, s[6:7] offset:4 glc dlc
836 ; GFX10-NEXT: s_waitcnt vmcnt(0)
837 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
838 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
839 ; GFX10-NEXT: global_store_dword v0, v1, s[4:5]
840 ; GFX10-NEXT: s_endpgm
841 ;
842 ; GFX11-LABEL: v_add_i32:
843 ; GFX11: ; %bb.0:
844 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
845 ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
846 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
847 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
848 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
849 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
850 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc
851 ; GFX11-NEXT: s_waitcnt vmcnt(0)
852 ; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:4 glc dlc
853 ; GFX11-NEXT: s_waitcnt vmcnt(0)
854 ; GFX11-NEXT: v_add_nc_u32_e32 v0, v1, v0
855 ; GFX11-NEXT: global_store_b32 v2, v0, s[0:1]
856 ; GFX11-NEXT: s_nop 0
857 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
858 ; GFX11-NEXT: s_endpgm
859 ;
860 ; GFX12-LABEL: v_add_i32:
861 ; GFX12: ; %bb.0:
862 ; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
863 ; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
864 ; GFX12-NEXT: v_mov_b32_e32 v2, 0
865 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
866 ; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
867 ; GFX12-NEXT: s_wait_kmcnt 0x0
868 ; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
869 ; GFX12-NEXT: s_wait_loadcnt 0x0
870 ; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:4 scope:SCOPE_SYS
871 ; GFX12-NEXT: s_wait_loadcnt 0x0
872 ; GFX12-NEXT: v_add_nc_u32_e32 v0, v1, v0
873 ; GFX12-NEXT: global_store_b32 v2, v0, s[0:1]
874 ; GFX12-NEXT: s_nop 0
875 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
876 ; GFX12-NEXT: s_endpgm
877 %tid = call i32 @llvm.amdgcn.workitem.id.x()
878 %gep = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid
879 %b_ptr = getelementptr i32, ptr addrspace(1) %gep, i32 1
880 %a = load volatile i32, ptr addrspace(1) %gep
881 %b = load volatile i32, ptr addrspace(1) %b_ptr
882 %result = add i32 %a, %b
883 store i32 %result, ptr addrspace(1) %out
884 ret void
885 }
887 define amdgpu_kernel void @v_add_imm_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
888 ; GFX6-LABEL: v_add_imm_i32:
889 ; GFX6: ; %bb.0:
890 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
891 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
892 ; GFX6-NEXT: s_mov_b32 s10, 0
893 ; GFX6-NEXT: s_mov_b32 s11, s7
894 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
895 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
896 ; GFX6-NEXT: s_mov_b64 s[8:9], s[2:3]
897 ; GFX6-NEXT: v_mov_b32_e32 v1, 0
898 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 glc
899 ; GFX6-NEXT: s_waitcnt vmcnt(0)
900 ; GFX6-NEXT: s_mov_b32 s6, -1
901 ; GFX6-NEXT: s_mov_b32 s4, s0
902 ; GFX6-NEXT: s_mov_b32 s5, s1
903 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0x7b, v0
904 ; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
905 ; GFX6-NEXT: s_endpgm
906 ;
907 ; GFX8-LABEL: v_add_imm_i32:
908 ; GFX8: ; %bb.0:
909 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
910 ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
911 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
912 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
913 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v0
914 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
915 ; GFX8-NEXT: flat_load_dword v2, v[0:1] glc
916 ; GFX8-NEXT: s_waitcnt vmcnt(0)
917 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
918 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
919 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0x7b, v2
920 ; GFX8-NEXT: flat_store_dword v[0:1], v2
921 ; GFX8-NEXT: s_endpgm
922 ;
923 ; GFX9-LABEL: v_add_imm_i32:
924 ; GFX9: ; %bb.0:
925 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
926 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
927 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
928 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
929 ; GFX9-NEXT: global_load_dword v0, v0, s[6:7] glc
930 ; GFX9-NEXT: s_waitcnt vmcnt(0)
931 ; GFX9-NEXT: v_add_u32_e32 v0, 0x7b, v0
932 ; GFX9-NEXT: global_store_dword v1, v0, s[4:5]
933 ; GFX9-NEXT: s_endpgm
934 ;
935 ; GFX10-LABEL: v_add_imm_i32:
936 ; GFX10: ; %bb.0:
937 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
938 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
939 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
940 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
941 ; GFX10-NEXT: global_load_dword v0, v0, s[6:7] glc dlc
942 ; GFX10-NEXT: s_waitcnt vmcnt(0)
943 ; GFX10-NEXT: v_add_nc_u32_e32 v0, 0x7b, v0
944 ; GFX10-NEXT: global_store_dword v1, v0, s[4:5]
945 ; GFX10-NEXT: s_endpgm
946 ;
947 ; GFX11-LABEL: v_add_imm_i32:
948 ; GFX11: ; %bb.0:
949 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
950 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
951 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
952 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
953 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
954 ; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] glc dlc
955 ; GFX11-NEXT: s_waitcnt vmcnt(0)
956 ; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x7b, v0
957 ; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
958 ; GFX11-NEXT: s_nop 0
959 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
960 ; GFX11-NEXT: s_endpgm
961 ;
962 ; GFX12-LABEL: v_add_imm_i32:
963 ; GFX12: ; %bb.0:
964 ; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
965 ; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
966 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
967 ; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
968 ; GFX12-NEXT: s_wait_kmcnt 0x0
969 ; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] scope:SCOPE_SYS
970 ; GFX12-NEXT: s_wait_loadcnt 0x0
971 ; GFX12-NEXT: v_add_nc_u32_e32 v0, 0x7b, v0
972 ; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
973 ; GFX12-NEXT: s_nop 0
974 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
975 ; GFX12-NEXT: s_endpgm
976 %tid = call i32 @llvm.amdgcn.workitem.id.x()
977 %gep = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid
978 %b_ptr = getelementptr i32, ptr addrspace(1) %gep, i32 1
979 %a = load volatile i32, ptr addrspace(1) %gep
980 %result = add i32 %a, 123
981 store i32 %result, ptr addrspace(1) %out
982 ret void
983 }
985 define amdgpu_kernel void @add64(ptr addrspace(1) %out, i64 %a, i64 %b) {
986 ; GFX6-LABEL: add64:
987 ; GFX6: ; %bb.0: ; %entry
988 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x9
989 ; GFX6-NEXT: s_load_dwordx2 s[8:9], s[2:3], 0xd
990 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
991 ; GFX6-NEXT: s_mov_b32 s2, -1
992 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
993 ; GFX6-NEXT: s_mov_b32 s0, s4
994 ; GFX6-NEXT: s_add_u32 s4, s6, s8
995 ; GFX6-NEXT: s_mov_b32 s1, s5
996 ; GFX6-NEXT: s_addc_u32 s5, s7, s9
997 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
998 ; GFX6-NEXT: v_mov_b32_e32 v1, s5
999 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1000 ; GFX6-NEXT: s_endpgm
1001 ;
1002 ; GFX8-LABEL: add64:
1003 ; GFX8: ; %bb.0: ; %entry
1004 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
1005 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x34
1006 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
1007 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
1008 ; GFX8-NEXT: s_add_u32 s0, s6, s0
1009 ; GFX8-NEXT: s_addc_u32 s1, s7, s1
1010 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
1011 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
1012 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
1013 ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
1014 ; GFX8-NEXT: s_endpgm
1015 ;
1016 ; GFX9-LABEL: add64:
1017 ; GFX9: ; %bb.0: ; %entry
1018 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
1019 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x34
1020 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
1021 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1022 ; GFX9-NEXT: s_add_u32 s0, s6, s0
1023 ; GFX9-NEXT: s_addc_u32 s1, s7, s1
1024 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
1025 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
1026 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
1027 ; GFX9-NEXT: s_endpgm
1028 ;
1029 ; GFX10-LABEL: add64:
1030 ; GFX10: ; %bb.0: ; %entry
1031 ; GFX10-NEXT: s_clause 0x1
1032 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
1033 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x34
1034 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
1035 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
1036 ; GFX10-NEXT: s_add_u32 s0, s6, s0
1037 ; GFX10-NEXT: s_addc_u32 s1, s7, s1
1038 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
1039 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
1040 ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
1041 ; GFX10-NEXT: s_endpgm
1042 ;
1043 ; GFX11-LABEL: add64:
1044 ; GFX11: ; %bb.0: ; %entry
1045 ; GFX11-NEXT: s_clause 0x1
1046 ; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x24
1047 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x34
1048 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1049 ; GFX11-NEXT: s_add_u32 s0, s6, s0
1050 ; GFX11-NEXT: s_addc_u32 s1, s7, s1
1051 ; GFX11-NEXT: v_mov_b32_e32 v0, s0
1052 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
1053 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]
1054 ; GFX11-NEXT: s_nop 0
1055 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1056 ; GFX11-NEXT: s_endpgm
1057 ;
1058 ; GFX12-LABEL: add64:
1059 ; GFX12: ; %bb.0: ; %entry
1060 ; GFX12-NEXT: s_clause 0x1
1061 ; GFX12-NEXT: s_load_b128 s[4:7], s[2:3], 0x24
1062 ; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x34
1063 ; GFX12-NEXT: s_wait_kmcnt 0x0
1064 ; GFX12-NEXT: s_add_nc_u64 s[0:1], s[6:7], s[0:1]
1065 ; GFX12-NEXT: v_mov_b32_e32 v2, 0
1066 ; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
1067 ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[4:5]
1068 ; GFX12-NEXT: s_nop 0
1069 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1070 ; GFX12-NEXT: s_endpgm
1071 entry:
1072 %add = add i64 %a, %b
1073 store i64 %add, ptr addrspace(1) %out
1074 ret void
1075 }
1077 ; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
1078 ; use VCC. The test is designed so that %a will be stored in an SGPR and
1079 ; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
1080 ; to a VGPR before doing the add.
1081 define amdgpu_kernel void @add64_sgpr_vgpr(ptr addrspace(1) %out, i64 %a, ptr addrspace(1) %in) {
1082 ; GFX6-LABEL: add64_sgpr_vgpr:
1083 ; GFX6: ; %bb.0: ; %entry
1084 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0xd
1085 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
1086 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
1087 ; GFX6-NEXT: s_mov_b32 s6, -1
1088 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
1089 ; GFX6-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
1090 ; GFX6-NEXT: s_mov_b32 s4, s0
1091 ; GFX6-NEXT: s_mov_b32 s5, s1
1092 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
1093 ; GFX6-NEXT: s_add_u32 s0, s2, s8
1094 ; GFX6-NEXT: s_addc_u32 s1, s3, s9
1095 ; GFX6-NEXT: v_mov_b32_e32 v0, s0
1096 ; GFX6-NEXT: v_mov_b32_e32 v1, s1
1097 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1098 ; GFX6-NEXT: s_endpgm
1099 ;
1100 ; GFX8-LABEL: add64_sgpr_vgpr:
1101 ; GFX8: ; %bb.0: ; %entry
1102 ; GFX8-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x34
1103 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
1104 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
1105 ; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
1106 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
1107 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
1108 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
1109 ; GFX8-NEXT: s_add_u32 s0, s2, s4
1110 ; GFX8-NEXT: s_addc_u32 s1, s3, s5
1111 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
1112 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
1113 ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
1114 ; GFX8-NEXT: s_endpgm
1115 ;
1116 ; GFX9-LABEL: add64_sgpr_vgpr:
1117 ; GFX9: ; %bb.0: ; %entry
1118 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x34
1119 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
1120 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
1121 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1122 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
1123 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1124 ; GFX9-NEXT: s_add_u32 s0, s6, s0
1125 ; GFX9-NEXT: s_addc_u32 s1, s7, s1
1126 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
1127 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
1128 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
1129 ; GFX9-NEXT: s_endpgm
1130 ;
1131 ; GFX10-LABEL: add64_sgpr_vgpr:
1132 ; GFX10: ; %bb.0: ; %entry
1133 ; GFX10-NEXT: s_clause 0x1
1134 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x34
1135 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
1136 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
1137 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
1138 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
1139 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
1140 ; GFX10-NEXT: s_add_u32 s0, s6, s0
1141 ; GFX10-NEXT: s_addc_u32 s1, s7, s1
1142 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
1143 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
1144 ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
1145 ; GFX10-NEXT: s_endpgm
1146 ;
1147 ; GFX11-LABEL: add64_sgpr_vgpr:
1148 ; GFX11: ; %bb.0: ; %entry
1149 ; GFX11-NEXT: s_clause 0x1
1150 ; GFX11-NEXT: s_load_b64 s[4:5], s[2:3], 0x34
1151 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
1152 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1153 ; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x0
1154 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1155 ; GFX11-NEXT: s_add_u32 s2, s2, s4
1156 ; GFX11-NEXT: s_addc_u32 s3, s3, s5
1157 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1158 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
1159 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1160 ; GFX11-NEXT: s_nop 0
1161 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1162 ; GFX11-NEXT: s_endpgm
1163 ;
1164 ; GFX12-LABEL: add64_sgpr_vgpr:
1165 ; GFX12: ; %bb.0: ; %entry
1166 ; GFX12-NEXT: s_clause 0x1
1167 ; GFX12-NEXT: s_load_b64 s[4:5], s[2:3], 0x34
1168 ; GFX12-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
1169 ; GFX12-NEXT: s_wait_kmcnt 0x0
1170 ; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x0
1171 ; GFX12-NEXT: s_wait_kmcnt 0x0
1172 ; GFX12-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[4:5]
1173 ; GFX12-NEXT: v_mov_b32_e32 v2, 0
1174 ; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
1175 ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1176 ; GFX12-NEXT: s_nop 0
1177 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1178 ; GFX12-NEXT: s_endpgm
1179 entry:
1180 %0 = load i64, ptr addrspace(1) %in
1181 %1 = add i64 %a, %0
1182 store i64 %1, ptr addrspace(1) %out
1183 ret void
1184 }
1186 ; Test i64 add inside a branch.
1187 define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %a, i64 %b, i64 %c) {
1188 ; GFX6-LABEL: add64_in_branch:
1189 ; GFX6: ; %bb.0: ; %entry
1190 ; GFX6-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x9
1191 ; GFX6-NEXT: s_mov_b64 s[8:9], 0
1192 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
1193 ; GFX6-NEXT: v_cmp_ne_u64_e64 s[10:11], s[4:5], 0
1194 ; GFX6-NEXT: s_and_b64 vcc, exec, s[10:11]
1195 ; GFX6-NEXT: s_cbranch_vccz .LBB9_4
1196 ; GFX6-NEXT: ; %bb.1: ; %else
1197 ; GFX6-NEXT: s_add_u32 s4, s4, s6
1198 ; GFX6-NEXT: s_addc_u32 s5, s5, s7
1199 ; GFX6-NEXT: s_andn2_b64 vcc, exec, s[8:9]
1200 ; GFX6-NEXT: s_cbranch_vccnz .LBB9_3
1201 ; GFX6-NEXT: .LBB9_2: ; %if
1202 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
1203 ; GFX6-NEXT: .LBB9_3: ; %endif
1204 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
1205 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
1206 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
1207 ; GFX6-NEXT: s_mov_b32 s2, -1
1208 ; GFX6-NEXT: v_mov_b32_e32 v1, s5
1209 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1210 ; GFX6-NEXT: s_endpgm
1211 ; GFX6-NEXT: .LBB9_4:
1212 ; GFX6-NEXT: ; implicit-def: $sgpr4_sgpr5
1213 ; GFX6-NEXT: s_branch .LBB9_2
1214 ;
1215 ; GFX8-LABEL: add64_in_branch:
1216 ; GFX8: ; %bb.0: ; %entry
1217 ; GFX8-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x24
1218 ; GFX8-NEXT: s_mov_b64 s[8:9], 0
1219 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
1220 ; GFX8-NEXT: s_cmp_lg_u64 s[4:5], 0
1221 ; GFX8-NEXT: s_cbranch_scc0 .LBB9_4
1222 ; GFX8-NEXT: ; %bb.1: ; %else
1223 ; GFX8-NEXT: s_add_u32 s4, s4, s6
1224 ; GFX8-NEXT: s_addc_u32 s5, s5, s7
1225 ; GFX8-NEXT: s_andn2_b64 vcc, exec, s[8:9]
1226 ; GFX8-NEXT: s_cbranch_vccnz .LBB9_3
1227 ; GFX8-NEXT: .LBB9_2: ; %if
1228 ; GFX8-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
1229 ; GFX8-NEXT: .LBB9_3: ; %endif
1230 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
1231 ; GFX8-NEXT: v_mov_b32_e32 v2, s4
1232 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
1233 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
1234 ; GFX8-NEXT: v_mov_b32_e32 v3, s5
1235 ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
1236 ; GFX8-NEXT: s_endpgm
1237 ; GFX8-NEXT: .LBB9_4:
1238 ; GFX8-NEXT: ; implicit-def: $sgpr4_sgpr5
1239 ; GFX8-NEXT: s_branch .LBB9_2
1240 ;
1241 ; GFX9-LABEL: add64_in_branch:
1242 ; GFX9: ; %bb.0: ; %entry
1243 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x24
1244 ; GFX9-NEXT: s_mov_b64 s[2:3], 0
1245 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1246 ; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0
1247 ; GFX9-NEXT: s_cbranch_scc0 .LBB9_4
1248 ; GFX9-NEXT: ; %bb.1: ; %else
1249 ; GFX9-NEXT: s_add_u32 s0, s8, s10
1250 ; GFX9-NEXT: s_addc_u32 s1, s9, s11
1251 ; GFX9-NEXT: s_andn2_b64 vcc, exec, s[2:3]
1252 ; GFX9-NEXT: s_cbranch_vccnz .LBB9_3
1253 ; GFX9-NEXT: .LBB9_2: ; %if
1254 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
1255 ; GFX9-NEXT: .LBB9_3: ; %endif
1256 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1257 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
1258 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
1259 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
1260 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
1261 ; GFX9-NEXT: s_endpgm
1262 ; GFX9-NEXT: .LBB9_4:
1263 ; GFX9-NEXT: ; implicit-def: $sgpr0_sgpr1
1264 ; GFX9-NEXT: s_branch .LBB9_2
1265 ;
1266 ; GFX10-LABEL: add64_in_branch:
1267 ; GFX10: ; %bb.0: ; %entry
1268 ; GFX10-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x24
1269 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
1270 ; GFX10-NEXT: s_cmp_lg_u64 s[8:9], 0
1271 ; GFX10-NEXT: s_cbranch_scc0 .LBB9_4
1272 ; GFX10-NEXT: ; %bb.1: ; %else
1273 ; GFX10-NEXT: s_add_u32 s0, s8, s10
1274 ; GFX10-NEXT: s_addc_u32 s1, s9, s11
1275 ; GFX10-NEXT: s_cbranch_execnz .LBB9_3
1276 ; GFX10-NEXT: .LBB9_2: ; %if
1277 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
1278 ; GFX10-NEXT: .LBB9_3: ; %endif
1279 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
1280 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
1281 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
1282 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
1283 ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
1284 ; GFX10-NEXT: s_endpgm
1285 ; GFX10-NEXT: .LBB9_4:
1286 ; GFX10-NEXT: ; implicit-def: $sgpr0_sgpr1
1287 ; GFX10-NEXT: s_branch .LBB9_2
1288 ;
1289 ; GFX11-LABEL: add64_in_branch:
1290 ; GFX11: ; %bb.0: ; %entry
1291 ; GFX11-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
1292 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1293 ; GFX11-NEXT: s_cmp_lg_u64 s[4:5], 0
1294 ; GFX11-NEXT: s_cbranch_scc0 .LBB9_4
1295 ; GFX11-NEXT: ; %bb.1: ; %else
1296 ; GFX11-NEXT: s_add_u32 s4, s4, s6
1297 ; GFX11-NEXT: s_addc_u32 s5, s5, s7
1298 ; GFX11-NEXT: s_cbranch_execnz .LBB9_3
1299 ; GFX11-NEXT: .LBB9_2: ; %if
1300 ; GFX11-NEXT: s_load_b64 s[4:5], s[2:3], 0x0
1301 ; GFX11-NEXT: .LBB9_3: ; %endif
1302 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1303 ; GFX11-NEXT: v_mov_b32_e32 v0, s4
1304 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
1305 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1306 ; GFX11-NEXT: s_nop 0
1307 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1308 ; GFX11-NEXT: s_endpgm
1309 ; GFX11-NEXT: .LBB9_4:
1310 ; GFX11-NEXT: ; implicit-def: $sgpr4_sgpr5
1311 ; GFX11-NEXT: s_branch .LBB9_2
1312 ;
1313 ; GFX12-LABEL: add64_in_branch:
1314 ; GFX12: ; %bb.0: ; %entry
1315 ; GFX12-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
1316 ; GFX12-NEXT: s_wait_kmcnt 0x0
1317 ; GFX12-NEXT: s_cmp_lg_u64 s[4:5], 0
1318 ; GFX12-NEXT: s_cbranch_scc0 .LBB9_4
1319 ; GFX12-NEXT: ; %bb.1: ; %else
1320 ; GFX12-NEXT: s_add_nc_u64 s[4:5], s[4:5], s[6:7]
1321 ; GFX12-NEXT: s_cbranch_execnz .LBB9_3
1322 ; GFX12-NEXT: .LBB9_2: ; %if
1323 ; GFX12-NEXT: s_load_b64 s[4:5], s[2:3], 0x0
1324 ; GFX12-NEXT: .LBB9_3: ; %endif
1325 ; GFX12-NEXT: s_wait_kmcnt 0x0
1326 ; GFX12-NEXT: v_mov_b32_e32 v0, s4
1327 ; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
1328 ; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1329 ; GFX12-NEXT: s_nop 0
1330 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1331 ; GFX12-NEXT: s_endpgm
1332 ; GFX12-NEXT: .LBB9_4:
1333 ; GFX12-NEXT: ; implicit-def: $sgpr4_sgpr5
1334 ; GFX12-NEXT: s_branch .LBB9_2
1335 entry:
1336 %0 = icmp eq i64 %a, 0
1337 br i1 %0, label %if, label %else
1339 if:
1340 %1 = load i64, ptr addrspace(1) %in
1341 br label %endif
1343 else:
1344 %2 = add i64 %a, %b
1345 br label %endif
1347 endif:
1348 %3 = phi i64 [%1, %if], [%2, %else]
1349 store i64 %3, ptr addrspace(1) %out
1350 ret void
1351 }
1353 ; Make sure the VOP3 form of add is initially selected. Otherwise pair
1354 ; of opies from/to VCC would be necessary
1355 define amdgpu_ps void @add_select_vop3(i32 inreg %s, i32 %v) {
1356 ; GFX6-LABEL: add_select_vop3:
1357 ; GFX6: ; %bb.0:
1358 ; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], s0, v0
1359 ; GFX6-NEXT: s_mov_b32 m0, -1
1360 ; GFX6-NEXT: ;;#ASMSTART
1361 ; GFX6-NEXT: ; def vcc
1362 ; GFX6-NEXT: ;;#ASMEND
1363 ; GFX6-NEXT: ds_write_b32 v0, v0
1364 ; GFX6-NEXT: ;;#ASMSTART
1365 ; GFX6-NEXT: ; use vcc
1366 ; GFX6-NEXT: ;;#ASMEND
1367 ; GFX6-NEXT: s_endpgm
1368 ;
1369 ; GFX8-LABEL: add_select_vop3:
1370 ; GFX8: ; %bb.0:
1371 ; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], s0, v0
1372 ; GFX8-NEXT: s_mov_b32 m0, -1
1373 ; GFX8-NEXT: ;;#ASMSTART
1374 ; GFX8-NEXT: ; def vcc
1375 ; GFX8-NEXT: ;;#ASMEND
1376 ; GFX8-NEXT: ds_write_b32 v0, v0
1377 ; GFX8-NEXT: ;;#ASMSTART
1378 ; GFX8-NEXT: ; use vcc
1379 ; GFX8-NEXT: ;;#ASMEND
1380 ; GFX8-NEXT: s_endpgm
1381 ;
1382 ; GFX9-LABEL: add_select_vop3:
1383 ; GFX9: ; %bb.0:
1384 ; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
1385 ; GFX9-NEXT: ;;#ASMSTART
1386 ; GFX9-NEXT: ; def vcc
1387 ; GFX9-NEXT: ;;#ASMEND
1388 ; GFX9-NEXT: ds_write_b32 v0, v0
1389 ; GFX9-NEXT: ;;#ASMSTART
1390 ; GFX9-NEXT: ; use vcc
1391 ; GFX9-NEXT: ;;#ASMEND
1392 ; GFX9-NEXT: s_endpgm
1393 ;
1394 ; GFX10-LABEL: add_select_vop3:
1395 ; GFX10: ; %bb.0:
1396 ; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0
1397 ; GFX10-NEXT: ;;#ASMSTART
1398 ; GFX10-NEXT: ; def vcc
1399 ; GFX10-NEXT: ;;#ASMEND
1400 ; GFX10-NEXT: ds_write_b32 v0, v0
1401 ; GFX10-NEXT: ;;#ASMSTART
1402 ; GFX10-NEXT: ; use vcc
1403 ; GFX10-NEXT: ;;#ASMEND
1404 ; GFX10-NEXT: s_endpgm
1405 ;
1406 ; GFX11-LABEL: add_select_vop3:
1407 ; GFX11: ; %bb.0:
1408 ; GFX11-NEXT: v_add_nc_u32_e32 v0, s0, v0
1409 ; GFX11-NEXT: ;;#ASMSTART
1410 ; GFX11-NEXT: ; def vcc
1411 ; GFX11-NEXT: ;;#ASMEND
1412 ; GFX11-NEXT: ds_store_b32 v0, v0
1413 ; GFX11-NEXT: ;;#ASMSTART
1414 ; GFX11-NEXT: ; use vcc
1415 ; GFX11-NEXT: ;;#ASMEND
1416 ; GFX11-NEXT: s_endpgm
1417 ;
1418 ; GFX12-LABEL: add_select_vop3:
1419 ; GFX12: ; %bb.0:
1420 ; GFX12-NEXT: v_add_nc_u32_e32 v0, s0, v0
1421 ; GFX12-NEXT: ;;#ASMSTART
1422 ; GFX12-NEXT: ; def vcc
1423 ; GFX12-NEXT: ;;#ASMEND
1424 ; GFX12-NEXT: ds_store_b32 v0, v0
1425 ; GFX12-NEXT: ;;#ASMSTART
1426 ; GFX12-NEXT: ; use vcc
1427 ; GFX12-NEXT: ;;#ASMEND
1428 ; GFX12-NEXT: s_endpgm
1429 %vcc = call i64 asm sideeffect "; def vcc", "={vcc}"()
1430 %sub = add i32 %v, %s
1431 store i32 %sub, ptr addrspace(3) undef
1432 call void asm sideeffect "; use vcc", "{vcc}"(i64 %vcc)
1433 ret void
1434 }
1436 declare i32 @llvm.amdgcn.workitem.id.x() #1
1438 attributes #0 = { nounwind }
1439 attributes #1 = { nounwind readnone speculatable }